JPS6026301B2 - 半導体集積回路の製造方法 - Google Patents

半導体集積回路の製造方法

Info

Publication number
JPS6026301B2
JPS6026301B2 JP52084322A JP8432277A JPS6026301B2 JP S6026301 B2 JPS6026301 B2 JP S6026301B2 JP 52084322 A JP52084322 A JP 52084322A JP 8432277 A JP8432277 A JP 8432277A JP S6026301 B2 JPS6026301 B2 JP S6026301B2
Authority
JP
Japan
Prior art keywords
insulating layer
semiconductor
layer
region
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52084322A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5310289A (en
Inventor
ミシエル・ザビ−ル・マリ−・ド・ブルビソン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JPS5310289A publication Critical patent/JPS5310289A/ja
Publication of JPS6026301B2 publication Critical patent/JPS6026301B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H10P76/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P14/61—
    • H10P14/662—
    • H10P50/283—
    • H10W10/0121—
    • H10W10/13—

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP52084322A 1976-07-15 1977-07-15 半導体集積回路の製造方法 Expired JPS6026301B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR7621646A FR2358748A1 (fr) 1976-07-15 1976-07-15 Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede
FR7621646 1976-07-15

Publications (2)

Publication Number Publication Date
JPS5310289A JPS5310289A (en) 1978-01-30
JPS6026301B2 true JPS6026301B2 (ja) 1985-06-22

Family

ID=9175756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52084322A Expired JPS6026301B2 (ja) 1976-07-15 1977-07-15 半導体集積回路の製造方法

Country Status (7)

Country Link
US (1) US4443933A (OSRAM)
JP (1) JPS6026301B2 (OSRAM)
CA (1) CA1094429A (OSRAM)
DE (1) DE2729973C2 (OSRAM)
FR (1) FR2358748A1 (OSRAM)
GB (1) GB1580657A (OSRAM)
NL (1) NL188668C (OSRAM)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers
JPS55163400A (en) * 1979-06-07 1980-12-19 Tokyo Sogo Keibi Hoshiyou Kk Liquid leak detection method in pipe line
US4443932A (en) * 1982-01-18 1984-04-24 Motorla, Inc. Self-aligned oxide isolated process and device
JPS58127374A (ja) * 1982-01-25 1983-07-29 Hitachi Ltd 半導体装置の製造方法
EP0093786B1 (de) * 1982-05-06 1986-08-06 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer planaren monolithisch integrierten Festkörperschaltung mit mindestens einem Isolierschicht-Feldeffekttransistor und mit mindestens einem Bipolartransistor
JPS5955052A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体集積回路装置の製造方法
EP0122313B1 (de) * 1983-04-18 1987-01-07 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem integrierten Isolierschicht-Feldeffekttransistor
NL188923C (nl) * 1983-07-05 1992-11-02 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4486266A (en) * 1983-08-12 1984-12-04 Tektronix, Inc. Integrated circuit method
US4569117A (en) * 1984-05-09 1986-02-11 Texas Instruments Incorporated Method of making integrated circuit with reduced narrow-width effect
US4663832A (en) * 1984-06-29 1987-05-12 International Business Machines Corporation Method for improving the planarity and passivation in a semiconductor isolation trench arrangement
US4669179A (en) * 1985-11-01 1987-06-02 Advanced Micro Devices, Inc. Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions
US4797372A (en) * 1985-11-01 1989-01-10 Texas Instruments Incorporated Method of making a merge bipolar and complementary metal oxide semiconductor transistor device
US4692344A (en) * 1986-02-28 1987-09-08 Rca Corporation Method of forming a dielectric film and semiconductor device including said film
US5023690A (en) * 1986-10-24 1991-06-11 Texas Instruments Incorporated Merged bipolar and complementary metal oxide semiconductor transistor device
DE3885658T2 (de) * 1987-06-11 1994-06-01 Fairchild Semiconductor Herstellung einer Halbleiterstruktur.
US5055417A (en) * 1987-06-11 1991-10-08 National Semiconductor Corporation Process for fabricating self-aligned high performance lateral action silicon-controlled rectifier and static random access memory cells
US6232232B1 (en) * 1998-04-07 2001-05-15 Micron Technology, Inc. High selectivity BPSG to TEOS etchant
US6660655B2 (en) * 1999-10-12 2003-12-09 Taiwan Semiconductor Manufacturing Company Method and solution for preparing SEM samples for low-K materials

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3576630A (en) * 1966-10-29 1971-04-27 Nippon Electric Co Photo-etching process
US3488564A (en) * 1968-04-01 1970-01-06 Fairchild Camera Instr Co Planar epitaxial resistors
BE758009A (fr) * 1969-10-27 1971-04-26 Western Electric Co Dispositif a impedance reglable pour circuit integre
JPS5012995B1 (OSRAM) * 1970-02-09 1975-05-16
US3708360A (en) * 1970-06-09 1973-01-02 Texas Instruments Inc Self-aligned gate field effect transistor with schottky barrier drain and source
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
US3748187A (en) * 1971-08-03 1973-07-24 Hughes Aircraft Co Self-registered doped layer for preventing field inversion in mis circuits
US3860466A (en) * 1971-10-22 1975-01-14 Texas Instruments Inc Nitride composed masking for integrated circuits
US3899363A (en) * 1974-06-28 1975-08-12 Ibm Method and device for reducing sidewall conduction in recessed oxide pet arrays
US3948694A (en) * 1975-04-30 1976-04-06 Motorola, Inc. Self-aligned method for integrated circuit manufacture
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers

Also Published As

Publication number Publication date
JPS5310289A (en) 1978-01-30
US4443933A (en) 1984-04-24
FR2358748A1 (fr) 1978-02-10
GB1580657A (en) 1980-12-03
NL188668B (nl) 1992-03-16
CA1094429A (en) 1981-01-27
NL188668C (nl) 1992-08-17
NL7707780A (nl) 1978-01-17
DE2729973A1 (de) 1978-01-19
DE2729973C2 (de) 1987-03-26
FR2358748B1 (OSRAM) 1978-12-15

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