JPS60258670A - Data transmission and reception method - Google Patents

Abstract

PURPOSE:To improve the efficiency of a system by dividing a common memory into at least two sections and allowing two devices to access each section at the same time. CONSTITUTION:A host device 22 refers to access information sent out of a subordinate device 23 to discriminate on a section which is not being accessed. When the 1st section 21a is not being accessed, the host device 22 stores commands and data to be stored in the 1st section respectively. The processor 23a of the subordinate device 23 discriminates that the host device 22 is not in process of access to the 1st section and reads the commands out of the command area of the 1st section. When the host device 22 writes next command and data in the common memory 21 during DMA transfer, the host device 22 discriminated on a section (2nd section 21b) which is not being accessed and writes them.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a data exchange method, and particularly relates to a data transfer method that can be commonly accessed from a host device, at least one computer-configured subdevice, and the host device and the subdevice. The present invention relates to a data transfer method for a system that has a shared memory and transfers data between a host device and a sub device via the shared memory.

<Prior Art> As shown in FIG. 1, there is a system in which data is exchanged between a host device 12 and a computer-configured subdevice 13 via a shared memory 11. According to this system, the sub-devices can share and execute predetermined processing based on commands from the host device, so that the load on the host device can be reduced. Now, in such a system, the host device 1
2 stores commands and data to be executed by the sub-device 13 in the command area 11a, data buffer section 11b of the shared memory 11, and the sub-device 13 executes a predetermined process based on the command. Write the result to the data buffer-1 section 11b of the shared memory 11,
The host device 12 reads the processing result from the shared memory. For example, when data is stored from the host device to a mass storage memory such as a disk or floppy of a sub-device, or when data is read from the mass storage memory, data for instructing read/write from the host device 12;
A command including information specifying the mass storage memory to be read/written is temporarily stored in the command area 11a of the shared memory, and then the processor of the sub-device 13 reads this information stored in the command area 11a, and then Under the control of the post-processing processor, data stored in the data buffer section 11b of the shared memory 11 is stored in the mass storage memory from the host device, or data is read from the mass storage memory. In other words, when writing from the host device to the NC device or NC data automatic creation device, the host device stores a write command, an I10 device specific command, and commands such as data length in the command area 11a of the shared memory. The NC program data is stored in the data buffer section 11b of the shared memory. After that, the sub-processor 'f113(r) reads command data from the command area 11a), and based on the instruction of the command data, reads the command data from the data buffer section 11b.
The NC program data is read from and sequentially stored in the empty area ζ of the disk.

On the other hand, when reading NC program data having a predetermined NC program number from the disk, the post device 12 writes commands such as a read command, a 110 device specific command, and the NC program number to the command area 11a of the shared memory 11. . Thereafter, the processor of the sub-device 13 reads command data from the command area 11a.

According to the data instructions, predetermined NC program data is read from the disk device and stored in the data buffer section 11b. Then, the host device 12 sequentially reads the NC program data from the data buffer section.

Although the above is a case of reading/writing data to/from a storage memory such as a disk or floppy disk, similar data exchange is also performed when a host device assigns and executes a predetermined process to a sub-device. Further, the sub device 13 is usually provided with a direct memory access controller (DMA controller), which controls data transfer between the data buffer section 11b of the shared memory and a mass storage memory such as a disk device. This is performed by the DMA controller, while the processor is free to perform other processing.

<Disadvantages of the prior art> However, in such a conventional system, when a sub device is accessing the shared memory 11, the host device cannot access the shared memory, and when the host device is accessing the shared memory, the sub device cannot access the shared memory 11. The device was unable to access the shared memory. Further, when the DMA controller was accessing the shared memory, neither the sub-device processor nor the host device processor could access the shared memory. For this reason, if a job requested from a host device to a subdevice takes a long time to execute, for example, if a large amount of data is stored in a mass storage device or if a large amount of data is read from a disk, the shared memory will be used for a long time. During this time, the host device cannot write the next command to the shared memory and must wait until the job (data transfer) is completed. Deadlocks occur frequently and for long periods of time, reducing system efficiency.

Also, when controlling data transfer between shared memory and storage devices such as disks using a DMA controller,
The processor of the sub-device is also unable to access the shared memory until the data transfer is completed, which also causes a decrease in system efficiency.

<Object of the Invention> An object of the present invention is to divide a shared memory into at least two partitions, configure each partition to be accessible at the same time, and connect two of the host device processor, sub device processor, and DMA controller. The purpose of the present invention is to provide a data exchange method that allows users to access each partition at the same time and improves the efficiency of the system.

Another object of the present invention is to provide a data exchange method that allows a host device to write the next command and data to the shared memory even when a sub device or a DMA controller is accessing the shared memory. It is with B.

Still another object of the present invention is to provide a data exchange method that allows a processor or a DMA controller of a sub-device to access a shared memory even when a host device is accessing the shared memory.

Another object of the present invention is to provide a data exchange method that allows a processor of a sub or host device to access the shared memory even when the DMA controller is accessing the shared memory.

<Summary of the Invention> In the data exchange method of the present invention, a shared memory is divided into at least two sections 1ζ, each section is configured so that two devices can access it simultaneously, and it is possible to determine which section is currently being accessed. , and writes commands and data to unaccessed partitions, or reads commands and data from unaccessed partitions, and sends and receives data between the host device and the subdevice. According to the invention of Party B, when a device is accessing the first partition, the other device can access the second partition. Even if there is a host device in the partition, the host device can immediately access another partition and write commands and data without waiting time as in the past, improving the efficiency of the system.

<Embodiment> FIG. 2 is a block diagram of a system according to the present invention. In the figure, 21 is a shared memory, and this shared memory is connected to the first and second two
It is divided into two sections 21'a and 21b, each having a command area CMA and a data buffer section BF. 2
2 is a host device, and 23 is a sub device. Sub device 23
is a processor 23a and an RO that stores a control program.
M23b and RAM that stores processing results and other data
23C, a DMA controller 23d, and a large capacity storage bag M (disk) such as a disk or floppy disk 23
e, a disk controller 23f, and a data input/output unit 23). Two spring lines Bl and B2 are connected to the processor 23a, and the first bus line Bit is R.
OM23 b, RAM23C1 data input/output crab unit 2
3g are connected respectively. Further, the first section 21a of the shared memory 21 is connected to the first bus line B1, and the second section 21b of the shared memory 21 is connected to the second bus line B2. Further, the disk controller 23f and the DMA controller roller 23d are connected to the first and second bus lines Bl and 8, respectively.
．． Connected to 2.

A processor (not shown) of the host device 22 connects to the bus line Bl'
, B2' to the first section 21a and second section 21b of the shared memory 21, and the host device 22 and the sub-device 23 are connected by a signal sB3, and information on which section is being accessed ( (Access information) is exchanged.

Now, when storing data from the host device 22 to the disk 23e, the host device 22 first refers to the access information sent from the sub device 23 via the signal *B3 and determines which partitions are not being accessed. If the first partition 21a is not currently being accessed, the host device 22 transfers commands and data to be stored to the command area CMk of the first partition and the data buffer section B via the bus l@Bl'.
Store each in F. Note that the host device 22 is connected to the signal line B.
3, the sub-device 23 is notified that the first partition 21a is being accessed, and that the access to the first partition 21a is terminated due to completion of data writing.

Thereafter, the processor 23a of the sub-device 23 determines whether the host device 22 is not accessing the first section via the data input/output unit 23g, and reads the command from the command area of the first section.

Then, based on the command, the DMA controller 23
The signal line B3 instructs the host device 22 to provide information indicating read/write distinction, the start address of the first section to be read/written, the data length, etc. Notify via.

As a result of the above, the DMA controller 23d outputs the address signal of the first section onto the first bus and writes the address signal of the first section of the shared memory.
The disk controller 2 reads data sequentially from the partitions.
3f, and the disk controller stores the data in a predetermined area of the disk 23e.

During this DMA transfer, the host device 22 makes all the following determinations, outputs the address signal of the second section onto the second bus, and outputs commands and data onto the bus to write into the second section. Note that when the processor 23a of the sub device 23 accesses the shared memory 21 during DMA transfer,
A partition that is not being accessed is determined and the partition is accessed.

Furthermore, when the host device 22 is accessing a predetermined section of the shared memory 21, when the sub device 23 accesses the shared memory 21, it similarly determines the section that has not been accessed by the host device 22 and determines the corresponding section. Access the parcel. In addition, the above data is stored in a disk device,
Alternatively, in the case of reading data from a disk device, the same is true when the host device causes a sub device to execute a predetermined job.

<Effects of the Invention> As explained above, according to the present invention, the shared memory is divided into at least two sections, and each section is configured so that two devices can access it at the same time. While a device is accessing one partition, other devices can access the other partition without waiting, allowing subdevices to efficiently execute short jobs and long jobs. can thus improve the efficiency of the system.

[Brief explanation of drawings]

FIG. 1 is a conventional system configuration diagram, and FIG. 2 is a system configuration diagram according to the present invention. 21... Shared memory, 21m... First section 21b.
...Second partition, 22...Host device, 23...Sub device, 23a"°°processor, 23d...DMA controller, 23e...Disk Patent applicant Fanuc Co., Ltd. agent Patent attorney Sen Saito General medical treatment) I21 leaf, 2) 7 1 ho

Claims (2)

[Claims] (1) A host device, at least one computer-configured subdevice, and a shared memory that can be commonly accessed by the host device and the subdevice, and data exchange between the host device and the subdevice via the shared memory. In the data exchange method of the system that performs
partition into two partitions, configure each partition so that it can be accessed simultaneously and read/write data, monitor which partitions are being accessed, and read/write data to partitions that are not being accessed. A data exchange method characterized by: (2) When a subdevice is provided with a direct memory access controller and one partition of the common memory is accessed via the direct memory access controller, the processor of the host device and the processor of the subdevice The data exchange method according to claim 1, wherein one of the partitions accesses the other partition and reads/writes data to the partition.