WO1985005709A1

WO1985005709A1 - Method of sending and receiving data

Info

Publication number: WO1985005709A1
Application number: PCT/JP1985/000318
Authority: WO
Inventors: Hajimu Kishi; Kunio Tanaka
Original assignee: Fanuc Ltd
Priority date: 1984-06-05
Filing date: 1985-06-05
Publication date: 1985-12-19
Also published as: JPS60258670A

Abstract

A method of sending and receiving data between two devices (22, 23) via a common memory (21) which consists of a first section (21a) and a second section (21b). When the host device (22) is accessing one section, the subordinate device (23) is allowed to access another section. The section which is being accessed is monitored. Commands and data are written onto the section that has not been accessed, or the commands and data are read out from the section that has not been accessed, so that the data are sent and received between the host device (22) and the subordinate device (23).

Description

- - Specification

Data transfer method

Technical field

The present invention relates to a method for exchanging data, in which a host device, a sub-device having at least one computer, a host device and a sub-device are commonly used. A data transfer method for a system having a shared memory capable of accessing the data in a host device and transmitting and receiving data between the host device and the sub device via the shared memory. About.

Background art

As shown in FIG. 1, a system for exchanging data between a host device 12 and a computer-configured sub device 13 via a shared memory 11 is shown in FIG. There is power. According to this system, the sub device can share and execute a predetermined process based on a command from the host device. The load can be reduced. Now, in such a system, the host device 12 shares commands and data to be executed by the sub device 13 in the shared memory 11. The command area 11a and the data buffer section 11b are respectively stored in memory, and the sub device 13 performs predetermined processing based on the command. After execution, the processing result is written into the data buffer section 11b of the shared memory 11, and the host device 12 reads the processing result from the shared memory. For example, data is stored from a host device to a large-capacity memory such as a disk or a floppy disk of a sub-device, or the large-capacity memory is stored. When reading data from the host A command containing data indicating read / write from the device 12 and information specifying the large-capacity memory to be read / written is shared. Command area 1 of the memory 11 1a, and then the information stored in the command area 11a is read by the processor of the sub-device 13. After that, the processor reads the information. The storage of the data stored in the data buffer section 11b of the shared memory 11 from the host device 12 into the large-capacity memory under the control of the processor. Or, read data from the large-capacity memory. For example, if the host device is an NC device or an automatic NC data creation device, the host device must be a line device when writing NC program data to the disk device. Command, a device-specific command, and data length and other commands are recorded in the command area 11a of the shared memory, and the NC program data is also stored. It is recorded in the data buffer section 11b of the shared memory. After that, the processor of the sub device 13 reads the command data from the command area 11a, and based on the command data, the data buffer. The NC program data is read from 1 lb of the disk unit, and is sequentially stored in the empty area of the disk.

On the other hand, when reading NC program data having a predetermined NC program certification from the disk, the host device 12 issues a read command and a read command. The IZO device specific instruction and the command such as the NC program number are written in the command area 11a of the shared memory 11. After that, the processor of the sub device 13 reads the command data from the command area 11a. In accordance with the instruction of the data, predetermined NC program data is read from the disk device and stored in the data buffer section 11b. Then, the host device 12 sequentially reads the NC program data from the data buffer section.

The above is the case of reading and writing data from and to memory such as a disk and a floppy disk. However, the host device shares predetermined processing with the sub device and executes the process. The same data transfer is also performed when this is done. Further, the sub device 13 is provided with a direct memory access controller (referred to as a DMA controller). The data transfer control of the large-capacity storage memory such as the data buffer section 11b of the memory 11 and the disk device is performed by the DMA controller π-controller. In the meantime, the processor can perform other processing.

However, in such a conventional system, when the sub device 13 is accessing the shared memory 11, the host device 12 is not connected to the shared memory. Cannot access the shared memory, and when the host device 12 accesses the shared memory 11 and the sub device 13 accesses the shared memory, the sub device 13 accesses the shared memory. I had ^five skills I could do. Furthermore, when the DMA controller has access to the shared memory 11 and accesses the shared memory 11, the processor 13 of the sub device 13 and the host device 12 2 Of the shared memory cannot access the shared memory.

For this reason, if the job executed from the host device 12 to the sub device 13 at the time of execution of the job is long, for example, if the data to be stored in the large-capacity memory is long, Or disk power If the data is long, the shared memory 11 is occupied for a long time to execute the job (data transfer), and during that time the host device is used. 12 cannot write the next command to the shared memory 11 and must wait until the job (data transfer) is completed. Deadlocks occur over the prosperity and over time, causing a decrease in the efficiency of the system.

When data transfer is controlled by the DMA controller using the shared memory 11 and a storage device such as a disk, the sub-device 13 pro- cessor is controlled. The processor is also unable to access the shared memory 11 until the data transfer is completed, which is a cause of a decrease in system efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to divide a shared memory into at least two sections and to make it possible to access each section at the same time. The processor and the DMA controller of the processor and the sub-device can be accessed at the same time for each partition. The purpose of the present invention is to provide a data transfer method capable of improving the efficiency of data transfer.

Disclosure of the invention

In the data transfer method according to the present invention, the shared memory is divided into at least two sections, and the host apparatus or the sub apparatus is provided in the first section. When you have access, configure devices that are not accessing the first partition to be able to access the second partition at the same time, and which partition is currently Monitor if it is being accessed and copy it to a non-accessed area. Write commands and data, or read commands and data from unaccessed sections and transfer data between the host device and the sub device. Give and receive. According to this invention, when one device has access to the first compartment, another device can access the second compartment, for example, Even if the DMA controller or sub-device is accessing the first partition, the host device will be as open as it used to be when waiting. The ability to quickly access another plot and write commands and data? And increase the efficiency of the system.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram of a conventional system, FIG. 2 is a diagram of a system according to a first embodiment to which the present invention is applied, and FIG. 3 is another embodiment of the present invention. This is the system configuration diagram.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 2 is a configuration diagram of a system according to the present invention. In the figure, 21 is a shared memory, and the shared memory is physically separated into first and second two sections 21a and 21b, each of which is a common memory. It has a data area CMA and a data buffer section BF. 22 is a host device and 23 is a sub device.

The sub-device 23 includes a processor 23a, a ROM 23b for storing a control program, and a RAM 2SC for storing processing results and other data. , DMA controller 23d, large-capacity storage devices (disks) such as disks and floppies 23e, and disk control devices 2 3 ί and data It has an input / output unit 23e.

The first section 2 la and the second section 2 lb of the shared memory 21 are respectively connected to the processor 23 a, the DMA controller 23 d and the disk via the bus line Bs. It is surrounded by the skim control device 23 f etc. Further, the first section 21a and the second section 2lb of the shared memory 21 are connected to a processor (not shown) of the host device 22 via a bus line Bii. The host device 22 and the sub-device 23 are connected by the signal line Be, and information on which section is accessed (access information). Perform the task.

When storing data from the host device 22 to the disk 23e, first, the host device 22 must be connected to the sub device 23 via the signal line Bc. Refer to the access information that has been sent from the server and determine the partition that is not in the access.

Now, assuming that the first section 21a is not being accessed, the host device 22 is placed on the address bus of the bus line Bh and the address of the first section 2la is located on the address bus. Command and data to be stored are sequentially output on the data bus together with the output of the data signal, and these are output to the command area CMA and data buffer of the first section 21a. Store them in section BF. Note that the host device 22 notifies the sub device 23 via the signal line Be that the first section 21a is being accessed, and terminates the data writing. This informs that the access to the first section 21a has been completed.

After that, the processor 23a of the support device 23 is a host device. It is determined via the data input / output unit 23e that the unit 22 is not accessing the first section 21a, and the command of the first section 21a is determined. Read the command from the command area CMA.

Based on the command, the processor 23a transmits to the DMA controller 23d information indicating the distinction between the read Z write and the read Z write. Command the start address of the first section 21a, the data length, etc., and confirm that the first section 21a is being accessed by the host device 22. Notify via signal line Be. One

From the above, the DMA controller 23 d subsequently reads out data sequentially from the first section 21 a using the space-time bus of the bus line B s, and The data is input to the disk controller 23f, and the disk controller stores the data in a predetermined area of the disk 23e. The same processing is performed when data is read from the disk 23e.

When the host device 22 writes the next command / data to the shared memory 21 during the DMA transfer, the host device 22 is connected to the signal line Be. Based on these data, the section that is not being accessed (second section 2 lb) is determined, and the second section 21b is put on the address bus of bus line Bli. Along with outputting the response signal, the command and data are output on the data bus and written to the second section 21b. When accessing the shared memory 21 of the processor 23 of the sub unit 23 during the DMA transfer, the partition not in the access is determined. To access the parcel. Further, when the host device 22 accesses a predetermined section of the shared memory 21, the sub device 23 accesses the shared memory 21. In the case of access, the host device 22 similarly determines a section that has not been accessed and accesses the relevant section. The above will store the data in the disk device 2 3 e, Oh Ru Iwade office click device but Ru Der When reading 2 3 _e or et ho be sampled apparatus 2 2 Gasa Bed The same applies to the case where the device 23 executes a predetermined job. Although the above description is an example in which the shared memory 21 is provided outside the sub device 23, the shared memory 21 may be provided inside the sub device.

FIG. 3 is a block diagram of another embodiment for realizing the present invention, and the same parts as those in FIG. 2 are denoted by the same reference numerals.

The difference between FIG. 3 and FIG. 2 is that the signal line B c in FIG. 2 has been deleted and the shared memory 21 has a bus switching control unit 21 c instead. It is. Note that the first partition 21a (called the first shared memory) and the second partition 2lb (called the second shared memory) depend on the RAM physically separated from each other. It is configured and has a capacity of, for example, 16 KB.

The bus switching controller 21c issues an access request earlier to each shared memory (21a, 2lb) of the host device 22 and the subdevice 23. Bus switching is performed with priority given to the device that has been set.

For example, if none of the devices is accessing the first shared memory 21a, the key of the first shared memory 21a is not detected. Bus switching is performed by giving priority to the device that first generates the dress signal. That is, if the host device 22 first generates an address signal of the first shared memory 21a, the bus switching control unit 21c will

(a) Database bus DBh and database bus DB1

(b) Address bus A Bh and address bus A B 1

(c) Connect the outlet port to the connection port C Bh and the connection port to the connection port C B1.

If the sub device 23 first generates an address signal for the first shared memory 21 a, the bus switching control unit 21 c

(a) Data bus D B s and data bus D B 1 閩,

(b) Address nodes A Bs and address nodes * A B 1

(c) Connect the control knobs * and the control knobs CB1 and CB1 respectively.

If one of the devices is accessing the first shared memory 21a, the bus switching control section 21c receives an access request from the other device. Also, no bus switching is performed.

Although the above description is for the first shared memory 21a, the same applies to the second shared memory 21b.

If one of the devices, for example, the sub device 23 is accessing the other shared memory, for example, the first shared memory 21a, the host device is accessed. Even if the address signal of the first shared memory 21 a is generated from the device 22, the first shared memory 21 a is not connected to the host device 22 ク. No session. The host device 22 cannot access the first shared memory 21a. Upon recognizing this, the address signal of the second shared memory 21b is generated on the address bus. Since the second shared memory 21b is not accessed by the sub device 23, the bus switching control unit 21c

(a) Data bus D Bh and data bus D B 2

(b) Address bus ABh and addressless, ♦

(c) Surrounding the control port CB h and the control bus CB 2 urugi, connecting the host device 22 to the second shared memory 21 b Get access.

As a result, the first shared memory 21a and the second shared memory U21b are simultaneously accessed by the sub device 23 and the host device 22, respectively. That is, while one device is accessing one shared memory, the other memory is able to access another shared memory, and the latency is the same as before. No longer required. Although the shared memory 21 is provided outside the sub device 23 in FIG. 3, the shared memory may be provided inside the sub device 23.

As described above, according to the present invention, the shared memory can be separated into at least two partitions, and different devices can access each of them at the same time. With this configuration, even if a certain storage device is being accessed in one partition, the other device can access the other partition without waiting time. It is possible to efficiently execute short jobs and long jobs as sub-units, thereby improving the efficiency of the system. I can do it.

Claims

The scope of the claims

1, Shared with the host device, at least one computer-configured sub device, and the host device and the sub device can be accessed in common In a method of transmitting and receiving data between the host device and the sub device via the shared memory, the shared memory has a small number of shared memories. It is divided into at least two partitions, and at the same time, each partition is accessed so that data can be read and written, and which partition is accessed A data transfer method that specializes in monitoring data and reading and writing data to unaccessed partitions.

2 * The data transfer method according to claim 1, wherein the two partitions are made up of two physically separated memories.

3. The data transfer method according to claim 1, wherein the method waits for the shared memory to be built in a sub device.

4. If one partition is being accessed by one device, take advantage of the fact that the other device cannot access that partition, and use the other device to access the other device. Claim 2, recognizing that the compartment is being accessed by another device, and specializing in accessing the other compartment. Data transfer method 0

5, A direct 'memory' access controller is provided in the sub unit, and the direct memory access controller is provided. Access to one partition of common memory via the During this time, one of the host device's processor and the sub device's processor accesses the other partition and reads and writes data to that partition. The data transfer method described in claim 1 which features this.