JPH0754494B2 - Asynchronous data transfer control device - Google Patents

Description

The present invention relates to a control device that is interposed between a higher-level device and a lower-level device and controls asynchronous data transfer performed between the two devices by a transfer route whose data transfer rate is not unique. Asynchronous data transfer between a host device and a lower device with a transfer route that is not unique at the data transfer rate, with the aim of providing a control device that enables asynchronous data transfer between a device and a lower device with optimal control. In the control device, a transfer control information table that stores the data transfer speed, the amount of processed data, etc. of each transfer route, a buffer memory that stores the transfer data, and a transfer at the time of optimal control on each transfer route based on the transfer control information Transfer start timing calculation means for calculating the start timing and combination with a corresponding transfer route at one transfer start timing It was provided with a transfer control means for transferring data in the buffer memory, configured to perform optimal control for asynchronous data transfer.

[Industrial application field]

The present invention relates to a control device used in an asynchronous data transfer system, and in particular, a control that is interposed between a higher-order device and a lower-order device and controls asynchronous data transfer performed between the two devices by a transfer route whose data transfer rate is not unique. Regarding the device.

[Conventional technology]

There are a synchronous data transfer method and an asynchronous data transfer method as a data transfer method of a system in which a control device is interposed between an upper device and a lower device, and the data transfer between both devices is controlled by this control device.

In the case of the synchronous data transfer method, the data transfer speeds of the upper device and the lower device are the same, and the upper device and the lower device simultaneously start the data transfer process via the control device,
At the same time, the data transfer process ends. Therefore, the synchronous data transfer method is used when the data transfer rates of the upper device and the lower device are equal.

On the other hand, in the case of the asynchronous data transfer method, the data transfer rates of the upper device and the lower device do not have to match, and the data transfer process between the upper device and the control device can be separated. is there. Therefore, the asynchronous data transfer method is used when the data transfer rates of the upper device and the lower device are different.

Next, with reference to FIG. 4, the principle of the asynchronous data transfer control system by the control device between the upper device and the lower device will be described.

In FIG. 5, reference numeral 21 is a host device such as a host CPU, which is capable of high-speed data transfer processing and has a high-speed data transfer route.

A lower device 22 such as a magnetic disk has a lower data transfer rate than the upper device 21 and a lower data transfer rate on the transfer route.

A control device 23 has a buffer memory 231 for storing transfer data therein, and controls the asynchronous data transfer between the upper device 21 and the lower device 22 by interposing the buffer memory 231 therein.

In this configuration, when transferring data from the upper device 21 to the lower device 22, the control device 23 once stores the data received from the upper device 21 in the buffer memory 23, and then reads it at the data transfer speed of the lower device 22 side. Transfer to the lower device.

When transferring data from the lower device 22 to the upper device 21,
The control device 23 stores the data read from the lower device in the shared buffer memory 231 and then interrupts the upper device 21 to read the data in the buffer memory 231 at the data transfer speed of the upper device 21 side and then to the upper device. Transfer to.

In this case, optimal control is performed so that data transfer from the lower device 22 to the upper device 21 is performed most efficiently.

That is, when a certain amount of data from the lower device 22 is accumulated in the buffer memory 231, the upper device 21 is interrupted, the data in the buffer memory is transferred to the upper device 21, and the lower device 22 outputs the buffer memory 231. Buffer memory for the host device 21 at the end of writing a specified amount of data to
The transfer of the data in 231 is completed. As a result, the most efficient data transfer can be performed.

[Problems to be solved by the invention]

As described above, the conventional asynchronous data transfer control method performs the optimum control so that the data transfer is performed most efficiently.

However, the optimum control in the conventional asynchronous data transfer control method is practically possible when the data transfer rates of the upper device and the lower device side are uniquely determined. Therefore, in the case of a system in which a higher-order device and a lower-order device exist in a reciprocating manner, it is necessary that each higher-order device side has the same data transfer rate and each lower-order device side also has the same data transfer rate.

Therefore, there is a problem in that the optimum control in the conventional asynchronous data transfer control method cannot be realized in the case of a system in which the data transfer rates of the transfer routes of the upper device side and the lower device side are different from each other.

That is, in such a system, it is not possible to determine the optimum data transfer rate that is common to the transfer routes of each upper device and each lower device, and each upper device can transfer data between arbitrary lower devices. Is possible, and
This is because the transfer route is not unique and the data transfer rate generally changes each time the transfer route changes.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a control device capable of optimally controlling asynchronous data transfer between a higher-level device and a lower-level device by a transfer route whose data transfer rate is not unique.

[Means for solving problems]

FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, 11a and 11b are upper devices, 12a and 12b are lower devices, and 111a, 112a, 111b and 112b are upper devices 11a and 11b, respectively.
Etc. channels. 13 is a control device, which is a higher-level device 11a, 11
It is interposed between b and the like and lower devices 12a, 12b and the like to control asynchronous data transfer between both devices.

In the control device 13, 131 is a transfer control information table,
It stores information necessary for data transfer control, such as the data transfer speed of the upper devices 11a and 11b and the lower devices 12a and 12b, and the amount of processed data.

132 is a buffer memory in which transfer data is temporarily stored.

Reference numeral 133 is a transfer start timing calculation unit, and based on the data transfer control information in the transfer control information table 131, each transfer route when the data in the buffer memory 132 is transferred by each transfer route of the instructed upper device and lower device. The transfer start timing at the time of optimum control in is calculated.

A transfer control unit 134 transfers the data in the buffer memory 132 in combination with the corresponding transfer route at one transfer start timing calculated by the transfer start timing calculation unit 133.

[Work]

Now, the operation of the present invention will be described by taking as an example the case where the lower device 12a is accessed and data is read from the upper device 11a via the respective transfer routes of the channels 111a and 112a.

The upper device 11a issues an access request to the lower device 12a to the control device 13 via the channel 111a or 112a.

The transfer control means 134 of the control device 13 accesses the lower device 12a based on the command of the received access request and stores the data read from the lower device 12a in the buffer memory 132.
To store.

On the other hand, the transfer control information table 131 stores in advance (for example, at the time of program loading) the channel of each upper device and the data transfer speed of each lower device, and the processing data amount designated by the access request command is transferred. It is stored by the control means 134.

The transfer start timing calculation unit 133 transfers the data in the buffer memory 132 to the higher-level device 11a by each transfer route via the channel 111a or 111b based on the information on the data transfer rate and the processing data amount in the transfer control information table 131. In this case, the transfer start timing at the time of optimum control in each transfer route is calculated (a specific calculation method will be described in the section of the embodiment).

The transfer control unit 134 transfers the data in the buffer memory 132 to the higher-level device 11a in combination with the corresponding transfer route at one transfer start timing calculated by the transfer start timing calculation unit 133. This processing is performed as follows, for example.

Now, it is assumed that the transfer start timing of the transfer route of the channel 111a is earlier than the transfer start timing of the transfer route of the channel 112a.

First, when the transfer start timing of the transfer route of the channel 111a is approached, an interrupt for coupling to the channel 111a is performed. When the channel 111a receives the interrupt, the data transfer is performed under the optimum control by the transfer route.

If the interrupt is not received by the channel 111a, the channel 112a is interrupted and coupled when the transfer start timing of the transfer route of the channel 112a approaches, and the data transfer is performed by the optimal control by the transfer route of the channel 112a. .

As a result, the data transfer is performed by optimal control by being coupled to the transfer route of either channel 111a or 112a.

As described above, even if the data transfer rate in each transfer route between the upper device and the lower device is not unique, asynchronous data transfer between each upper device and the lower device can be performed by optimal control.

Further, until the transfer start timing is reached, the control device and the host device (channel) are in a non-coupled state and the respective processes can be performed, so the load on the host device (channel) can be reduced. At the same time, the throughput of the entire system can be improved.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. FIG. 2 is an explanatory view of the configuration of an embodiment of the present invention, and FIG.
The figure is an operation timing chart of the embodiment.

(A) Configuration of Embodiment In FIG. 2, upper devices 11a, 11b, etc., lower devices 12a, 12b.
The control device 13, the transfer control information table 131, the buffer memory 132, the transfer start timing calculation unit 133, the transfer control means 134, the channels 111a, 112a, 111b, 112b, etc. are as described in FIG. The transfer start timing calculation unit 133 (133a, 133b, etc.) is provided separately for each device control unit described later.

The upper devices 11a and 11b are host CPUs in this embodiment, and the lower devices are devices such as magnetic disks.

In the transfer control means 134, 135a, 136a, 135b, 136b, etc.
The channel control unit connected to each of the channels 111a, 112a, 111b, 112b, etc., accepts access requests from the corresponding channels, issues commands to the device control unit connected to a predetermined lower-level device, and accepts interrupts from the device control unit. , And controls data transfer between the channel and the buffer memory 132.

137a, 137b and the like are device control units corresponding to the lower devices 12a, 12b, etc., respectively, internally provided with transfer start timing calculation units 133a, 133b, and receiving commands from the channel control unit to the corresponding lower devices. Access control, data transfer control between the lower device and the buffer memory 132, and interrupt processing for the channel control unit based on the transfer start timing calculated by the transfer start timing calculation unit.

138 is a common bus for each channel control unit 135a, 136a, 135b, 13
6b and the like, device control units 137a and 137b and the like, the transfer control information table 131 and the buffer memory 132 are commonly connected.

It is possible to collectively provide the transfer start timing calculation units 133a, 133b and the like at one location outside each device control unit. However, since the transfer start timing calculation units 133a and 133b are separately provided for each device control unit, the transfer start timing calculation process is performed. Can be speeded up.

(B) Operation of Embodiment Referring to the operation timing chart of FIG. 3, the operation of the embodiment will be described in which the lower device 12a is accessed from the upper device 11a via the channels 111a and 112a to read data. Will be described as an example. The upper device 11a is a host computer, and the lower device 12a is a magnetic disk device.

Next, the content of each code used in the following description will be described.

M _B: capacity of the buffer memory 132 S _ca1: data rate of the channel 111a S _ca2: data rate of the channel 112a S _cb1: data rate of the channel 111b S _cb2: data rate of the channel 112b S _Da: lower apparatus 12a Data transfer rate S _Db : Data transfer rate of lower device 12b P: Processed data amount T _sa1M (or T _sa1P ): Data amount M _B (or P−M _B ) is transferred with optimum control on the transfer route of channel 111a transfer start timing T _Sa2M when (or _T sa2P): transfer start timing T _Ca1M of transferring at optimum control amount of data M _B (or P-M _B) in the transfer route of the channel 112a (or T _CA1P): channel 111a data amount M _B at a transfer route (or P-M _B) channel processing time required for transferring the T _CA2M (or _T ca2P): amount of data transfer route of the channel 112a M _B (or P-M _B) Channel processing time required to transfer T _DaM (or T _DaP ): Device processing time required to transfer the data amount M _B (or P-M _B ) at the data transfer rate of the lower device 12a DT _a1M (or DT _a1P ): Transfer start timing T _sa1M (or T
_sa1P ), the amount of data stored in the buffer memory DT _a2M (or DT _a2P ): transfer start timing T _sa2M (or T
amount of data stored in the buffer memory in _Sa2P) Here, the data transfer rate S _Ca1 channel 111a is a data rate S _{Ca @ 2} is smaller than the channel 112a. That is, S _Ca1 <S _Ca2 .

Further, it is assumed that the processing data amount P is larger than the buffer memory capacity M _B (from the description of the operation when P> M _B , the operation when P ≦ M _B can be easily understood).

The operation of the embodiment will be described below according to the order in which the processes are executed.

The upper device 11a sends an access request to the lower device 12a via the channel 111a (or 112a) to the control device 13a.
To the channel control 135a (or 136a). In the access request command, data transfer control information such as the type of processing to be requested (type of reading processing or writing processing) and the amount of processing data P (number of bytes or number of records) is specified.

The channel control unit 135a (or 136a) stores the data transfer control information such as the processing type and the processing data amount P in the received access request command in the transfer control information table 131 via the common bus 138.

On the other hand, in the transfer control information table 131, when the program is loaded into the control device 13, each channel 111a, 112a, 11
Data transfer rates (S _Ca1 , S _Ca2 , S _Cb1 , S _Cb2 , S _Da , S _Db, etc.) of 1b, 112b, etc. and each lower device 12a, 12b, etc. are read from an external storage area (not shown). It is stored in advance.

As this external storage area, an area that can retain information even after the power is turned off, such as a hard disk or a floppy disk, is used.

The channel control unit 135a (or 136a), upon completion of the above-described access request acceptance processing, the channel 111a (or 112a)
And it becomes a non-bonded state.

The channel control unit 135a (or 136a) instructs the device control unit 137a to read the predetermined processing data amount P from the lower device 12a.

The device control unit 137a accesses the lower-level device 12a, positions it in a predetermined address area, and
The storage of data is started (at time t _{0 in} FIG. 3).

At the same time, from the transfer control information table 131, the data transfer rates S _Ca1 and S _{Ca2 of} the channels 111a and 112a, the lower device 1
The data transfer speed S _{Da and the} processing data amount P of 2a are read and sent to the transfer start timing calculation unit 132a together with the buffer memory capacity information M _B to calculate the transfer start timing.

The transfer start timing calculation unit 133a determines the size relationship between the processing data amount P and the buffer memory capacity M _B. If P> M _B , first, the data transfer for the buffer memory capacity M _B is performed by optimal control. The transfer start timings (T _sa1M and T _sa2M ) for the channels 111a and 112a are calculated.

To transfer optimal control data transfer of the buffer memory capacity M _B min, M _B of data data M _B fraction from the lower unit 12a in this embodiment from the time the buffer memory 132 stored in the buffer memory 132 Transfer start timings S _sa1M and S _sa1M and S
_{Select sa2M} .

Therefore, in the case of the channel 111a, the following equation (1) is established by using the channel processing time T _ca1M .

M _B = S _ca1 × T _ca1M = S _Da × (T _sa1M + T _ca1M ) ... (1) From this, T _Sa1M is obtained from the following equation (2).

T _sa1M = M _B / S _Da −M _B / S _ca1 = T _DaM −T _ca1M (2) That is, T _sa1M is the channel processing time T of the channel 111a.
_ca1M (M _B / S _ca1 ) and device processing time T of lower device 12a
It can be obtained from the difference of _DaM (= M _B / S _Da ).

The amount of data stored in the buffer memory 132 during this T _sa1M , that is, the amount of data read from the lower device 12a (D
T _a1M ) is _calculated by the following equation (3).

_{DTs a1M} = T _sa1M × S _Da ) = (1-S _Da / S _ca1 ) × M _B (3) Similarly, between the transfer start timing T _sa2M and this T _sa2M during optimum control in the case of channel 112a. In buffer memory 132
The amount of data DT _a2M stored in is _calculated in the following (4) and (5).
It is calculated from each.

T _sa2M = T _DaM -T _ca2M = M _B / S _Da -M _B / S _ca2 (4) Here, T _ca2M is the channel processing time of the channel 112a.

Since _{DT a2M = (1-S Da} / S ca2) × M B ...... (5) The T _Sa1M and DT _A1M (or T _Sa2M and DT _a2M) is of equivalent contents, as the transfer start timing, T _sa1M (T
_{Either sa2M} ) or _DTa1M ( _DTa2M ) can be used.

Clearly, T _sa1M <T _sa2M , DT _a1M <DT _a2M .

The device control unit 137a is a transfer start timing calculation unit.
Referring to each transfer start timing calculated in 133a, first, transfer start timing T _sa1M (or DT
_a1M ), a level "0" interrupt is _issued to the channel control units 135a and 136a.

It should be noted that this interrupt prompts the processing to the channel control units 135a and 136a, and does not have to be a level interrupt.

When the level is “0”, the channel control unit 135a is checked with priority. When the channel control unit 135a first detects an interrupt, the channel control unit 135a immediately detects the interrupt.
Interrupt the 6a interrupt processing, performs binding processing with the channel 111a, initiates the transfer of data of the lower device 12a in the buffer memory 132 (t ₁ point of FIG. 3).

Thus, M _B of data transfer end timing (FIG. 3 of the t ₂ time), the device control unit 137a and a channel control unit 13
It becomes almost the same in 5a, and data transfer is performed by optimal control.

The channel control unit 136a uses the channel 1 at the timing of T _sa1M.
Since it is not necessary to combine with 12a, interrupt processing for level "0" is not performed.

If a level "0" interrupt occurs, the channel controller 135a
If the interrupt cannot be accepted during other processing, the device control unit 137a, when approaching the transfer start timing T _sa2M (or DT _a2M ) of the next channel 112a, to the channel control units 135a and 136a, Performs a level "1" interrupt.

When the interrupt level is "1", the channel control unit 136a is checked with priority. When the channel control unit 136a detects this level "1" interrupt, it interrupts the level "0" processing and accepts the interrupt.

At the same time, the interrupt processing of the channel control unit 135a is immediately interrupted, the connection processing with the channel 112a is performed, and the transfer of the data of the lower device 12a in the buffer memory 132 is started (at time t ₁ ′ in FIG. 3). the data transfer end timing of M _B component becomes substantially simultaneously by the device control unit 137a and the channel control unit 136a,
It becomes equal to the data transfer end timing t _{2 in} the case of the channel control 135a described above.

When the buffer memory capacity M _B of data transfer is completed, the channel control unit 135a (or 136 performing the data transfer
The channel a) becomes uncoupled again with the channel 111a (or 112a).

On the other hand, the read data from the lower device 12a is continuously stored in the buffer memory 132 by the device control unit 137a.

If the processing data amount P is _{P = N · M B + X} (N is a positive integer), if it is, repeated N times operation - as described above, N + 1 th moves to the next.

The transfer start timing calculation unit 133a determines each transfer start timing (T _sa1p ) when the transfer of the remaining processing data amount (P−M _B ) is optimally controlled via the channels 111a and 112a.
And T _sa2p ).

In the aforementioned (2) and (4), P-M _B instead of M _B
By using T _sa1p and T _sa2p , the following (6) and (7) are obtained.

T _sa1p = T _Dap −T _ca1p = (P−M _B ) / S _Da − (P−M _B ) / S _ca1 (6) T _sa2p = T _Dap −T _ca2p = (P−M _B ) / S _{Da - (P-M B)} / S ca2 ...... (7) where, T _Dap, T _CA1P and T _Ca2p, the amount of transfer data (P
When it is -M _B), a channel processing time of the device processing time of the lower unit 12a and the channel 111a and the channel 112a.

Clearly, T _sa1p <T _sa2p , DT _a1p <DT _a2p .

Also, since T _sa1p and DT _a1p (or T _sa2p and DT _a2p ) have the same contents, the transfer start timing is T
_sa1p (T _sa2p) or _DT a1p (DT _a2p) of any that can be used is similar to the case of transferring the above-mentioned M _B.

The device control unit 137a is a transfer start timing calculation unit.
Referring to each transfer start timing calculated in 133a, the same processing as described above is performed, and the channel control units 135a and 136a.
To transfer the data of (P-M _B ) to the upper device 11a.

That is, the transfer start timing T of the channel 111a
_{When sa1p} (or DT _a1p ) is approached, a level “0” interrupt is performed and the channel control unit 135a attempts data transfer (time t _{3 in} FIG. ₃ ).

If the channel control unit 135a does not _{perform the} interrupt process, the device control unit 137a performs the level "1" interrupt when the transfer start timing T _sa2p (or DT _a2p ) of the channel 112a is approached, and the channel control unit 137a Attempt data transfer by 136a (time t ₃ ′ in FIG. ₃ ).

As a result, in both of the channel control units 135a and 136a, data transfer by optimal control is performed, and at the same time point t ₄ (see FIG. 3), the data transfer of P-M _B remaining in the buffer memory 132 is performed. finish.

Incidentally, when the processing amount of data P is P <M _B, the operation at a P instead of P-M _B in, or operation at the P instead of M _B is performed in ~.

The embodiment has been described above in which the higher-level device 11a accesses the lower-level device 12a via the channels 111a and 112a, but the higher-level device 11a also accesses other lower-level devices via the channels 111a and 112a. Even when another higher-level device accesses an arbitrary lower-level device, data transfer can be performed by optimal control in the same manner.

Further, it can be similarly performed when there are more than two channels. In that case, the higher the transfer start timing, the higher the interrupt level is selected.

〔The invention's effect〕

As described above, according to the present invention, the following various effects can be obtained.

(A) Even if the data transfer rate in each transfer route between the upper device and the lower device is not unique, asynchronous data transfer between each upper device and the lower device can be optimally controlled.

(B) Until the transfer start timing is reached, the transfer routes of the control device and the host device are in a non-coupling state, and each process can be performed, so the load on the host device can be reduced and the throughput of the entire system can be reduced. Can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention, FIG. 2 is an explanatory diagram of a configuration of an embodiment of the present invention, FIG. 3 is an operation timing chart of the same embodiment, and FIG. 4 is a conventional asynchronous data transfer. It is explanatory drawing of a control system. In FIGS. 1 and 2, 11a, 11b ... Upper device, 12a, 12b ... Lower device, 13 ... Control device, 111a, 112a, 111b, 112b ... Channel, 131 ... Transfer control information table, 132 …… Buffer memory, 133,133
a, 133b ... Transfer start timing calculation unit, 134 ... Transfer control means.

Claims (2)

[Claims] 1. A high-order device (11a, 11b, etc.) and a low-order device (12a, 1)
2b, etc.), and in an asynchronous data transfer control device that controls asynchronous data transfer performed between both devices by a transfer route whose data transfer rate is not unique, (a) Upper device (11a, 11b, etc.) ) And subordinate devices (12a, 12b
Etc.), a transfer control information table (131) that stores information necessary for data transfer control such as the data transfer speed and the amount of processing data of each transfer route, and (b) a buffer memory (132) that stores the transferred data. ), And (c) each transfer when data in the buffer memory (132) is transferred by each transfer route of the instructed upper device and lower device based on the data transfer control information in the transfer control information table (131). A transfer start timing calculation unit (13) for calculating a transfer start timing at the time of optimal control in the route
3) and (d) transfer control means (134) for transferring the data in the buffer memory (132) in combination with the corresponding transfer route at one transfer start timing calculated by the transfer start timing calculation section (133), An asynchronous data transfer type control device comprising: 2. A transfer start timing calculated by a transfer start timing calculating section (133) is a time required for transferring a processing data amount at a data transfer rate of a higher device side transfer route and a lower device side transfer route data transfer. The difference between the time required to transfer the processing data amount at a speed or the amount of data stored in the buffer memory (132) at the time difference is defined. Control device for asynchronous data transfer.