JPH03156560A - Inter-processor data communication equipment - Google Patents

Abstract

PURPOSE:To reduce the processing burden of a processor and to improve processing speed by accessing a data buffer by each processor without executing a processing to read out the status of the data buffer. CONSTITUTION:When a buffer 13 is set in a 'filled-up' state, a processor 11 generates a write command to the buffer 13. This command is detected by a write wait time control part 15 and a write wait signal is asserted and transmitted to the processor 11. According to this signal, the processor 11 prolongs the write wait time. When the buffer 13 is made 'empty', the write wait signal is negated and data write to the buffer 13 is started. In another form, when the buffer 13 is 'empty' and a processor 12 tries to read out data, such a state is detected by a control part 16 and a read wait signal is asserted and transmitted to the processor 12. According to this signal, the processor 12 prolongs the read wait time. When the buffer 13 is filled up, the read wait signal is negated and data read from the buffer 13 is started.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an inter-processor data communication device for transferring data between processors in, for example, a multiprocessor system.

The purpose of this invention is to eliminate the need for a processor to read the status of a data buffer, thereby improving processing efficiency and further increasing data communication speed.

A transfer source processor, a transfer destination processor, a buffer that mediates data transfer between these processors, a buffer control unit that monitors the "empty" and "full" status of this buffer, and a transfer destination processor's The write waiting time control unit that performs control to extend the write waiting time is jlq l.
li, i L, when the buffer is full, when the source processor issues an h-write command to the buffer, the latency time control unit prolongs the write latency of the source processor until the buffer becomes "empty." Purchased to be controlled by.

[Industrial Application Field 1] The present invention relates to an inter-processor data communication device for transferring data between processors in, for example, a multiprocessor system.

In recent years, as computer systems have become faster.

Faster data communication between processors is also required. In particular, when transferring data on large sparrows, it is necessary to be able to do so at high speed and with a small burden on the processor.

[Prior Art 1] A conventional inter-processor data communication device for transferring data between processors is shown in FIG. In the figure, l is the processor (CPU) of the data transfer source.

2 is a data transfer destination processor (CPU), 3 is a data buffer that mediates data transfer between processors 1 and 2, and 4 is a processor that monitors the empty state and full state of data buffer 3. This is a buffer control section that outputs a buffer empty signal BE to the processor 1 and a buffer full signal BF to the processor 2.

The operation of this conventional device will be explained below with reference to the time chart of FIG. processor l to processor 2
A case where data is transferred via the header data buffer 3 will be described. The buffer control section 4 monitors the state of the data buffer 3, and changes the buffer empty signal BE and buffer full signal BF to 0/1 depending on the state. Now, assuming that the data buffer 3 is in the "empty" state, the data buffer empty signal BE is "l".
Then, the buffer full signal BF is set to "0".

Processor l reads this buffer empty signal BE as a status, and if it is 'l', the data buffer 3 is 'empty' (ie, data buffer 3 is 'empty').

(Writing is possible) and writes the data to the data buffer 3. On the other hand, the processor 2 reads the buffer full signal BF as a status, which is "O".
', then data buffer 3 is empty (i.e.,
4), and data is not read from the data buffer 3.

When the processor 1 writes data to the data buffer 3, the data buffer 3 becomes "full to 1", so the buffer control unit 4 outputs the buffer empty signal BE.
°0" and the buffer full signal I3F to "1"'. In this case, if the buffer empty status is "0", the processor l indicates that the data buffer 3 is full (that is, writing is not possible). On the other hand, if the buffer full status is "1", the processor 2 recognizes that the data buffer 3 is full (that is, reading is possible). ) and reads data from the data buffer 3.

When the processor 2 reads data from the data buffer 3, the buffer control unit 4 again sets the buffer empty signal BE to "1-" and sets the buffer full signal BF to "0".
``''. Thereafter, by repeating this operation, data transfer from processor 1 to processor 2 is performed sequentially.

[Problems to be Solved by the Invention] In the conventional inter-processor data communication device, the transfer source processor 1 and the transfer destination processor 2 are as follows.

When loading and reading data 4 from data buffer 3,
Always have buffer empty signal BE and buffer full signal B.
It is necessary to read F as a status and determine whether or not reading V is possible based on the status.

This processing increases the number of processing steps in each processor 1.2 and increases the processing time of the h processor, which hinders speeding up data transfer.

In addition, in such a data communication system, if the speed difference between both processors (t is the software speed difference) is large,
The slower processor has less need to read the status of the data buffer. For example, the source processor l
If the write speed of the destination processor 2 is sufficiently faster than the read speed of the destination processor 2, the data buffer 3 will almost always be in the "full" state, so the destination processor 2 will be able to read the data in most cases. , there is almost no need to read the status of the buffer full signal BF from the buffer control section 4.

However, in conventional devices in such cases, the slower processor always reads the status of data buffer 3 before accessing data buffer 3, so additional transfer processing is required for this status reading process. This results in a delay, and the waiting time of faster processors also increases accordingly, resulting in a problem that the overall processing efficiency deteriorates.

Therefore, an object of the present invention is to eliminate the need for a processor to read the status of a data buffer, thereby improving processing efficiency and further increasing data communication speed.

[T steps to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

An inter-processor data communication device according to the present invention.

As one form, the processor 11 of the transfer source.

The transfer destination processor 12 and these processors 11.
12, a buffer control unit 14 that monitors the "empty" and "full" states of this buffer 13, and a controller that controls the extension of the 1g waiting time of the transfer source processor 11. Waiting time control unit 15
When the buffer 13 is full, when the source processor 11 issues an old-fill command to the buffer I3, the source processor 13 continues to operate until the buffer 13 becomes empty.
The inflow waiting time control unit 15 is configured to perform control so as to extend the M inflow waiting time of l.

An inter-processor data communication device according to the present invention.

As another form, a transfer source processor 11, a transfer destination processor 12, a buffer 13 that mediates data transfer between these processors 11. and a read latency control unit 16 that performs control to extend the read waiting time of the transfer destination processor 12. buffer 13 when
The read wait time control circuit 1 extends the read wait time of the transfer destination processor 12 until the transfer destination processor 12 reaches the "full" state.
6 is configured to perform control.

[Effect] Now, when the buffer 13 is "full" (i.e.

Assume that the processor 11 issues a write command in an attempt to write three data into the buffer 13 when the data cannot be written. Then, the write waiting time control unit 15 writes the buffer 1
It detects that 3 is [full] and that a write command signal is issued, asserts (enables) the S write wait signal, and sends 1 to the processor 11. Processor 11 thereby extends the write time (disciplinary cycle).

When buffer 13 becomes "empty", the sneak wait signal is negated (disabled), thereby ending the extended write latency.

Insertion of data 1 into the buffer 13 is started.

Similarly, in another embodiment of the present invention, if the processor 12 attempts to read when the buffer 13 is "empty", the read waiting time control unit 15 determines that the buffer 13 is "empty" and the read command (5 detects that a signal has been issued,
The read wait signal is asserted (enabled) and transmitted to the processor 12. Processor 12 thereby lengthens the read latency (read cycle). Buffer 13
When becomes "full," the read wait signal is negated (disabled), thereby ending the extended read wait time and starting reading data from the buffer 13.

[Example] The present invention will be described in detail below with reference to nine drawings.

FIG. 2 shows an inter-processor data communication device as an embodiment of the present invention. In the figure, 1 is a transfer source processor, 2 is a transfer destination processor, 3 is a data buffer, and 4 is a buffer control unit, each of which has the same function as that described in relation to the prior art.

Reference numeral 5 denotes a write wait control section, into which the write command signal W from the processor l and the buffer empty signal BE from the buffer control section 4 are input, and based on these, the write wait signal WW is generated and the write wait signal WW is sent to the processor. l
is configured to provide. Further, 6 is a read weight control unit, into which the read command signal R from the processor 2 and the buffer full signal BF from the buffer control unit 4 are input, and based on these, a read weight No. 13 RW is generated and given to the processor 2. It is configured like this.

Reference numeral 7 denotes a data transmission request unit, which is a circuit that interrupts the processor 2 by starting the processor 1 when a data transmission request is issued from the processor 1 to the processor 2. Further, 8 is a memory for storing transfer data of the processor 1, and 9 is a memory for storing transfer data of the processor 2.

Now, assume that data is transferred from processor 1 to processor 2. The processor 1 first activates the data transmission request unit 7, notifies the processor 2 of the transmission request by interrupt, and starts data transfer using the data buffer 3. Here, if there is a difference in processing speed between processor 1 and processor 2, processing is performed in two ways: primary.

(A) First, the case where the 3-input speed of processor 1 is faster than the readout speed of processor 2 will be described.

Processor I loads the data read from memory 8 into data buffer 3 in the conventional manner. That is, the processor 1 reads the status of the buffer empty signal BE, confirms that it is "l" (that is, data can be edited), and then writes the data read from the memory 8 into the data buffer 3. It's crowded.

On the other hand, the processor 2 outputs the read command signal R to the data buffer 3 without performing the process of reading the status of the buffer full signal BF of the buffer control unit 4.

It is now assumed that data δ has not yet been written into the data buffer 3 and it is "empty". A buffer full signal BF and a read signal R are both input to the read weight control section 6. This read weight control pusher 6 is
Data buffer 3 is “empty” (i.e. buffer full signal B
If it detects that F is "°°O" and readout is not possible) and that the readout signal R is being output, it asserts (enables) the readout wait signal RW and transmits it to the processor 2.The processor 2 weight 13
While the signal RW is asserted, the read cycle (that is, the read waiting time: the time from when a read command is issued until the read actually starts) is extended, and the read operation is not started.

When data writing to the data buffer 31 is completed, the buffer full signal BF of the buffer control unit 4 is turned on.
1"'. Then, the read wait control circuit 6 detects this and negates (disables) the read wait signal [<W. As a result, the extended read cycle ends γ. , reading from the data buffer 3 is started.

Eighteen pieces of read data are stored in the memory 9.

In this method, since the data read speed of the processor 2 is slow, in most cases it is possible to start reading as soon as the read command is issued, but if the data buffer 3 is empty When an attempt is made to read data, the read wait control section 6 asserts the read wait signal RW, thereby extending the read cycle of the processor 2 until the data buffer 3 is in a readable state.

(B) Next, the processor [of,! A case where the read speed of the processor 2 is slower than the read speed of the processor 2 will be described.

When the processor l attempts to write three data into the data buffer 3, it outputs the write command signal W to the data buffer 3 without performing the process of reading the status of the buffer empty signal BE. If data buffer 3
Buffer empty signal B because data is clogged in
When E is “0”, the 3-input weight control unit 5 uses the buffer empty signal BE and the write signal W to
It is detected that the data buffer 3 is "full" and the old write signal W is output, and during that time, the write wait signal W
asserts W to signal processor l, thereby interrupting processor l's interrupt cycle (i.e., Q interrupt latency:
The time period from when a write command is issued until the actual start of divination is extended to prevent divination from starting.

When the contents of the data buffer 3 are read and become "empty," the buffer empty signal BE becomes "1-," which causes the old weight signal WW of the waste weight control section 5 to
negate. As a result, the prolonged stay cycle of processor l is completed, and a write operation is started.

On the other hand, the reading process of the processor 2 is performed in the same manner as before. That is, the processor 2 reads the status of the buffer full signal BF, confirms that it is "1"' (that is, readable), and then transfers the data buffer 3 to the data buffer 3.
Read data from.

Note that even in the case (A) described above, the write cycle of the processor 1 on the write side is controlled by the write wait control circuit 5.
It is also possible to control the length to be extended. However, since the read speed of the processor 2 is slow, the write cycle is extended by the write wait signal WW on the write side until the read operation is completed on the read side, and other processing by the processor 1 is performed during that time. Since the processing speed of processor l will decrease, it is more efficient for processor l to write using the conventional method.

The same applies to case (B), and in this case, it is desirable that the processor 2 side performs reading using a conventional method.

[Effect of the Invention 1 According to the present invention, each processor can access the data buffer without performing processing to read the status of the data buffer, thereby reducing the processing load on the processor and further increasing the processing speed. This greatly contributes to speeding up data communication. In particular, when there is a difference in processing speed between the transfer source and transfer destination processors, the optimal transmission f-stage can be selected by software, further improving the processing efficiency of the entire device, and reducing the amount of data between processors. It is possible to further speed up communication.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing an inter-processor data communication device as an embodiment of the present invention. FIG. 3 is a block diagram 9 showing a conventional inter-processor data communication device. FIG. 4 is a diagram showing a time chart of a conventional device. In fig. 1.2...Processor 3...Data buffer 4...Buffer control section 5...Write wait control section 6...Read wait control section 7...Data transmission request section 8.9... Memory failure 111: related principle explanatory diagram 1st

Claims (1)

[Claims] 1. A processor (11) serving as a transfer source; a processor (12) serving as a transfer destination; a buffer (13) that mediates data transfer between these processors; A buffer control unit (14) that monitors the status of “empty” and “full” and a write latency control unit (15) that performs control to extend the write latency of the transfer source processor (11), When the buffer (13) is “full”, the transfer source processor (
11) when there is a write command to the buffer (13), the write wait time control unit extends the write wait time of the transfer source processor (11) until the buffer (13) becomes "empty". (15) An inter-processor data transfer device configured to perform control. 2. A processor (11) that is a transfer source, a processor (12) that is a transfer destination, a buffer (13) that mediates data transfer between these processors, and whether the buffer (13) is empty or full. a buffer control unit (14) that monitors the state of the transfer destination processor (12), and a read latency control unit (16) that performs control to extend the read latency time of the transfer destination processor (12), When “empty”, the destination processor (
12) to the buffer (13), the read wait time control unit (12) extends the read wait time of the transfer destination processor (12) until the buffer (13) becomes "full". 16) an inter-processor data communication device configured to perform control.