JPH0743663B2 - Data transfer controller - Google Patents

Description

The present invention relates to a data transfer control device for performing data transfer between a main memory device and an extended memory device by block transfer at the same transfer speed.

[Prior Art] In a supercomputer that performs large-scale scientific and technological calculations, the scale of the target program also becomes large, and it is difficult to store all the necessary data in the main storage device. In addition, a large-capacity extended storage device that is capable of high-speed transfer is provided.

However, since the extended storage device is composed of dynamic RAM, it requires several times as much read time as the main storage device. Conventionally, in this kind of data transfer between a main memory device and an extended memory device, in order to accept a main memory access request from a high-speed processing device during transfer, the transfer data is divided into fixed blocks, and the blocks are divided into multiple blocks. High-speed transfer was possible by performing transfer continuously. To this end, the extended storage control circuit is provided with buffers for reading data from the main storage device and for reading data from the extension storage device, each of which has a capacity equivalent to the size of a block, and temporarily stores transfer data to store the transfer data. It was designed to transfer data in synchronization with the device and the extended storage device.

[Problems to be Solved by the Invention]

However, in the above-described extended storage control circuit for performing data transfer between the main storage device and the extended storage device, the size of the block for data transfer is set in the case of the transfer from the main storage device to the extended storage device and from the extended storage device. This is the same as in the case of transfer to the main memory, and therefore the capacity of the main memory read data buffer and the capacity of the extended memory read data buffer are also the same. The transfer block needs to be large enough for continuous data transfer for each block, and the block size is set according to the data transfer from the extended storage device to the main storage device. Therefore, the size of the block is the same when data is transferred from the main storage device to the expansion storage device, which has a shorter read time than the expansion storage device, and there is a drawback that a large capacity main storage read data buffer is required. .

In view of the above drawbacks, the technical problem of the present invention is to provide a data transfer control device capable of high-speed data transfer without increasing the capacity of the main memory data buffer.

[Means for Solving the Problem] According to the present invention, a main memory read data buffer for temporarily storing main memory data read from a main memory, and an extended memory having a response time for reading longer than that of the main memory. Data transfer control for block-transferring the main storage data and the extension data between the main storage device and the extension storage device via the extension storage read data buffer that temporarily stores the extension data read from the device In the device, the buffer size and transfer block size of the main memory read data buffer are smaller than the buffer size and transfer block size of the extended memory read data buffer, and the number of data transfers during main memory read is the data during extended memory read. A data transfer control device that is larger than the number of transfers can be obtained.

[Embodiment] A data transfer control device of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of a data transfer control device according to an embodiment of the present invention, including peripheral devices.

This data transfer control device, in accordance with a vector-calculated data transfer request from the high-speed arithmetic processing device 2, connects the main memory between the main memory 3 storing main memory data and the expanded memory 4 storing expanded data. It comprises a system controller 1 for performing block transfer of data and extended data at the same transfer rate. Here, regarding the peripheral device, a high-speed and large-capacity one is used as the main storage device 3, and a high-speed and large-capacity one is used for the expansion storage device 4 to store data that cannot be stored in the main storage device 3. In addition, the high-speed arithmetic processing unit 2 can independently make a main memory access request to the main memory 3.

The system control device 1 includes a request acceptance control circuit 6 that accepts a main memory access request from the high-speed arithmetic processing device 2 and a request for data transfer between the main storage device 3 and the extended storage device 4, and the request acceptance control circuit 6 A data transfer control circuit 8 for controlling data transfer between the main storage device 3 and the extended storage device 4 in response to a request for data transfer from the main storage device 3, and a main memory reading for temporarily storing main storage data read from the main storage device 3. A main memory read data buffer circuit 9 as a data buffer, and an extended memory read data buffer for temporarily storing extended data read from the extended memory 4 whose response time to read is longer than that of the main memory 4. A buffer circuit 10,
The main memory control circuit 7 controls the main memory device 3 in response to a main memory access request from the request acceptance control circuit 6 and a data transfer request from the data transfer control circuit 8.

Of these, the data transfer control circuit 8, the main memory read data buffer circuit 9, and the extended memory data buffer circuit 10 collectively constitute the extended memory control circuit 5, and the buffer size and transfer in the main memory read data buffer circuit 9 The block size is smaller than the buffer size and transfer block size in the extended storage data buffer circuit 10. Further, the number of data transfers when reading the main memory is larger than the number of data transfers when reading the extended memory.

Next, regarding the operation of the embodiment, a time chart of data transfer from the extended storage device 4 to the main storage device 3 of FIG. 2 and a time chart of data transfer from the main storage device 3 to the extension storage device of FIG. It demonstrates using. In FIG. 2, when a data transfer request from the extended storage device 4 to the main storage device 3 is accepted from the high-speed processing unit 2, the data transfer control circuit 8 requests the extended storage device 4 to read the first block transfer 100. -1 is sent. Then, the data transfer control circuit 8 receives the first extended storage read data 102-10 after the response time T0 of the extended storage device 4 has elapsed, and stores it in the extended storage data buffer circuit 10.

Then, the data transfer control circuit 8 reads the data in the extended storage data buffer circuit 10 if the main storage device 3 is in the writable state, and the first main storage write data 202-10
Is sent to the main memory device 3 through the main memory control circuit 7, and at the same time, a read request 100-2 for the second block transfer is sent to the extended memory device 4. In this way, data transfer is performed from the extended storage device 4 to the main storage device 3, and the transfer block L0 from the extended storage device 4 includes the last read data 102-1n of the first block transfer and the second block transfer. The response time T0 of the extended storage device 4 determines that the first read data 102-20 is continuous, and the capacity of the extended storage data buffer circuit 10 is the same as that of the transfer block L0.
Next, in FIG. 3, when a data transfer request from the main storage device 3 to the expansion storage device 4 is accepted from the high-speed arithmetic processing unit 2, the data transfer control circuit 8 sends the data to the main storage device 3 through the main storage control circuit 7. The read request 200-1 for the second block transfer is transmitted. Then, the data transfer control circuit 8
Receives the first main memory read data 201-10 after the response time T1 of the main memory device 3 has elapsed and stores it in the main memory data buffer circuit 9.

Then, the data transfer control circuit 8 reads the data in the extended storage data buffer circuit 9 if the extended storage device 4 is in the writable state, and then reads the first extended storage write data.
At the same time that 101-10 is sent to the expanded storage device 4, a read request 200-2 for the second block transfer is sent to the main storage device 3 through the main storage control circuit 7.

In this way, the data transfer from the main memory 3 to the extended memory 4 is performed, and the transfer block L1 from the main memory 3 is transferred.
Is the last read data 201-1n of the first block transfer.
And the first read data 201-20 of the second block transfer
Is determined by the response time T1 of the main memory device 3, and the capacity of the main memory data buffer circuit 9 becomes the same as that of the transfer block L1. Therefore, since the response time T1 of the main memory 3 is smaller than the response time T0 of the extended memory 4,
In data transfer from the main memory 3 to the expanded memory 4,
Even if the transfer block L1 from the main storage device 3 is smaller than the transfer block L0 from the extended storage device 4, high-speed data transfer can be performed by increasing the number of block transfers.

〔The invention's effect〕

As described above, according to the data transfer control device of the present invention, the buffer size and transfer block size of the main memory read data buffer at the time of main memory read from the main memory device are set to the extended memory read from the extended memory device. Since it is made smaller than the buffer size and transfer block size of the extended storage read data buffer at the time, and the number of data transfers at the time of main memory read is made larger than the number of data transfers at the time of extended storage read,
Even if the capacity of the main storage data buffer is reduced, high speed data transfer can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a data transfer control device according to an embodiment of the present invention including peripheral devices, and FIG. 2 is a time chart of data transfer from an extended storage device 4 to a main storage device 3. , FIG. 3 is a time chart of data transfer from the main storage device 3 to the expansion storage device 4. 1 ... System control unit, 2 ... High-speed processing unit, 3 ...
Main memory, 4 ... Extended memory, 5 ... Extended memory control circuit, 6 ... Request acceptance control circuit, 7 ... Main memory control circuit, 8 ... Data transfer control circuit, 9 ... Main memory data buffer Circuit, 10 ... Extended storage data buffer circuit.

Claims (1)

[Claims] 1. A main memory read data buffer for temporarily storing main memory data read from a main memory device, and temporary storage for extended data read from an extended memory device having a response time for reading longer than that of the main memory device. In the data transfer control device for block-transferring the main memory data and the extended data at a same transfer rate between the main memory device and the extended memory device via the extended memory read data buffer, the main memory read data buffer Buffer size and transfer block size are smaller than the buffer size and transfer block size of the extended storage read data buffer, and the number of data transfers during main memory read is greater than the number of data transfers during extended storage read. And a data transfer control device.