JPH0415490B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a device equipped with a plurality of ports that can access memory simultaneously based on access by a processor (MP), a large capacity buffer memory for storing fetch data from the memory is provided. , and an address register in which the processor can store a write destination address for the buffer memory, so that when the processor (MP) accesses the memory, the write destination for the buffer memory is determined in accordance with the access port number. By simply writing the address to the above address register, at the end of the memory access, the data fetched by the memory access is transferred to the buffer memory address where the data should be written by accessing the address register based on the port number. , and writes the fetch data from the area of the address in the buffer memory.

[Industrial application field]

The present invention relates to a memory access method in a device equipped with a plurality of ports (A to D) that can access memory simultaneously based on access by a processor (MP), and a buffer memory that stores fetch data from the memory.

With the recent spread of computer systems, the amount of data to be processed has increased, and efficient execution of data processing has become required.

However, with the recent remarkable progress in semiconductor technology, the speed of processor MP has been increased.
On the other hand, as the capacity of memory is increasing, the burden on memory access from the processor is becoming heavier.

In particular, in a computer system that has multiple devices, each of which has multiple memory access ports that can access memory simultaneously, a specific job executed by a device may be executed by one of the ports. , even if you try to access memory using a free port, if all ports are busy, the fetch data stored in the port is fetched in response to the memory access requested by another job, and then the new job is executed. In the case where multiple memory accesses have to be performed and the buffering capacity is limited by the number of ports, there is a problem that the access frequency increases and the overhead in the processor (MP) increases.

In addition, if memory access is performed from multiple devices or multiple ports at the same time, the order of responses to each memory access cannot be guaranteed, so the access port must be fixed for a specific job. There is a problem that cannot be done.

Under these circumstances, there has been a demand for a system that can effectively perform fetch access to memory even in computer systems equipped with a plurality of memory access ports.

[Conventional technology]

FIG. 2 is a diagram illustrating a conventional memory access method.

First, when a memory access request is sent from the processor (MP) 1 of the device, a port control section (not shown) searches for an empty port number and returns the port number to the processor (MP) 1.

When the processor (MP) 1 performs memory access controlled by the selector (SEL 50), memory access information (for example, data, address, command, etc.) is set in the port based on the received port number. and starts the memory request control unit (MRC) 31.

In the memory request control unit (MRC) 31,
A memory access request number (ID) is added to the memory access information and sent to the memory control unit (MCU) 3 to access a main storage device (memory) not shown.

When the fetch data is returned from the main storage device (memory) together with the memory access request number (ID), the memory request control unit (MRC)
31, the port number of the access request source is recognized based on the memory access request number (ID), and the fetch data is stored in a fixed capacity buffer memory provided in the port (A to D) 2.

After that, the fetish data is sent to the selector (SEL)
51 to the processor (MP) 1 at a specific write timing (WT).

[Problem that the invention seeks to solve]

Therefore, in the conventional method, when a memory access is made from the processor (MP) 1, the fetch data corresponding to the memory access is stored at the port (A) selected when the processor (MP) 1 performs the memory access. ~D) Since it is stored only for 2, the relevant processor (MP) 1
In order to import the data, it was necessary to know the port number at the time of the memory access.

Also, since the number of memory access ports (A to D) 2 provided for each processor (MP) 1 is limited, the maximum number of memory access ports (A to D) 2 provided for each processor (MP) 1 is (A~
D) Fetch data can only be buffered by the fixed capacity buffer area provided in port 2, so even if there is a lot of fetch data from a certain job and a new memory access request occurs immediately, each port (A to D) When processor (MP) 2 is busy, it is necessary to import fetch data stored in each port into each job, resulting in an increase in overhead in processor (MP) 1.

In addition, the above memory access ports (A to D) 2
For example, since it is shared by multiple jobs executed on processor (MP) 1, when a certain job tries to acquire a free port, it is not necessarily possible to acquire the same port. When focusing on a specific job executed on MP) 1, there was a problem in that the captured port could not be determined.

Furthermore, in this computer system, since memory is accessed by multiple devices, there is a problem that the order of responses cannot be guaranteed for memory accesses from specific jobs executed by each processor (MP) 1. From this, when focusing on a specific job in each processor (MP),
There was a problem that the ports that could be captured could not be identified. This increases the burden on the processor for memory access.

In view of the above conventional drawbacks, the present invention provides a memory system in which the storage location of fetch data is floated with respect to the ports in a device equipped with a plurality of memory access ports, and the ordering of responses to memory accesses is not guaranteed. The purpose is to provide a method for improving the performance of processor MP when using processor MP.

[Means for solving problems]

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the present invention, in a device equipped with a plurality of ports (A to D) that access memory simultaneously based on an access request from a processor (MP) 1, a buffer memory 42 that stores fetch data from the memory, and It is provided with an address register 41 for storing the write destination address of the fetch data into the buffer memory 42 in units of the two ports (A to D) selected by the processor (MP) 1, based on a memory access request from the processor MP1. Then, at the start of the memory access, the selected port (A to D)
Set the memory access information to the port indicated by the number (RQPN), and select the port (A to A) selected above.
A memory access is performed by setting the write address of fetch data in the address register 41 indicated by the number (RQPN) in D), and when the memory access is completed, the recognized port is set in response to the response from the memory to the memory access. Based on the number (CPNO), a predetermined amount of fetch data is stored in the buffer memory 42 indicated by the write address of the fetch data obtained by accessing the address register 41, and the processor (MP) 1 , the fetch data stored in the buffer memory 42 is accessed using the write address set above to obtain the fetch data.

[Effect]

That is, according to the present invention, in a device equipped with a plurality of ports that can access memory simultaneously based on access by a processor (MP), a large-capacity buffer memory that stores fetch data from the memory; By providing an address register in which the processor can store a write destination address for the buffer memory, when the processor (MP) accesses the memory, the write destination address for the buffer memory can be stored in accordance with the access port number. , just write to the address register, and at the end of the memory access, the data fetched in the memory access accesses the address register based on the port number,
Since the address of the buffer memory where the data is to be written is recognized and the fetch data is written from the area of the address in the buffer memory, the storage location of the fetch data can be made floating with respect to the port. This has the effect of improving the performance of the processor (MP) when using a memory system that does not guarantee the order of responses to memory accesses from the processor (MP).

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
In FIG. 1, the same reference numerals as in FIG. 2 indicate the same objects, and address register 41, buffer memory 42, and related mechanisms are functional blocks necessary to implement the present invention.

First, when accessing memory from processor (MP) 1 through free ports (A to D) 2,
Port number is port number register (RQPN) 6
The address register 41 is accessed by the port number set to 0, and the address where the fetch data is to be stored is written in the area corresponding to the port (A to D) 2, and the selector (SEL) 50 is Controlled by the output of the port number register (RQPN) 60, memory access information (data, addresses, commands, etc.) is stored in the ports (A to D) 2, and the memory request control unit (MRC) 31 is activated. . For example, the amount of fetch data in one memory access is determined by the above command.

In the memory request control unit (MRC) 31,
When a memory access request from each port (A to D) 2 is recognized, a memory access request number (ID) is added to the memory access and sent to the memory control unit (MCU) 3.

In the memory control unit (MCU) 3,
After performing conflict control with memory access from other devices, such as channel devices, when memory access from the processor (MP) 1 is selected,
A main storage device (memory) (not shown) is accessed, and the fetch data returned together with the memory access request number (ID) is sent back to the memory request control section (MRC) 31 described above.

When the memory request control unit (MRC) 31 recognizes the port number (CPNO) corresponding to the memory access request number (ID), it
~D) By storing the fetch data in 2 and accessing the address register 41 based on the port number (CPNO), the buffer memory 4 corresponding to the port (A to D) 2 is stored.
The fetch data write address at No. 2 is read out, and the buffer memory 42 is accessed based on the address.

At this time, depending on the above port number (CPNO),
When the selector (SEL) 51 is controlled and the corresponding port (A to D) 2 is selected, the aforementioned fetch data is read out at a specific write timing WT, and is determined from the aforementioned write address of the buffer memory 42 by the aforementioned command. A predetermined amount of data is stored.

Therefore, as shown in the figure, when the processor (MP) 1 performs memory access, the fetch data can be read from the buffer memory 42 at the buffer memory address specified by the processor (MP) 1, unlike the conventional system. There is no need to be aware of port numbers, and the burden on memory access can be reduced.

Furthermore, by increasing the capacity of the buffer memory 42, it is possible to increase the amount of buffering of fetch data required by each job executed by the processor (MP) 1, thereby reducing the frequency of memory access requests. , the performance of the processor (MP) 1 can be improved.

In this way, in the present invention, when performing memory access in a device equipped with a plurality of memory access ports, when an empty port is captured, the address of the buffer memory that the user wants to use is stored in the address register based on the port number. The feature is that by writing data into the buffer memory, subsequent readout of the fetch data is possible using the address of the buffer memory, regardless of the port number.

〔Effect of the invention〕

As explained above in detail, the memory access method of the present invention stores fetch data from the memory in a device equipped with a plurality of ports that can access the memory simultaneously based on the access by the processor MP. By providing a large-capacity buffer memory and an address register in which the processor can store a write destination address for the buffer memory, when the processor (MP) accesses the memory, it By simply writing the write destination address for the buffer memory into the address register, when the memory access ends, the data fetched in the memory access is accessed based on the port number and the data is fetched. Recognizes the buffer memory address to write to,
Since the fetch data is written from the address area of the buffer memory, the fetch data storage location can be floating with respect to the port, and the order of responses to memory access from the processor (MP) can be changed. This has the effect of improving the performance of the processor (MP) when using a memory system that does not guarantee performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram illustrating a conventional memory access method. In the drawing, 1 is a processor (MP), 2 is a port (A to D), 3 is a memory control unit (MCU), 31 is a memory request control section (MRC), and 4 is a memory control unit (MCU).
1 is an address register, 42 is a buffer memory,
50 and 51 indicate selectors (SEL), respectively.

Claims (1)

[Claims] 1. In a device equipped with a plurality of ports (A to D) 2 that access memory simultaneously based on an access request from a processor (MP) 1, a buffer memory 42 stores fetch data from the memory. Then, the address where the fetch data is written to the buffer memory 42 is set to the port A~ selected by the processor (MP) 1.
and an address register 41 that is stored in units of D2, and based on a memory access request from the processor (MP) 1, at the start of the memory access, the number of the selected port (A to D) 2 is stored.
Set memory access information to port (A to D) 2 specified by RQPN, and
~D) Set the write address of the fetch data in the address register 41 indicated by the number 2 (RQPN) and perform memory access, and when the memory access ends, recognition is performed in response to the response from the memory to the memory access. A predetermined amount of fetch data is stored in the buffer memory 42 indicated by the write address of the fetch data obtained by accessing the address register 41 based on the port number (CPNO) obtained by the processor (MP). 1 is a memory access control device characterized in that the buffer memory 42 is controlled so as to access the fetch data stored in the buffer memory 42 at the set write address and obtain the fetch data.