JPS60254238A - Data extraction processor - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware and to increase the processing speed of a data extraction processor by defining the contents of a RAM main body part, a latch part equivalent to 2p bytes and a data register as data which are extracted by different memory accesses. CONSTITUTION:A data extraction processor used for instruction word processing, etc. is provided with a main memory 1, a RAM2 of the (4 words X 4 bytes) capacity that incorporates a latch part equivalent to 4 bytes, a data register 3, a switch 4 which switches alternately the reading and writing actions of the RAM2, a RAM access mechanism 6 which performs write/read of the RAM2, a main memory access control mechanism 7, an alignment device 8, a residual indicator 5, etc. The mechanism 7 transfers the 16-byte data within the RAM2 every 4 bytes in 4 times and stores them in the main memory 1. While the device 8 stores the 4-byte data directly to the register 3 and extracts them.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data extraction processing device used for command word processing and the like.

(Prior art) A conventional data extraction processing device used for instruction word processing, etc. has an instruction word buffer of at least 3p bytes for the minimum required instruction word of p (positive integer) bytes, and reads it from a storage device. The output 2p bytes of data are stored in this buffer, and if there is free space of p bytes or more, the subsequent 2p bytes of data are read out and the instruction word buffer is left-justified at the same time. In an instruction word buffer of 1 or 3p bytes or more that stores 2p bytes of data, left shifting by p or 2p bytes requires a huge amount of connection wiring, selection circuits, and selection control circuits.

In addition, other conventional data extraction processing devices have a 2p byte instruction word buffer and a register file of m (positive integer) x 2p bytes for the minimum required p byte instruction words, and The word buffer reads and stores consecutive 2p bytes from a desired position in the register file, and when the register file is used up and less than p bytes of data remain, the instruction word of 2p bytes is read only for these p bytes. The data is stored in the first half p bytes of the buffer, and when the register file becomes empty, the next memory access is performed to request continuous m words x 21) bytes of data from the storage device, and storage in the register file begins. At the stage where the data is stored or when the storage is completed, the first p bytes of data are taken out from the register file and stored in the latter p bytes of the instruction word buffer to obtain a 2p byte instruction word.

This device has the disadvantage that the next memory access cannot be made until the data in the register file is used up.
From the time the first half p bytes are stored in the instruction word buffer until the second half p bytes are stored and 2p bytes of valid data are available, the hardware is occupied and high-speed transfer processing cannot be performed. There are drawbacks.

(Object of the Invention) An object of the present invention is to provide a data extraction processing device that eliminates the above-mentioned drawbacks.

(Structure of the Invention) The device of the present invention includes first and second storage means each having a capacity of 2p (p is a positive integer) bytes, and m (positive integer) storage areas, each of which has a capacity of 2p (p is a positive integer) bytes. a first storage means each having a capacity of 2p bytes; a switching means for alternately switching between a read operation and a write operation for the first storage means at a predetermined period; and during the write operation period. A write address is supplied to the first storage means and the second
During the read operation period, a read address is supplied to the first storage means to store p bytes or 2p bytes of read data in the first storage means. an access means, a memory access means for transferring (2pxm) bytes of data in the second storage means m times in units of 2p bytes and storing it in the first storage means; alignment means for storing 2p bytes of data directly or by exchanging upper p bytes and lower p bytes in the second storage means; desired p bytes of the new (2pxm) bytes of data to be stored from the second storage means into the first storage means by the memory access means; and display means for displaying that the data currently stored in the first storage means is valid for transferring the data to the alignment means.

(Example) Next, the present invention will be described in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, this embodiment shows the following:
Built-in main memory 1 and latch section for 4 bytes, 4 words x
Readable and writable memory with a capacity of 4 bytes (
(hereinafter referred to as RAM) 2, data register 3, and read data from AM3 at half the cycle of one machine cycle)
A switch 4 alternately switches between operation and write operation, and during the write operation period, it supplies a write address to AM2 and writes 4 bytes of write data using a write clock. During the read operation period, the RAM access mechanism 6 supplies a read address to the AM 2 and reads it out of the AM 2 via the 4-byte latch section, and the main memory access mechanism 6. A control mechanism 7, an alignment device 8, a remaining indicator 5, a read/write address line 100 for accessing the left 2 bytes of the RAM 2,
A read/write address line 101 for accessing two bits on the right side of the RAM, an alignment selection line 102,
Indicator line 103 and main memory data read line 104
, RAM data read lines 105 and 106, and alignment lines 107 and 108.

FIG. 2 is a detailed diagram of the RAM 2, RAM access mechanism 6, alignment device 8, and data register 3 shown in FIG. Latch sections 23 and 24 consisting of 2 bytes, an AM write address pointer (hereinafter abbreviated as WP) storage section 61, a RAMfi output address pointer (hereinafter abbreviated as P) storage section 62, and a WP input data switch 63. , RP input data switch 64,
Upper 2 byte read pointer addition circuit 65, upper 2 byte RAM address switching circuit 66, lower 2 byte R
AM address switching circuit 67, write pointer update circuit 68, start pointer update circuit 69, upper 2 bytes) fLAM data demultiplexer 81, lower 2 bytes RAM data aligner 82, upper data register 31, and a lower data register 32. Regarding this embodiment, an example in which the RAM 2 is used as an instruction buffer will be described below.

Now, when the instruction address is address (4n+2) (n is an integer greater than or equal to 0), the instruction word of 16 bytes of data starting from address 4n is fetched from the main memory 1, and sent to the beginning via the instruction buffer 2. The operation for storing the 4-byte data from the third byte into the data register 3 is as follows. The memory access control mechanism 7 accesses the main storage device 1 to obtain a command word of 16-byte data starting from address 4n, and also writes "o o '" to the storage unit 61.
Set Wl'l and write "o o i" in the storage unit 62.
Set the value of P. The data '00' is given through the WP input data switch 63, and the data '001' is given through the BP input data switch 64. In response to the memory access, the main memory 1 first The 4-byte data of the address is transferred.The read/write switch 4 controls the circuit 66 to select the contents of the WP storage section 61 in 1/2 machine cycle during the write cycle.

As a result, in the first write cycle, 4 bytes of data are stored in the instruction buffers 21 and 22 at addresses @00#, 2 bytes each. Next, the main memory device 1 is (4n+
4) Transfers 4 bytes of data at the address. The read/write switch 4 selects the contents of the WP storage section 61 in the same manner as described above during the next write cycle. At this time, W.P.
The contents of the storage section 61 are 1/2 after the end of the previous write cycle.
By the write pointer update circuit 68 in the machine cycle
Only 1 is added. Accordingly, in the second write cycle, the 4-byte data taken out from the main memory 1 is stored in the instruction buffers 21 and 22 at addresses @"01" in 2-byte units. Similarly, (4n+8
) and (4n+12) addresses are stored in the 'IQ' and '11' of the instruction buffers 21 and 22.
The read/write switch 4 stores 2 bytes at each address at the address "l'LP storage section 6" during the read cycle, in 172 machine cycles different from the write cycle.
The circuit 66 is controlled to select the contents of 2. The instruction buffer at indicates a RAM address, and the lower one bit is used to select between the upper instruction buffer 21 and the lower instruction buffer 22. Here, since 几P is @001'', 几AM
Address @00-lower instruction buffer 22 is specified. The upper two bits of this RP are applied to circuit 67. At the same time, the circuit 66 is given 01'' which is obtained by adding +1 to the upper 2 bits of BP by the upper 2 byte read pointer adder circuit 65.
) Once the contents of address ) have been extracted into the instruction buffers 21 and 22-1 0-, a valid read cycle begins. In the read cycle, latch sections 23 and 24
instruction buffer 21 in response to addresses "'01" and 100" from switching circuits 66 and 67, respectively.
The data at the address 101'' of the instruction buffer 22 and the data at the address ``OO'' of the instruction buffer 22 are then read out from the RAM.
(top 2 bytes via D/D outgoing lines 105 and 106)
RAM data alignment unit 81 and lower 2 bytes R
The data is transferred to the AM data aligner 82.

When the lower 1 bit of P is 1'', the RAM data aligners 81 and 82 output the lower RAM data read line 106 and the upper RJAM data read line 1, respectively.
05 is selected. With this, upper data register 3
1 and lower data register 32 have alignment line 1.
The data of latch units 24 and 23 are transferred via 07 and 108, respectively. Each 2-byte data of the instruction buffer 21 is stored in descending order of storage address I Boo ,
I Blo.

IB2G and IB30, each 2 of the instruction buffer 22
IBol stores byte data in ascending order of address.

If I Bll , I B2t and fBal, the data stored in data registers 31 and 32 is IB
ol and I BIG. IBot and IBt
o is 4-byte data starting from address (4n+2) of main storage device 1. After the contents of the data registers 31 and 32 are processed, the R, Pii bladder pointer update circuit 69 adds +2 to the updated BP@0.
11" is set in the storage unit 62 via the AM read address pointer input data switch 64. In the same operation as described above, data registers 31 and 32 each have a value corresponding to address (4n+6) of the main memory 1. The data IBzt and IB20 of the instruction buffers 22 and 21 corresponding to the address (4n+10) of the main storage device 1 are further updated to the data IB21 and IB20 of the instruction buffers 22 and 21 corresponding to the address (4n+10) of the main storage device 1. 1B50 is stored. Further, when the data lBa1 of the instruction buffer 22 corresponding to address (4n+14) of the storage device 1 is transferred to the latch section 24 according to the updated RP "111", the instruction buffers 21 and 22 are in an empty state. becomes. At this time, the latch unit 23 stores the contents of IBoo. In this state, a read access to the next 16 bytes is made to the main memory device 1, and 16 bytes of data starting from address (4n+16), ie I Boo', I Bol
',I BID'.

I Bu', I B20', I B21', I Ba
o'o and IBst' are transferred to instruction buffer 2 in the same way as above.
1 and 22. The remaining indicator 5 indicating that two valid remaining bytes are stored in the latch unit 24 is set to the on state. When the remaining indicator 5 is on, storage of data in the latch section 24 is inhibited. As a result, only the 2-byte data IB00' starting from address (4n+16) of the main memory device 1 is stored in the latch unit 23, and then the contents of the latches 23 and 24 are aligned by the alignment units 81 and 82, and the register 31 and 32 of main storage device 1 (4n
+14) 4-byte data I B31 and I Boo' following the address are stored. After the contents of data registers 31, 13- and 32 are processed, +2 is added to P, and the value changes from "111" to "1001".

Carry pits are discarded. Similarly, 113o
l' and I B1o', I Bll'o and lB2O
'(7) The data are taken out to the data registers 31 and 32 in order.

FIG. 3 is a diagram showing another example of data extraction.

Now, the contents of the 16-byte data area 301 starting from address 4070 of the main memory device 1 are extracted to the instruction buffer 2. At this time, when the 4-byte data ``0'' and ``1'' starting from address 4090 are to be extracted, the data IO of the buffer 2 is immediately extracted to the lower latch section 24. Next, the contents of the 16-byte data area 304 starting from address 4092 are extracted to the instruction buffer 2. Further, the 2-byte data Il from address 4092 is aligned with the data IO of the lower latch section 24 and taken out to the data register 3. Furthermore, when extracting 4 consecutive bytes of 2-byte data 2 at address 4094 and 2-byte data 3 at address 8194, data 2 is extracted from buffer 2 to lower latch 14-24. After the data is output, a 16-byte data area 305 from address 8194 is extracted from the storage device 1 to the instruction buffer 2 as subsequent data. next,
RAM latch section 24 data I2 and data I2 in instruction buffer 2 are both aligned and extracted to data register 3.

(Effects of the Invention) As described above, the present invention has a feature that the contents of the RAM main body, the 2p-byte latch section, and the 2p-byte data register are data extracted from the memory by mutually different memory accesses. It is possible to add functions equivalent to those of a register file, such as a read operation during a write operation, as an AM function, and it has the effect of improving instruction processing speed while reducing hardware requirements. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an embodiment of the present invention;
FIG. 2 is a detailed circuit diagram of this embodiment, and FIG. 3 is a diagram showing an example of data extraction. In the figure, 1... Main storage device, 2...
・几AM. 3...Data register, 4...Switcher, 5...Remaining indicator, 6...
RAM access mechanism, 7...Memory access control mechanism, 8. 81. 82... Alignment device, 21.22... RAM main unit s 23.
24...R, AM latch section, 61...
RAM write address pointer storage section, 62...
- RAM read address pointer storage section, 63. 64
゜66.67...Switcher, 100-108.
·····Signal line. Figure 1 Figure 2

Claims (1)

[Claims] The first one has a capacity of 2p (p is a positive integer) bytes each.
and a second storage means; a first storage means having m (positive integer) storage areas, each of which has a capacity of 2p bytes; switching means for alternately switching between a read operation and a write operation for the first storage means; during the write operation period, the first storage means is supplied with a write address to store 2p bytes of write data from the second storage means; During a continuous operation period, access means supplies a read address to the first storage means to store p bytes or 2p bytes of continuous data in the first storage means, and an access means in the second storage means. memory access means for transferring (2pxm) bytes of data m times in units of 2p bytes and storing it in the first storage means; alignment means for exchanging p bytes and storing them in the second storage means; and alignment means for exchanging desired p bytes of the 2p bytes of data currently stored in the first storage means and then the memory access means. In order to transfer desired p bytes of the new (2pxm) bytes of data to be stored from the second storage means to the first storage means to the alignment means, 1. A data extraction processing device comprising: display means for displaying that the data stored in the storage means is valid.