JPH0231418B2 - DEETACHUSHUTSUSHORISOCHI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data extraction processing device used for command word processing and the like.

(Prior art) A data extraction processing device used for conventional instruction word processing has an instruction word buffer of at least 3p bytes for the minimum required instruction word of p (positive integer) bytes, and has an instruction word buffer of at least 3p bytes. 2p served
Bytes of data are stored in this buffer, and if there is more than p bytes of free space, the subsequent 2p
As the byte of data is read out, the instruction word buffer is left-justified, and a new 2p byte of data is stored. In an instruction word buffer of 3p bytes or more, shifting to the left by p or 2p bytes requires an enormous amount of connection wiring, selection circuits, and selection control circuits.

In addition, other conventional data extraction processing devices have a 2p byte instruction buffer and a register file of m (positive integer) words x 2p bytes for the minimum required p byte instruction words. Read and store consecutive 2p bytes from a desired position in the register file in the instruction word buffer;
When the register file is used up and less than p bytes of data remain, only the p bytes of data are left.
It is stored in the first half p bytes of a 2p byte instruction word buffer, and when the register file is empty, the next memory access is performed and consecutive m words x
Requests 2p bytes of data from the storage device, and when storage begins or ends in the register file, takes out the first p bytes of data from the register file and stores it in the latter p bytes of the instruction word buffer. As a result, a 2p byte instruction word is obtained. This device has the disadvantage that the next memory access cannot be performed until the data in the register file is used up, and the instruction word buffer is 2p bytes valid from the time when the first half p bytes are stored until the second half p bytes are stored. The disadvantage is that the hardware is occupied until all data is available, making it impossible to perform high-speed transfer processing.

(Object of the Invention) An object of the present invention is to provide a data extraction processing device that eliminates the above-mentioned drawbacks.

(Structure of the Invention) The device of the present invention includes first and second storage means each having a capacity of 2p (p is a positive integer) bytes, and m (positive integer) storage areas, each of which has a capacity of 2p (p is a positive integer) bytes. a first storage means each having a capacity of 2p bytes, a switching means for alternately switching between a read operation and a write operation for the first storage means at a predetermined period, and a write address during the write operation period. the first storage means and the second storage means;
During the read operation period, a read address is supplied to the first storage means to store p bytes or 2p bytes of read data in the first storage means. an access means, a memory access means for transferring (2p×m) bytes of data in the second storage means m times in units of 2p bytes and storing it in the first storage means; of
alignment means for storing 2p bytes of data directly or by exchanging upper p bytes and lower p bytes in the second storage means; and desired p bytes of new (2p×m) bytes of data to be stored from the second storage means to the first storage means by the memory access means. and display means for displaying that the data currently stored in the first storage means is valid for transfer to the alignment means.

(Example) Next, the present invention will be described in detail with reference to the drawings.

In FIG. 1 showing one embodiment of the present invention, this embodiment has a main memory 1 and a readable and writable memory (hereinafter referred to as (referred to as RAM) 2, a data register 3, and a switch 4 that alternately switches between read operation and write operation of the RAM 3 at a half cycle of one machine cycle.
During the write operation period, a write address is supplied to RAM2 to store 4 bytes of write data using the write clock, and during the read operation period, a read address is supplied to RAM2 to store 4 bytes of write data. A RAM access mechanism 6 for reading data out of the RAM 2 through the latch section of the RAM 2, a main memory access control mechanism 7, an alignment device 8, a remaining indicator 5, and a RAM
A read/write address line 100 accesses 2 bytes on the left side of RAM 2, and a read/write address line 101 accesses 2 bytes on the right side of RAM.
, an alignment selection line 102 , an indicator line 103 , a main memory data read line 104 ,
It is composed of RAM data read lines 105 and 106 and alignment lines 107 and 108.

FIG. 2 is a detailed diagram of the RAM 2, RAM access mechanism 6, alignment device 8, and data register 3 shown in FIG. latch parts 23 and 24,
RAM write address pointer (hereinafter abbreviated as WP)
A storage section 61, a RAM read address pointer (hereinafter abbreviated as RP) storage section 62, a WP input data switch 63, an RP input data switch 64,
Upper 2-byte read pointer addition circuit 65, upper 2-byte RAM address switching circuit 66, lower 2-byte RAM address switching circuit 67, write pointer update circuit 68, read pointer update circuit 69, and upper 2-byte RAM data alignment 81, a lower 2-byte RAM data alignment unit 82, an upper data register 31,
and a lower data register 32. Regarding this embodiment, an example in which RAM 2 is used as an instruction buffer will be described below.

Now, the instruction address is (4n+2) (n is 0
(integer greater than or equal to), 16 starting from address 4n
The operation for retrieving a command word of byte data from the main storage means 1 and storing the third byte of 4-byte data from the head into the data register 3 via the command buffer 2 is as follows. The memory access control mechanism 7 accesses the main storage device 1 in order to obtain a command word of 16-byte data starting from address 4n, and also stores a WR of "00" in the storage section 61.
is set, and an RP of “001” is set in the storage unit 62. “00” data is WP input data switch 6
3, the data of "001" is applied via the RP input data switch 64, respectively. In response to the memory access, the main memory device 1 first responds to the 4n
Transfers 4 bytes of address data. Read/write switch 4 is 1/2 during write cycle
The circuit 66 is controlled to select the contents of the WP storage 61 in machine cycles. As a result, in the first write cycle, 4 bytes of data are stored in the instruction buffers 21 and 22 at addresses "00", 2 bytes each. Next, main memory 1 is (4n+4)
Transfers 4 bytes of address data. The read/write switch 4 selects the contents of the WP storage section 61 in the same manner as described above during the next write cycle.
At this time, the contents of the WP storage unit 61 are incremented by +1 by the write pointer update circuit 68 in 1/2 machine cycle after the end of the previous write cycle. As a result, in the second write cycle,
The 4-byte data taken out from the main memory 1 is stored in 2-byte units at addresses "01" in the instruction buffers 21 and 22. Similarly, below,
Addresses (4n+8) and (4n+12) of main storage device 1
Each 4-byte data from the address is stored in the instruction buffer 2.
Two bytes each are stored at addresses "10" and "11" of numbers 1 and 22. Read/write switch 4
controls the circuit 66 to select the contents of the RF storage section 62 during a read cycle in a 1/2 machine cycle different from the write cycle. Consider the instruction buffers 21 and 22 divided into upper and lower parts of 2 bytes each. RP consists of 3 bits, the upper 2
The bit indicates a RAM address, and the lower one bit is used to select between the upper instruction buffer 21 and the lower instruction buffer 22. Here, since RP is "001", RAM address "00" and lower instruction buffer 22 are specified. The upper two bits of this RP are applied to circuit 67. At the same time, circuit 66 has
RP with upper 2 byte read pointer addition circuit 65
``01'' is given by adding +1 to the upper two bits of . At the stage when the contents of addresses 4n and (4n+4) from the main memory 1 have been extracted to the instruction buffers 21 and 22, a valid read cycle is started. In the read cycle, data at address "01" of instruction buffer 21 and address "00" of instruction buffer 22 are sent to latch units 23 and 24 in response to addresses "01" and "00" from switching circuits 66 and 67, respectively. The data is then taken out and subsequently transferred to the upper 2-byte RAM data aligner 81 and the lower 2-byte RAM data aligner 82 via the RAM data read lines 105 and 106. When the lower one bit of RP is "1", RAM data aligners 81 and 82 select lower RAM data read line 106 and upper RAM data read line 105, respectively. As a result, data from latch sections 24 and 23 is transferred to upper data register 31 and lower data register 32 via alignment lines 107 and 108, respectively. Each 2-byte data of the instruction buffer 21 is stored in IB ₀₀ , IB ₁₀ , IB ₂₀ and IB ₃₀ in descending order of address.
Then, each 2-byte data of the instruction buffer 22 is stored in IB ₀₁ , IB ₁₁ , IB ₂₁ and
Assuming IB ₃₁ , the data stored in data registers 31 and 32 are IB ₀₁ and IB ₁₀ . _IB01
and IB ₁₀ is 4-byte data starting from address (4n+2) in main storage device 1. After the contents of the data registers 31 and 32 are processed, +2 is added to the RP by the read pointer update circuit 69, and the updated RP “011” is sent to the storage unit via the RAM read address pointer input data switch 64. It is set to 62. With the same operation as above,
The data registers 31 and 32 contain the data IB ₁₁ and IB ₂₀ of the instruction buffers 22 and 21 corresponding to address (4n+6) of the main memory 1, respectively. Data IB ₂₁ and IB ₃₀ of instruction buffers 22 and 21 corresponding to address (4n+10) are stored. Furthermore, when the data IB ₃₁ of the instruction buffer 22 corresponding to address (4n+14) of the storage device 1 is transferred to the latch unit 24 due to the updated RP “111”, the instruction buffers 21 and 22 become empty. Become. At this time, the latch portion 23 has
The contents of IB ₀₀ are stored. In this state, read access to the next 16 bytes to main memory device 1,
16 bytes of data starting from address (4n+16), i.e. IB ₀₀ ′, IB ₀₁ ′, IB ₁₀ ′, IB ₁₁ ′, IB ₂₁ ′, IB ₃₀ ′
and IB ₃₁ ' are extracted to instruction buffers 21 and 22 in the same manner as described above. The remaining indicator 5 indicating that two valid remaining bytes are stored in the latch unit 24 is set to the on state. When the remaining indicator 5 is on, storage of data into the latch section 24 is inhibited. As a result, only the 2-byte data IB ₀₀ ' starting from address (4n+16) of the main memory device 1 is stored in the latch section 23, and after this, the contents of the latch sections 23 and 24 are aligned by the aligners 81 and 82. ,,
Registers 31 and 32 contain (4n
+14) 4-byte data following the address IB ₃₁ and
IB ₀₀ ′ will be stored. After the contents of data registers 31 and 32 are processed, RP is added by +2 and changes from "111" to "001".
Carry bits are discarded. Similarly, below,
IB ₀₁ ′, IB ₁₀ ′, IB ₁₁ ′, and IB ₂₀ ′ are taken out to data registers 31 and 32 in this order.

FIG. 3 is a diagram showing another example of data extraction.
Now, the contents of the 16-byte data area 301 starting from address 4070 of the main memory device 1 are extracted to the instruction buffer 2. At this time, when taking out 4-byte data I ₀ and I ₁ starting from address 4090, data I ₀ of buffer 2 is first taken out to lower latch section 24 . Next, the contents of the 16-byte data area 304 starting from address 4092 are extracted to the instruction buffer 2. Further, the 2-byte data I ₁ from address 4092 is aligned with the data I ₀ of the lower latch section 24 and taken out to the data register 3. Additionally, 2 bytes of data at address 4094
When extracting 4 consecutive bytes of data I ₂ and 2 bytes of data I ₃ at address 8194, after extracting data I ₂ from buffer 2 to lower latch section 24,
From storage device 1 to instruction buffer 2 from address 8194
A 16-byte data area 305 is extracted as subsequent data. Next, the RAM latch section 24 data
I ₂ and data I ₃ in the instruction buffer 2 are aligned and extracted to the data register 3.

(Effects of the Invention) As described above, the present invention has a feature that the contents of the RAM main body, the 2p byte latch part, and the 2p byte data register are data extracted from the memory by mutually different memory accesses. In addition, it is possible to add a function equivalent to that of a register file as a RAM function, such as a read operation during a write operation, and it has the effect of improving instruction processing speed while reducing hardware requirements. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the embodiment, and FIG. 3 is a diagram showing an example of data extraction. In the figure, 1...main storage device, 2...
RAM, 3...Data register, 4...Switcher, 5...Remaining indicator, 6...RAM access mechanism, 7...Memory access control mechanism, 8,
81, 82... Alignment device, 21, 22...
RAM main body, 23, 24...RAM latch section,
61...RAM write address pointer storage section,
62...RAM read address pointer storage section,
63, 64, 66, 67...Switcher, 100~
108...Signal line.

Claims (1)

[Claims] 1. First and second storage means each having a capacity of 2p (p is a positive integer) bytes, and m (positive integer)
Each storage area has 2p storage area.
a first storage means having a capacity of one byte; a switching means for alternately switching between a read operation and a write operation for the first storage means at a predetermined period; During the read operation period, a read address is supplied to the first storage means to store 2p bytes of write data from the second storage means, and p bytes are stored in the first storage means. or an access means for storing read data of 2p bytes, and (2p×m) in the second storage means.
a memory access means for transferring 2p bytes of data m times each and storing it in the first storage means; alignment means for exchanging and storing the data in the second storage means; and a desired p bytes of the 2p bytes of data currently stored in the first storage means and then the memory access means to store the data in the second storage means.
desired p bytes of the new (2p×m) bytes of data to be stored in the first storage means from the storage means in the storage means are currently stored in the first storage means in order to transfer them to the alignment means. 1. A data extraction processing device comprising: display means for displaying that the data being processed is valid.