JPH02138624A - Queue device - Google Patents

Abstract

PURPOSE:To improve the performance of a microcomputer by setting the write data width at 2 words to an instruction queue and securing the variable length reading for the read data width every 1 or 2 words against the instruction queue. CONSTITUTION:The instruction codes read out of a memory are written into an instruction queue latch 101 every 2 words. Then the instruction codes are read out of the latch 101 every 1 or 2 words for execution of instructions. While an IQWR signal 1081, i.e., the instruction codes applied to the latch 101 every 2 words or a write signal is inputted to an instruction queue control part 105 from a bus control part 108. At the same time, a QWRD signal 1091, i.e., the instruction code read signals received from the latch 101 every word and a QLWRD signal 1092, i.e., the instruction code read signals received from the latch 101 every 2 words are inputted to the part 105 from an instruction executing part 109. Thus the necessary and sufficient number of instruction codes are supplied and therefore the performance of a microcomputer is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a queue device used for advance processing of a microcomputer.

[Conventional technology]

Generally, a microcomputer that performs pipeline control is equipped with a buffer or queue that stores instruction codes and operand data in advance from memory.

FIG. 8 is a block diagram showing the configuration of an instruction code fetch unit equipped with a queue for prefetching instruction codes, which is used in a conventional microcomputer that employs vibe line control; FIG. 9 (1) to FIG. (3) is an explanatory diagram showing the operation of the conventional example shown in FIG.

The instruction code edge unit 500 includes an instruction queue latch 501 that stores instruction codes in units of one word in FIFO;
It consists of an instruction queue pointer 502 that indicates the read position from the instruction queue latch 501, and an instruction queue control unit 503 that controls the instruction code fetch unit 500. It is connected to an instruction code output bus 505.

The instruction code input bus 504 is connected to a bus control unit 506 that reads instruction codes from the memory and reads/writes data to and from the memory, and the instruction food output bus 505 is connected to an instruction execution unit 507 that executes instructions. has been done.

The instruction queue latch 501 is composed of 1-word x 4-stage shift registers 5011 to 5014, and by writing to the instruction queue latch 501, the contents of the 1-word wide instruction code input bus 504 are transferred to the shift register 5011. At the same time as importing, the previous shift registers 5011 to 501
Shift the entire contents of 4 to the output side by one stage.

The instruction queue pointer 502 is composed of 1-bit x 5-stage shift registers 5021 to 5025, of which only one bit is always set to 1'', and the set pointer is transferred to the instruction queue latch 501. one of them
Word data read position, i.e. instruction code output bus 5
This corresponds to the position of 1 word data in the instruction queue latch 501 that is output to 05.

When instruction queue latch 501 is empty, ie, there is no valid instruction code in instruction queue latch 501, shift register 5021 is set to 1''.

The instruction code read from the memory by the bus control unit 506 is written in the instruction queue latch 501 in units of one word.
An instruction code is read from the instruction queue latch 501 in units of one word by the instruction execution unit 507.

The instruction queue control unit 503 receives the following information from the bus control unit 506:
A QWII signal 5061, which is a one-word instruction code write signal to the instruction queue ledge 501, is input.

The instruction queue control unit 503 controls the instruction queue when there is one word or more of unread instruction code in the instruction queue latch, that is, when any of the instruction queue pointers 5022 to 5026 is set to 1''. The queue ready signal 50:33 indicating that the instruction code can be read from the latch 501 is activated.

When reading an instruction code from the instruction queue latch 501, the instruction execution unit 507 is in a readable state, that is, if the queue ready signal 5033 is active,
A QRD signal 5071, which is an instruction code read signal in units of one word, is output to the instruction queue control unit 503.

Command* Knee ill full af1503 Ha, Q
The operation of the instruction queue pointer 502 is controlled by the WRI number 506tQRD signal 5071. Instruction queue control unit 5
03, for the instruction queue pointer 502, a QPB signal 5031 that shifts the instruction queue pointer 502 by one stage to the input side, and a QPB signal 5031 that shifts the instruction queue pointer 502 by one stage to the output side.
Outputs QPF signal @5032 which is shifted by step.

Next, the operation of instruction code fetch section 500 will be explained.

The combination of the write operation to the instruction queue latch 501 and the read operation from the instruction queue latch 501 is as follows: (1) The instruction queue latch 501 by the bus control unit 506
When only 1 is added to QWR signal 5061
(active) (2) Instruction queue latch 501 by instruction execution unit 507
(QRD signal 507
1 is active) (3) Instruction queue latch 501 by bus control unit 506
When writing to and reading from the instruction queue latch 501 by the instruction execution unit 507 are performed at the same time (QWR
There are three ways (signal 5061 and QRD signal 5071 are active).

Instruction code edge section 50 under these three conditions
The operation of 0 will be described with reference to FIG. In addition, ao in the figure
, al, and a2 indicate instruction codes in the instruction queue latch 501.

In the case of (1), as shown in FIG. 9(1), the contents of the instruction queue latch 501 are shifted one stage to the output side, and the instruction queue control unit 503 activates the QPF signal 5032 to The cue pointer 502 is shifted one stage to the output side. As a result, the instruction code being output to the instruction code output bus 505 does not change.

In case (2), as shown in FIG. 9(2), the contents of the instruction queue latch 501 are not shifted, and the instruction queue control unit 503 activates the QPB signal 5031 to set the instruction queue pointer 502. Shift one step to the input side. As a result, the following one is sent to the instruction code output bus 505.
A word instruction code is output.

In case (3), as shown in FIG. 9(3), the contents of the instruction queue latch 501 are shifted one stage to the output side, and the instruction queue pointer 502 is not shifted. This results in
The next one-word instruction code is output to the instruction code output bus 505.

[Problem to be solved by the invention]

In the conventional instruction queue described above, the read data width is a fixed length, so if the minimum unit of read data from the instruction queue is one word, the data width of the queue latch cannot be made larger than one word. In other words, in the conventional queue configuration, the data width of the queue latch is limited by the minimum unit of the read data width. Even if an attempt is made to improve the processing power of a microcomputer by increasing the bus width, the data width in the instruction queue becomes a bottleneck, and the instruction code is not sufficiently supplied to the instruction execution part, so the processing power cannot be improved. It has the disadvantage of being suppressed.

[Means to solve the problem]

The queue device of the present invention comprises a storage means configured with a multi-stage shift register having a width twice the unit instruction code length or unit data length for storing instruction codes or data in FIFO, and an upper unit of the storage means. Upper read position indicating means indicating the read position of the long instruction code or upper unit length data; Lower read position indicating means indicating the read position of the lower unit length instruction code or lower unit length data of the storage means; Upper unit length instruction code or upper unit length data in the storage means pointed to by the position indication means and lower unit length instruction code or lower unit length in the storage means pointed to by the lower reading position indication means An exchange means for exchanging instruction codes or lower unit length data, a detection means for detecting that instruction codes or data are stored in the storage means, and an upper read position instruction in response to external read and write signals. and control means for changing the contents of the lower read position indicating means and for activating/inactivating the exchange means.

[Effect]

In the present invention, the write data width to the instruction queue is 2 words, and the read data width from the instruction queue is variable in length in units of 1 word or 2 words. This prevents bottlenecks in supplying instruction codes to the instruction execution section due to limitations on the data width of the instruction queue, and improves the performance of the microcomputer by supplying necessary and sufficient output instruction codes.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an instruction code fetch section of a microcomputer equipped with an instruction code prefetching queue, which is a first embodiment of the queue device of the present invention.
FIG. 4 (1) to FIG. 4 (10) are explanatory diagrams of the operation of the first embodiment.

The instruction code fencing unit 100 includes an instruction queue latch 101 that stores instruction codes in units of 2 words in FIFO;
In the instruction queue latch 101 having a 2-word configuration, a lower instruction queue pointer 102 indicates the position from which one word of data is read from the lower side, and an upper instruction queue pointer 103 indicates the position from which one word of data is read from the upper side. , an instruction queue exchanger 104 that exchanges and outputs the lower one word data of the output of the instruction queue latch 101 and the upper/lower one of the upper one word data, and the instruction queue control section 105 that controls the instruction code fetch section 100. and a 2-word wide instruction code input bus 106 and 2
It is connected to a one-word wide instruction code output bus 107.

The instruction code input bus 106 is connected to a bus control unit 108 that reads instruction codes from the memory and reads/writes data to and from the memory, and the instruction code output bus 107 is connected to an instruction execution unit 109 that executes instructions. It is connected to the.

The instruction queue latch 101 is composed of 2-word x 4-stage shift registers 1011 to 1014, and by writing to the instruction queue latch 101, the contents of the 2-word wide instruction code input bus 106 are transferred to the shift register 101+. At the same time as importing, the previous shift registers 1011 to 101
The entire contents of 4 are shifted one stage to the output side.

The lower instruction queue pointer 102 is composed of 1 bit x 5 stage shift registers 1021 to 1025, of which only one bit is always set to 1'', and the set pointer is connected to the instruction queue latch. 101 shows the reading position of one word of data on the lower side.

The upper instruction queue pointer 103 is composed of shift registers 1031 to 1o35 with 1 bit x 5 stages, and only one bit among the 5 bits is always set to "1", and the set pointer is Cue latch 10
1 shows the read position of the upper 1 word data in 1.

When the instruction queue 100 is empty, that is, the instruction queue latch 10
If there is no valid instruction code in 1, shift registers 1021 and 103+ are both set to ``1''.

The instruction code read from the memory is written in 2-word units to the instruction queue latch 101, and the instruction code is written in 1-word or 2-word units for instruction execution from the instruction queue latch 101. Read in units.

The instruction queue control unit 105 receives the following information from the bus control unit 108:
The IQWR signal 1081, which is an instruction code write signal in units of 2 words, is input to the instruction queue latch 101, and the instruction execution unit 109 writes the 1 word from the instruction queue latch 101.
QWRD signal which is a word unit instruction code read signal @
109t and a QIJRD signal 1092 which is an instruction code read signal in units of 2 words from the instruction queue are input. The instruction queue control unit 105 uses these signals to set the lower instruction queue pointer 102 . Upper instruction queue pointer 103 and instruction queue exchanger 104
The operation of III! Ill do it. For the lower instruction queue pointer 102, a QPLB signal 1051 that shifts the lower instruction queue pointer 102 one step toward the input side and a QPLF signal 1952 that shifts the lower instruction queue pointer 102 one step toward the output side are sent to the upper instruction queue pointer 102. Side instruction queue pointer 1
For 03, the Q P If B signal 1053 which shifts the upper instruction queue pointer 103 by one step to the input side and the QPHF signal 1054 which shifts the upper instruction queue pointer 103 by one step to the output side are sent to the instruction queue exit. For changer 104, IQX signal 1055 controls the inversion of the output from instruction queue exchanger 104.
Output.

Next, the operation of the instruction code fetch section 100 shown in FIG. 1 will be explained.

The combination of the write operation to the instruction queue latch 101 and the read operation from the instruction queue latch 101 is as follows: (1) The instruction queue latch 101 by the bus control unit 108
(IQWn signal 1081 is active).

(2) Instruction queue latch 101 by instruction execution unit 109
If only one word is read from QWRD
signal 1091 is active).

(3) Instruction queue latch 101 by instruction execution unit 109
When only 2 words are read from QL14
RD signal 1092 is active).

(4) Instruction queue latch 101 by bus control unit 108
When two words are written to the instruction queue latch 101 and one word is read from the instruction queue latch 101 by the instruction execution unit 109 at the same time (rQWR signal 1081 and QWRD signal 109
1 is active).

(5) Instruction queue latch 101 by bus control unit 108
When two words are written to the instruction queue latch 101 and two words are read from the instruction queue latch 101 by the instruction execution unit 109 at the same time (IQWR signal 1081 and QL14RD signal 1
092 is active).

There are five ways.

Instruction code fetch unit 100 under these five conditions
The operation will be described with reference to FIG. In addition, ao in the figure,
al, a2. a3 indicates the instruction code in the instruction queue latch 101.

Case (1) (Figure 4 (1), (2)). Figure 4 (1) shows the case where IQXfi No. 1055 is 0'',
Figure (2) C, IQX signal l 055 F “1” (7
) It shows I match. In either case, the contents of the instruction queue latch 101 are shifted one stage to the output side, and the instruction queue control unit 105 outputs the QPLF signal 1052 and the QPHr
The signal 1054 is activated to shift both the lower instruction queue pointer 102 and the upper instruction queue pointer 103 one stage to the output side. As a result, the instruction code being output to the instruction code output bus 107 does not change. Further, the state of the instruction queue exchanger 104 does not change.

Case (2) (Figure 4 (3), (4)). FIG. 4(3) shows the case where the IQX signal 1055 is "0", and FIG. 4(4) shows the case where the IQX signal 1056 is "1". The contents of the instruction queue latch 101 are not shifted;
The instruction queue control unit 105 determines that the IQX signal 1055 is “
0'', the QPLB signal 1051 is activated and the lower instruction queue pointer 102 is shifted one step to the input side, and when the IQX signal 1055 is 111 II, the QPHB signal @1053 is activated and the lower instruction queue pointer 102 is shifted one step to the input side. The side instruction queue pointer 103 is shifted one step to the input side.As a result, the next two-word instruction code is output to the instruction code output bus 107.In addition, the instruction queue control unit 105 outputs the IQX signal 1055 to the instruction code output bus 107. By reversing the
The output of the instruction queue exchanger 104 is inverted.

Case (3) (Figure 4 (5), (6)). 4 (5) shows the case where the IQX signal @1055 is “i 0 +′”, and FIG. 4 (6) shows the case where the IQX signal 1055 is “1”. Contents of the instruction queue latch 101 is not shifted, and the instruction queue control unit 105 uses the QPLB signal 10.
51 and QPHB signal 1053,
Both the lower instruction queue pointer 102 and the upper instruction queue pointer 103 are shifted one stage to the input side. As a result, the next two words of instruction code are output to the instruction code output bus 107.

Further, the state of the instruction queue exchanger 104 does not change.

Case (4) (Figure 4 (7), (8)). FIG. 4 (7) shows the case where the IQX signal 1055 is “OH”,
Figure (8) C shows the case where the IQX signal 1055 is 441 II. The contents of the instruction queue latch 101 are shifted one stage to the output side, and the instruction queue control unit 105 outputs the IQX
When signal 1055 is O'', QPHF signal 1054
7 active and the upper instruction queue pointer 103
is shifted one stage to the output side, and the IQX signal 1055 becomes 1''
In this case, the QPLF signal 1053 is activated and the lower instruction queue pointer 102 is shifted one stage to the output side. As a result, the instruction code output bus 107 has
The next two words of instruction code are output. Further, the instruction queue control unit 105 inverts the output of the instruction queue exchanger 104 by inverting the IQX signal 1055.

In the case of (5) (Figure 4 (9) and (10)). FIG. 4 (9) shows the case where the IQX signal 1056 is “0”,
Figure (10) C shows the case where the IQX signal 1055 is 1'. The contents of the instruction queue latch 101 are shifted one stage to the output side. The states of the lower instruction queue pointer 102, the upper instruction queue pointer 103, and the instruction queue exchanger 104 do not change. As a result, the next two words of instruction code are output to the instruction code output bus 107.

FIG. 2 is a block diagram showing the configuration of an instruction food edge section of a microcomputer equipped with an instruction code prefetching queue, which is a second embodiment of the queue device of the present invention.

In the second embodiment, the instruction queue control unit 105 stores two unread instruction codes in the instruction queue latch 101.
There are one word or more, that is, one of the lower instruction queue pointers 1022 to 1026 is II I Tl
When set to , it activates a long word queue ready signal 1056 indicating that instruction code reading in units of 1 word or 2 words is executable.

When reading the instruction code from the instruction queue latch 101, the instruction execution unit 109 reads the instruction code in units of one word or two.
When the instruction code in units of one word can be read, that is, when the long word queue ready signal 1056 is active, when reading the instruction code in units of one word, the Q14RD signal 1091 is set to one word. When reading instruction codes in units of codes, a QLWRD signal 1092 is output to the instruction queue control section 105.

Note that the operation of the instruction code fetch unit 100 in this embodiment is the same as that described in FIGS. 4(1) to (10), so the description thereof will be omitted.

FIG. 3 shows a third embodiment of the cue device of the present invention. FIG. 2 is a block diagram showing the configuration of an instruction code fetch section of a microcomputer equipped with an instruction code prefetch queue.

In the third embodiment, in addition to the long word queue ready signal 1056, which is the notification means in the second embodiment,
Two cue ready signals including the word cue ready signal 1057 are provided as notification means. That is, in the third embodiment, even if only one word of the instruction code exists in the instruction queue latch 101, the reading of one word of the instruction code is newly performed so that the instruction code of one word can be read. A word cue ready signal 1057 indicating that it is executable is added.

The instruction queue control unit 105 determines that there is only one word of unread instruction code in the instruction queue latch 101, that is, the upper instruction queue pointer 1032 is set to 1'', and the lower instruction queue pointer 1022 to
When all 1026 are reset to 11011, a word queue ready signal @305a is output indicating that the instruction code can be read in units of 1 word, and the instruction code is not read into the instruction queue latch 101. Two or more words of the instruction code exist, that is, one of the lower instruction queue pointers 1022 to 1025 is 1.
'', the word queue ready signal 1057 indicates that instruction code reading in 1-word units is executable, and the long signal 1057 indicates that instruction code reading in 2-word units is executable. Activate word queue ready signal 3016.

When reading the instruction code from the instruction queue latch 101, the instruction execution unit 109 outputs the QWRD signal if the medium-sized instruction code of 1 word is readable, that is, if only the word queue ready signal 1056 is active. When the QWRD signal 1091 is in a state where the instruction code can be read in 1-word or 2-word units, that is, when the word queue ready signal 1057 and the long word queue ready signal 1058 are both active, the QWRD signal 9
Either the QLWIID signal 1091 or the QLWIID signal 1092 is output to the instruction queue control unit 105.

Note that the operation of the instruction code fetch unit 100 in this embodiment is the same as that described in FIGS. 4(1) to (10), so the description thereof will be omitted.

55 is a block diagram showing the configuration of a data edge section of a microcomputer equipped with a block data prefetching queue, which is a fourth embodiment of the queue device of the present invention;
FIG. 7(1) to FIG. 7(10) are explanatory diagrams of the operation of the fourth embodiment.

The data fetch unit 300 fetches data in units of 2 words.
A data queue latch 301 that is stored in an IFO, a lower data queue pointer 302 that indicates the reading position of one word of data from the lower side of the two-word data queue latch 301, and one word of data that is read from the upper side. An upper data queue pointer 303 indicating the position, a data queue exchanger 304 that exchanges and outputs the lower one word data of the output of the data queue latch 301 and the upper/lower one word data, and the data fetch The data queue controller 305 is connected to a 2-word wide data input bus 306 and a 2-word wide data output bus 307.

Further, the data input bus 306 is connected to a bus control unit 308 that reads instruction codes from the memory and reads/writes data to and from the memory, and the data output bus 307
is connected to a data processing unit 309 that performs data processing.

The data queue latch 301 is composed of 2-word x 4-stage shift registers 3011 to 3014, and by writing to the data queue latch 301, the contents of the 2-word wide data input bus 306 are taken into the shift register 3011. In addition, the previous shift registers 3011 to 301
The entire contents of 4 are shifted one stage to the output side.

The lower data queue pointer 302 is composed of shift registers 3021 to 3025 with 1 bit x 5 stages, and only one bit among the 5 bits is always set to 1'', and the set pointer points to the data queue. latch 5
This shows the read position of the lower one word data in 01.

The upper data queue pointer 303 is composed of 1 bit x 5 stage shift registers 3031 to 3035, of which only one bit is always set in II 111, and the set pointer is connected to the data queue latch 301. This shows the read position of one word of data on the upper side.

When data queue latch 301 is empty, that is, when there is no valid data in data queue latch 301, shift registers 302+ and 303+ are both set to 111 II.

The data read from the memory is loaded into the data queue latch 301 in 2-word units, and data is read out from the data queue latch 301 in 1-word or 2-word units as data is processed. be done.

The data queue control unit 305 receives a DQWR signal 5°81 from the bus control unit 308, which is a data storage signal for the data queue latch 301 in units of 2 words, and the data processing unit 309 DQ! which is a data read signal in units of one word from 301. iRD
A signal 3091 and a DQLWRD signal 3092, which is a data read signal in units of 2 words from the data queue, are input. The data queue control unit 305 uses these signals to set the lower data queue pointer 302 . The operations of the upper data queue pointer 303 and the data queue exchanger 304 are performed ll611. For the lower data queue pointer 302, a DQPLB signal 3051 that shifts the lower data queue pointer 302 by one stage to the input side and a DQPLF signal 3052 that shifts the lower data queue pointer 302 by one stage to the output side are sent to the upper For the side data queue pointer 303, DQP shifts the upper side data queue pointer 303 one stage to the input side.
HB signal 3o53 and upper data queue pointer 30
A DQPHF signal 3o54 for shifting 2 to the output side by one step is output to the data queue exchanger 304, and a DQX signal 3053 for controlling the inversion of the output from the data queue exchanger 304.

Next, the operation of the data fetch section 300 shown in FIG. 5 will be explained.

The combination of the write operation to the data queue latch 301 and the read operation from the data queue latch 301 is as follows: (1) The data queue latch 30 by the bus control unit 308
If only 2-word 1-into 1 is performed (DQWR
signal 3081 is active).

(2) Data queue latch 3 by data processing unit 309
When only one word is read from 01 (DQ
WRD signal 3o91 is active).

(3) Data queue latch 3 by data processing unit 309
When only two words are read from 01 (DQ
IJRD signal 3092 is active).

(4) Data queue latch 30 by bus control unit 308
When writing 2 words to 1 and reading 1 word from the data queue latch 301 by the data processing unit 309 are performed at the same time (DQWIt signal @ 3081 and DQ1
4R [l signal 3091 active).

(5) Data queue latch 30 by bus control unit 308
When 2-word writing to 1 and 2-word reading from data queue latch 301 by data processing unit 309 are performed simultaneously (DQWR signal 3081 and DQLWR start signal 3092 are active).

There are five ways.

The operation of the data fetch unit 300 under these five conditions will be described with reference to FIGS. 7(1) to 7(10).

Note that ao, al, a2. a3 indicates data in the data queue latch 301.

In the case of (1) (Figure 7), (2)). Figure 7 (
1) shows the case where the DQX signal 3055 is O'' as shown in Fig. 7 (
2) C. The case where the DQX signal 3056 is II 111 is shown. In either case, the data queue latch 301
The contents of DQPLF signal 3052 and DQPIIF are shifted one stage to the output side, and data queue control unit 305
By activating signal 3054, lower data queue pointer 302 and upper data queue pointer 30
3 are both shifted one step to the output side. As a result, the data being output to the data output bus 307 does not change.

Furthermore, the state of the data queue exchanger 504 does not change.

Case (2) (Figure 7 (3), (4)). Figure 7 (3) shows the QX signal 3055 ``0'' (7).
'14 Match, Figure 7 (4) C, DQX signal 3055
tfi "1" (7) is shown. The contents of the data queue latch 301 are not shifted, and when the DQX signal 3055 is O11, the data queue control unit 305 activates the DQPLB signal 3051 and shifts the lower data queue pointer 302 by one stage to the input side.
When the DQX signal 3055 is "1", the DQPHB signal 3053 is activated and the upper data queue pointer 303 is shifted one stage to the input side. This results in
The following two words of data are output to the data output bus 307. Further, the data queue control unit 305
By inverting the signal 3055, upper/lower data of the data queue exchanger 304 is exchanged.

In the case of (3) (Figure 7 (5), (B)'). 7th
Figure (5) shows the case where the DQX signal 5055 is O'' at the seventh
Figure (6) C, DQX signal 3055 is '1' (7)
It shows the case. The contents of the data queue latch 301 are not shifted, and the data queue control unit 305
The signal 3051 and the DQPH8 signal 5053 are activated to shift both the lower data queue pointer 302 and the upper data queue pointer 303 to the input side by one stage. As a result, the next two words of data are output to the data output bus 307. Furthermore, the state of the data queue exchanger 304 does not change.

In the case of (4) (Figure 7 (71, (81). Figure 7 (7)
The case where the DQX signal 3055 is °'o'' is shown in Figure 7 (
8) shows the case where the DQX signal 3055 is "1". The contents of the data queue latch 301 are shifted by one stage to the output side, and the data queue control unit 305 outputs the DQX signal 3.
If 055 is 110 II, DQPIIF signal 3
054 is activated, the upper data queue pointer 303 is shifted one stage to the output side, and the DQX signal 3055 is activated.
is 1'', the DQPLF signal 3052 is activated and the lower data queue pointer 302 is shifted one stage to the output side.
The following two words of data are output. Further, the data queue control unit 305 exchanges upper/lower data of the data key 1 exchanger 304 by inverting the DQX signal 3055.

In the case of (5) (Figure 7 (9) and (10)). FIG. 7 (9) shows the case where the DQX signal 3055 is 'O''+7).
FIG. 7(10) c shows the case where the DQX signal 3055 is "1". The contents of data queue latch 301 are shifted one stage to the output side. Lower side data queue pointer 3o2. The states of the upper data queue pointer 303 and the data queue extender 304 do not change.

As a result, the next two words of data are output to the data output bus 307.

FIG. 6 is a block diagram showing the configuration of a data fetch section of a microcomputer equipped with a queue for prefetching block data, which is a fifth embodiment of the queue device of the present invention.

In the fifth embodiment, the data queue control unit 3053 determines that there is only one word of unread data in the data queue latch 301, that is, the upper data queue pointer QPII 3032 is set to "1", and the lower data queue pointer QPII 3032 is set to "1". When the data queue pointers 3022 to 3025 are all reset to 0'', a word queue ready signal 3057 indicating that data can be read in units of 1 word is output, and the data queue latch 301 is There are two or more words of data that have not been read out in the lower data queue pointer 302.
When any one of 2 to 3025 is set to 11111, word queue ready signal 5305yJ5 indicates that data reading in units of 1 word is executable.
and activates a long word queue ready signal 3056 indicating that data reading in 2-word units is executable.

When reading data from the data queue latch 301, if the data processing unit 309 is in a state in which only one word of data can be read, that is, only the word queue ready signal 3057 is active, the DQWItD
When the signal 3091 is in a state where data can be read in units of 1 word or 2 words, that is, when both the word queue ready signal 3057 and the long word queue ready signal 3056 are active, the DQWRD is activated.
Either the signal @3091 or the DQLWRD signal 3092 is output to the data queue control unit 305.

Note that the data queue fetch unit 300 in this embodiment
Since the operation is the same as that explained in FIG. 7, its explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention provides a variable-length readable queue structure, and the present invention is used as an instruction queue for prefetching instruction codes of a microcomputer or as a data queue for collectively processing a group of block-transferred data. By doing so, the following effects can be obtained.

(1) The performance of the microcomputer can be improved by suppressing the bottleneck in supplying instruction codes to the instruction execution section due to limitations on the data width of the instruction queue and by supplying a necessary and sufficient amount of instruction codes.

(2) By making the reading width of the instruction queue variable, it is possible to read immediate data in an instruction code at high speed, thereby realizing an improvement in instruction execution speed.

(3) In response to multiple read signals with different read instruction code widths, the state of the instruction queue is notified to the read destination by multiple status signals indicating the state of the instruction queue, and the read destination receives the multiple read signals. Select one from among them and read the command of the required width. Thereby, by increasing the responsiveness to read requests from the read destination, it is possible to improve the read speed from the instruction queue.

(4) By using it as a data queue, it is possible to transfer blocks of data containing a mixture of 1-word length data and 2-word length data in advance, and then read and process each data according to the data length when executing an instruction. It has become. This allows data block transfers from memory and
It is possible to execute the internal processing of the microcomputer on the transferred data in a vibrating manner, and the performance for block data processing can be greatly improved.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 respectively show the first embodiment of the cue device of the present invention. Second. FIG. 4 is a block diagram of the third embodiment, FIG. 4 is an explanatory diagram of the operation of the first to third embodiments, and FIGS. A block diagram of the fifth embodiment, FIG. 7 is an explanatory diagram of the operation of the fifth embodiment, and
9 is a block diagram of a conventional example of a cue device, and FIG. 9 is an explanatory diagram of the operation of the conventional example of FIG. 8. 100... Instruction code fetch unit, 101... Instruction queue latch, 1011-1014... Shift register, 102...
・Lower side instruction queue pointer, 1021 to 1024...
・Shift register, 103... Upper instruction queue pointer, 1031 to 1034... Shift register, 10
4...Instruction queue exchanger, 105...Instruction queue control unit, 1051...QPLB signal, 1052...QPL
F signal, 1053...QPH8PH11054...
QPHF signal, 1055- IQX signal, 1056... Long word queue ready signal, 10
57... Word queue ready signal, 106... Instruction code input bus, 107... Instruction code output bus, 108... Bus control unit, 1081... IQW'R signal, 109... Instruction execution Part, 1091...Qken RO signal, 1092...
QLenRD signal, 300...Data fetch unit, 301...Data queue latch, 3011-3014...Shift register, 302...
・Lower side data queue pointer, 3021 to 3024・
...Shift register, 303...Upper side data queue pointer, 3031-3035...Shift register,
304...Data queue exchanger, 305...
...Data queue control unit, 3051 ...QPLB signal, 5052...QP
1. F signal, 3053...QP11B signal, 50
54...QPIIF signal, 3055...-DQX(i
No. 3056...Long word cue ready signal, 30
57... Word queue ready signal, 306... Data human power bus, 307... Data output bus, 308... Bus control unit, 308... DQWR signal, 309... Data processing unit, 3091 ・...OQ RO signal, 3092...DQLWRD signal. Patent Applicant NEC Corporation Agent Patent Attorney Uchi Hara Onma 0] K, 102 Roe Hara Hara To 102 Picture ■] K, 1 o 2 Possible ■ [F] Rabbit 102 Funeral diagrams I Possible ~ 102 Possible硼6102 蹟tomoe 110" Sara-Kou [Co., Ltd.] Total 102 Fig. 102 Fig. 102 可酊 [F] Ml-102 Fig. 1 102 102 102 102 103 Fig. solid intoxication ■box, 302 solid 302 Fig. 3 o 2 times mfu H3O2 box 302 times 302 box 3o2 box 303 (1o) Figure 302 Box [F] 1 time'' 02 Hard ■] Times J502 ■Purchase 02 Times Press 502 Box ``Picture 502 Figure

Claims (1)

[Scope of Claims] 1. Storage means configured with a multi-stage shift register having a width twice the unit instruction code length or unit data length for storing instruction codes or data in FIFO, and an upper layer of the storage means upper read position indicating means for indicating the read position of the side unit length instruction code or the upper side unit length data; and lower read position indicating means for indicating the read position of the lower side unit length instruction code or the lower side unit length data of the storage means. , the upper unit length instruction code or the upper unit length data in the storage means indicated by the upper read position instruction means and the lower unit in the storage means indicated by the lower read position instruction means; exchanging means for exchanging the long instruction code or the lower unit length data; and changing the contents of the upper read position indicating means and the lower read position indicating means in response to external read and write signals; and control means for activating/inactivating.