JPS60105061A - Buffer memory - Google Patents

Abstract

PURPOSE:To reduce the deterioration of performance in a cache-off state by providing a data memory and a bypass buffer and using the bypass buffer as a data memory of small capacity. CONSTITUTION:A validity display bit for the inside of a control memory 8-2 is referred to when an access is given from a logical device 1. When the validity is decided, i.e., the desired data exists inside a data memory 6 or bypass buffer memory 7, an FB is defined. In this case, the output of the buffer 7 or the output of the 1st selection circuit 10 which are delivered via a memory 8-2, a control circuit 21 and a memory 6 is selected by the 2nd selection circuit 11 and transferred to the device 1 as the desired data. In a cathe-off mode, the FB is decided only when the store position set by the output of the memory 8-2 shows the buffer 7. In such a way, the buffer 7 is used as a data memory of small capacity to reduce the deterioration of performance in a cach-off state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a buffer storage device, and more particularly to a bypass buffer control method in a cache-off state.

(Prior Art) Conventionally, in this type of buffer storage device, a data memory and a bypass buffer have been used as a pair. Therefore, in the cache-off state, the bypass buffer is not used, and all accesses are direct accesses to the main storage device, resulting in a disadvantage that the performance is significantly lower than in the cache-on state. The bypass buffer is explained in detail in Japanese Patent Application No. 56-93040 "Buffer Storage Device".

(Object of the Invention) An object of the present invention is to provide a data memory and a bypass buffer, and to control the bypass buffer so that it can be used as a small-capacity data memory when the cache is off.
An object of the present invention is to provide a buffer storage device that reduces performance degradation in a cache-off state by storing data.

(Structure of the Invention) A buffer storage device according to the present invention includes a data memory and a bypass buffer.

The data memory is for storing part of the storage contents of the main storage device in a block format.

The bypass buffer is used to store transfer blocks from the main memory in units of one or more blocks at a time.

In the present invention, a validity display focus indicating that the contents of each block inside the bypass buffer are valid;
It includes a management table that has address information indicating the internal storage location of the main memory corresponding to each block, and when the use of the data memory is prohibited, the desired data is managed when access to the main memory occurs. If the data is in a block that is displayed as valid by referencing the inside of the table, select the read data from inside the bypass buffer as the desired data, and use the data in the block that is displayed as invalid by referencing the inside of the management table. If there is, the block data transferred from the main memory by generating an access to the main memory is stored in the bypass buffer, and at the same time, the control is configured to transfer it as desired data to the request source.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows one implementation of a buffer storage device according to the present invention.
FIG. 1 is a block configuration diagram illustrating 1 together with related devices. In FIG. 1, 1 is a logic device, 2 is a main storage device, 6 is a buffer storage device, 5 is an address register, 6 is a data memory, 7 is a bypass buffer, 8 is a management table memory, 8
-1 is the address memory, 8-2 is the management memory, 9 is the comparison circuit, 10°11.16, 17.18 are the first to
5th selection circuit, 12 is a buffer address register, 1
4.15 are first and second adder circuits, 20 is a write address register, 21-digit control circuit, and 22 is a cache-off indicating flip-flop.

In FIG. 1, a logic device 1 and a main memory device '2 are connected via a buffer memory device 3.

In the buffer storage device in this embodiment,
77 memory device fM 61r! The number of cents is 64. The number of compartments is 2. The block length is cent-associative with a block length of 32 bytes, and a system is adopted in which the management table of the bypass buffer 7 is shared within the directory section of the data memory 6. Also, block transfer from main storage device 2 to buffer storage device I\6 is 8 times per access.
Although each byte is transferred 44 times in a time-division manner, other methods may be used.

Buffer storage device 3 and address register 5.

data memory 6, bypass buffer 7, management table memory 8, comparison circuit 9, first and second selection circuits IC1, 11, buffer address register 12,
(first and second) JD arithmetic circuits 14, 15, third to fifth selection circuits 16, 17, 18, write address register 20, control circuit 21, and cache off display flip-flop 22. We are prepared.

6 data memories, main memory 1, alpha A part of the memory contents of device 2 is stored in blocks of 32 bytes long, and 8 bytes per compartment are read/accessed per access.
It has as the write data width.

Still, the bypass buffer 7 has the function of temporarily storing the transfer block from the main memory device m2, and has the function of temporarily storing the transfer block from the main memory device m2, and has the function of temporarily storing the transfer block from the main memory device m2.
It has a byte structure. Bypassing buffer 7 by using a well-known register file
It is possible to perform reading and filling at the same time.

The management table memory 8 corresponds to each block inside the data memory 6 and includes an address memory 8 - 1 for storing bits 8 to 20 of an address indicating the storage position of each block in the main storage device 2 .

A validity indicator bit indicating whether the content of each block is the same as the memory content of the main memory device 2, and a validity indicating bit indicating whether the content of each block exists in the bypass buffer 7 of the data memory 6. and a management memory 8-2 for storing storage position indicating bits.

Comparison circuit 9 is used to compare the respective outputs of two compartments of address memory 8-1 with pins 8 to 20 of address register 50.

The first selection circuit 10 selects the output of the two compartments of the data memory 6 for which the comparison circuit 9 detects a match.

Further, the second selection circuit 11 selects either the output of the first selection circuit 10 or the bypass buffer 7 for the storage position indication bit in the management memory 8-2 and the contents of the cache-off indication flip-flop 22. .

12 buffer address registers, 7 bypass buffers
A 6-bit address indicating the storage location of the data memory 6 is stored corresponding to the internal block of the data memory 6. The first and second adder circuits 14 and 15 add the input address information of the 2 pins by "+" modulo "4" (that is, when the addition result is 14), Then, the 2-bit addition result is output. It still supplies a write address to the write address register 201d and the bypass buffer 7. The read address for bypass buffer 7 is supplied with bit 27°2B of address register 5. Further, the control circuit 21 is configured to perform communication for access control between the logic device 1 and the main memory device 2 and to control each circuit inside the buffer storage device 3.

Next, the operation of this embodiment in various cases will be explained.

In the following explanation, as a result of referring to the internal validity display focus of the management memory 8-2 at the time of access from the logical device 1,
When it is "valid", that is, when it is determined that the desired data exists inside the data memory 6 or the bypass buffer 7, it is called [FBJ]. Conversely, a case where the data is found to be "invalid" and the desired data must be accessed and fetched from the main storage device 2 is called rNFBJ.

[In case of FB] ■ By referring to the storage position indication bit which is the output of the management memory 8-2 and the contents of the cache-off indication flip-flop 22 by the control circuit 21, the first bit which is the output of the data memory 6 is Selection circuit 10 (7'> output,
Alternatively, the output of the bypass buffer 7 is sent to the second selection circuit 1.
1 and transfer it to the logical device 1 as desired data.

If the contents of the cache-off display flip-flop 22 indicate the cache-off state, the storage position according to the output of the management memory 8-2 indicates the bypass buffer 7, and becomes rFBJ only when the storage position is indicative of the bypass buffer 7.

[In case of NFB in cache-on state] The block stored in the previous NFB bypass server 77a7 is designated as block A, and the block that has become NFBK this time is designated as block B.

- The control circuit 21 generates an access request to the main storage device 2, selects one of the two compartments using a known replacement algorithm from the prior art, and stores the selected information in the management table memory 8. Store bits 8 to 20 of the output of address register 5 in the compartment, as well as the validity indication and 7)
The above two bits are stored with the polarity so that the storage position display focus is indicated in the bypass buffer 7. Through this operation, a read request for block B is made to the main storage device 2, and information regarding block B is registered in the management table memory 8.

■ Bits 21 to 26f of the output of address register 5,
The output of the buffer address register 12 is sent to the buffer address register 12 via the third selection circuit 16 to bits 21 to 26 of the address register 5, and the contents of each 6 bits of the address register 5 and buffer address register 12 are exchanged. bits 27.28'5 of the output of address register 5 are stored in the write address register 20. ), bit 21 of address register 5
26 indicates the address for block A, the contents of the buffer address register 12 indicate the address for block B, and the contents of the address register 2o,
The position of the first 8 bytes of data in block B transferred from the main storage device 2 is shown.

■ How to output address register 5) 27.28f.

One word, ie, 8 bytes of data inside the bypass buffer 7 is read out as a read address input and stored in the data memory 6. Bit 2 of address register 5 output
1 to 26 are used as address inputs to view the contents of the management memory 8-2, the control circuit 21 directs the compartment indicating the bypass buffer 7 to the data memory 6 by displaying the storage position, and outputs the address register 5. Bits 21 to 28 of the data memory 6 become the write address. With this operation, 8 bytes of the block are transferred from the bypass buffer 7 to the data memory 6.

゛Furthermore, the pin point 27.2 of the output of address register 5
8 is incremented by +1 in the adder circuit 14 and incremented by 2, and the addition result is stored in the bit 27.2B of the address register 5 via the fourth selection circuit 17.

By repeating the above operation four times, the transfer from the bypass buffer 7 to the data memory 6 is completed.

■ Set the storage position indication bit to the management memory 8-2 with a polarity that indicates that block A exists in the data memory 6.
Store in. Furthermore, ((, the read operation in +storage device δ2 due to access to main storage device 2 is completed, and main storage device 2
After waiting for the block transfer to the bypass buffer 7 to start, the following operation is performed.

■-■ 8-byte transfer data from the main storage device 2 is bypassed to the write address register 20 inside the buffer 7.
is stored at the address location indicated by the output of . Furthermore, the output of the write address register 20 is incremented by adding [+1] in the adder circuit 15, and the addition result is stored in the write address register 20 via the fifth selection circuit 18. Through this operation, 8 bytes of block B are stored in the bypass buffer 7.

■-■ In addition to performing the same operation as in ■-■, bits 27 and 28 of the output of the address register 5 are read out, and the output of the bypass buffer 7 is used as the second selection circuit 11.
The data is transferred to logical device 1 via , and operation in logical device 1 is resumed. These 2 bits are used only 4 times in step ■ [+1]
Because of the addition of , the value returns to the original value when the access request was made from the logical device 1.

By repeating the same operation as (1)-(2)-6) twice, storage from the main storage device 2 to the bypass buffer 7 is completed.

[In the case of NFB in the cache-off state] The differences from the above description of the operation in the case of NFB in the cache-on state are as follows. In other words, after step ■ and step ■, step ■ is performed without performing step ■.
Control so that the operation of is completed, substep ■−■,
Execute substeps ■-■ and substeps ■-■.

(Effects of the Invention) As explained above, the present invention is equipped with a data memory and a bypass buffer, and draws control so that the bypass buffer is in a cache-on state and is used while pretending that a small-capacity data memory exists. By doing so,
This has the effect of minimizing performance degradation in the cache-off state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a buffer storage device according to the present invention together with related devices. 1.9 fist logic device 2@...Main memory device 6...Buffer storage device 5...Address register 6...Data memory 7...Bypass buffer 8...Management table memory 8-1.e -Address memory 8-2--Management memory 9--Comparison circuit 10.11.16.17.18--Selection circuit 12e-
・Buffer address register 14, 15...Addition circuit 20...Write address register 21...Control circuit 22...Cash-off display flip-flop patent issuer Hisashi Inoro, Patent attorney, NEC Co., Ltd.

Claims (1)

[Claims] A data memory for storing part of the storage contents of the main storage device in block units; and a bypass buffer for storing transfer blocks from the main storage device in block units of one or more blocks at a time. , including a management table having a validity indicator indicating that the content of each block inside the bypass buffer is valid, and address information indicating a storage location inside the main storage device corresponding to each block; When the use of the data memory is prohibited, if the desired data is data in a block that is validly displayed by reference to the management table at the time when the main storage device is accessed, the data stored in the bypass buffer is Select read data from the main memory as the desired data, and if the data is in a block that has been invalidated by reference to the management table, an access to the main memory will be generated. A buffer storage device characterized in that control is configured to store pronk data transferred from the bypass buffer in the bypass buffer and at the same time transfer it to the request source as the desired data.