JPH05313888A - Instruction buffer system - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to enable high integration by constituting an instruction by a specified register file or a RAM and controlling the register file or the RAM by write and read pointers. CONSTITUTION:The system is provided with a memory for storing programs and an instruction buffer for taking out the instruction from the memory to be stored prior to the execution of the instruction. The instruction buffer is constituted of register files 600, 610,... or the RAM with the width of the minimum unit (2 bytes for example) of the instruction length in the arrangement so as to be the width (8 bytes) capable of fetching the instruction from the memory at one time. A write pointer 700 indicates a head position for writing at the next fetch of the instruction and a write address circuit 701 controls the write address of the register file and a write enable signal with the value of the pointer. A read pointer 800 indicates the head position of the instruction to be executed next and a read address circuit 801 controls the read address with the value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program storage system computer, and more particularly to an instruction buffer system in which instructions are sequentially fetched from a memory into a buffer prior to execution.

[0002]

2. Description of the Related Art In a computer of a program storage system, it is necessary to fetch a machine instruction from a memory, that is, perform an instruction fetch when executing the program. This fetching can be done immediately before the execution of the instruction, but in order to improve the performance of the computer, this fetching is done in advance and stored in a FIFO (first in first out) type buffer called an instruction buffer. There has been devised an instruction buffer system in which instructions are sequentially fetched from and executed. Traditionally,
This instruction buffer was composed of a shift register composed of flip-flops (hereinafter referred to as FF).

As a conventional example, an instruction buffer having a shift register structure in units of 2 bytes is shown below, and each operation will be described. In FIG. 10, in a computer system in which the instruction length is a unit of 2 bytes and the values are 2, 4, and 6 bytes, the instruction fetch can be performed up to 8 bytes in units of 2 bytes at a time, and the size of the instruction buffer can be increased. An example of an instruction buffer whose size is 16 bytes is shown.

In FIG. 10, 100 to 107 are registers each having a width of 2 bytes, 110 to 117 are input selectors of the registers 100 to 107, and 110-.
x to 117-x are inputs to the selectors 110 to 117, 200 is a fetch circuit, 300 is a branch destination fetch circuit, 400 is an effective length control flag group, 410 is an effective length update circuit, and 500 is a shift amount control circuit.

The effective length control flag group 400 is a flag group showing registers which hold an instruction which has not been executed in the shift register. When an effective flag is provided for each register of 2 bytes. Alternatively, it may be configured as a pointer indicating which position from the beginning is effective. Here, the pointer system is assumed to indicate the following states depending on its value.

[0006]

[Table 1]

As can be seen from Table 1, if the pointer (effective length control flag 400) is 0 ---- (-represents don't care), the contents of registers 100-107 are all invalid. If the effective length control flag 400 is 1001, only the contents of the register 100 are effective, that is, the effective length of the instruction buffer is 2 bytes. Also, the effective length control flag 4
If 00 is 1010, register 100 and register 101
Is valid and the contents of other registers are invalid, that is, the effective length of the instruction buffer is 4 bytes.

The instruction fetch is performed by the fetch circuit 200, and the fetch amount (the number of bytes of the fetched instruction) is sent to the shift amount control circuit 500 and the effective length updating circuit 410 by a signal 502. The shift amount control circuit 500 uses the value of the signal 502 and the effective length flag group 400.
The input selectors 110 to 110 as shown in Table 2 below depending on the value of
Control 117. However, it is assumed that an instruction fetch that exceeds the capacity of the instruction buffer (16 bytes in this case) does not occur.

[0009]

[Table 2]

As can be seen from Table 2, the pointer (effective length control flag 400) is 0 ---, and the fetch amount signal 50
If 2 is 2 bytes, selector input 11 of register 100
0-1 is selected and the value of the pointer after fetch is 0
It is set from --- to 1001. If the pointer is 0
--- and the fetch amount signal 502 is 4 bytes,
Selector input 110-1 of register 100 and register 1
The selector input 111-2 of 01 is selected, and the value of the pointer after fetching is set from 0 --- to 1010. If the pointer is 1001 and the fetch amount signal 502 is 2 bytes, the selector input 111-1 of the register 101 is selected, and the pointer value after fetch is set to 1001 to 1010.

When the instruction is executed, the registers 100 to 1 forming the instruction buffer according to the instruction length.
The instruction is read from 07 and executed. The instruction length of the instruction to be executed is determined by the signal 501 by the shift amount control circuit 500,
And the effective length update circuit 410. At the same time, the register values corresponding to the other instructions are sequentially shifted in the same unit as the length of the executed instruction.

The shift amount control circuit 500 operates according to the value of the signal 501 as shown in Table 3 below.
Control 117. As can be seen from Table 3, if the signal 501 indicating the instruction length of the execution instruction is 2 bytes, the selector input 110-
5, selector input 111-5 of register 101, selector input 112-5 of register 102, selector input 113-5 of register 103 ... Input selector 116-5 of register 106 is selected, and the value of the pointer is It is set by subtracting 1 from the value of the pointer before executing the instruction. That is, the contents of the register 101 are stored in the register 10
Move to 0, move the contents of register 102 to register 101, and set the value of the pointer by subtracting 1 from the value of the pointer before executing this instruction. If the signal 501 indicating the instruction length of the execution instruction is 4 bytes, the contents of the register 102 are moved to the register 101, the contents of the register 103 are moved to the register 101, the contents of the register 104 are moved to the register 102, and the pointer The value is set by subtracting 2 from the value of the pointer before executing this instruction. The principle of this pointer subtraction is shown in Table 4. For example, if the pointer is 1001, the pointer value after subtraction will be 0000. However, if the effective instruction length in the instruction buffer is less than the instruction length of the instruction to be executed, the execution of the instruction is not started. That is, this instruction cannot be executed because only a portion of this instruction is stored in the instruction buffer. Therefore, this instruction must be fetched again from memory.

[0013]

[Table 3]

[0014]

[Table 4]

Actually, the instruction fetch and the instruction execution start are performed at the same time, that is, the instruction is often fetched from the memory to the instruction buffer while executing the instruction.
Controls shown in Tables 5 to 8 are performed according to the instruction length and the fetch amount of the executed instruction. The case where only one of them is performed is as shown in Table 2 above. That is,
Tables 5 to 8 show the pointer 4 according to the instruction length and the signal 501 and the fetch amount 502 signal which are executed when the instruction is fetched from the memory into the instruction buffer while executing the instruction.
00 and the selector input of each register are controlled. For example, the pointer value is 1001, the execution instruction length signal 501 is 2 bytes, and the fetch amount signal 5
If 02 is 2 bytes, the selector input 110-1 of the register 100 is selected, and the updated pointer value is 1001.

[0016]

[Table 5]

[0017]

[Table 6]

[0018]

[Table 7]

[0019]

[Table 8]

Next, fetching of a branch destination instruction will be described. When executing a branch instruction, if a branch is taken, it is necessary to fetch the branch destination instruction into the instruction buffer. Here, the branch destination instruction is the branch destination fetch circuit 3
00 shall be fetched.

The branch destination fetch circuit 300 shifts the fetch amount according to the signal 503 to the shift amount control circuit 500,
And the effective length update circuit 410. Table 9 below shows the relationship between the selector inputs 110-t, 111-t and 112-t from which the branch destination fetch amount signal 530 is selected, and the pointer value after fetch. Here, it is assumed that the branch destination instruction is in the instruction buffer. Since the branch destination instruction is taken into the instruction buffer only when the branch is taken, the branch determination result signal 700 from the branch determination circuit (not shown) is sent to the shift amount control circuit 500 and the effective length update circuit 410. As can be seen from Table 5, if the branch destination fetch amount signal 503 is 2 bytes, the register 100
The selector input 110-t is selected, and the pointer value after fetching becomes 1001. Branch destination fetch signal 503
Is 4 bytes, the selector input 110 of the register 100
-T and the selector input 111-t of the register 101 are selected, the value of the pointer after fetching becomes 1010.

[0022]

[Table 9]

Depending on the method of constructing the branch target instruction, the branch target instruction may be fetched from the fetch circuit 200, that is, the branch target instruction may not be in the instruction buffer.
In that case, the value in the instruction buffer until then is invalidated by the branch taken (that is, the value of the effective length flag group 400 is set to "0
····· ”), the selector and pointer may be controlled in the same manner as in the case of instruction fetch.

[0024]

The above conventional instruction buffer has the following problems. Problem (1) It is desirable that the buffer capacity be reasonably large, although it depends on the instruction execution speed (speed at which instruction execution starts).
However, even with recent LSIs, it is desirable that the circuit scale be small. That is, it is important to determine the trade-off between circuit scale and capacity. However, since the conventional instruction buffer described above consists of FFs (flip-flops),
The operation speed is high, but the circuit scale is large. Problem (2) In the case of a computer whose instruction length is not fixed, the shift amount in the buffer is also not fixed, which complicates the structure of the FIFO register. For example, as shown in FIG.
Several selectors are used to construct O.
Also, many wirings are required between the FFs.

The present invention simplifies the circuit configuration and enables the LSI
It is an object of the present invention to provide an instruction buffer system that can be highly integrated and operates at a high speed when it is realized.

[0026]

In order to solve the above problems, the present invention uses a register file or a RAM instead of an FF to form an instruction buffer. A write pointer and a read pointer are set in order to write an instruction to this register file or RAM or read an instruction from the register file or RAM.
Since these pointers are provided, the conventional FF shift operation is unnecessary. Therefore, the scale of the circuit is reduced. Further, by using these pointers, the processing for branch instructions can be easily performed. Register file or RA
Since the read speed of M is slower than that of FF, the instruction buffer method according to the present invention stores some or all of the next instruction to be executed in FF.

The present invention utilizes the fact that the register file and the RAM are highly integrated as compared with the normal gate and FF (Flip-Flop). The instruction buffer of the present invention is configured by arranging register files (or RAM) so that the instruction buffer has a width that satisfies both the write side and the read side.
On the write side, register files (or RAM) having a width with the minimum instruction length as a unit are arranged so that the width can be fetched at once from the memory device. For example, in a system with instructions of 2, 4, 6 bytes long,
If the width that can be fetched at one time is 8 bytes in units of 2 bytes, at least 4 register files (or R
AM) are arranged.

On the read side, the register files (or RAM) are arranged so that the instruction with the maximum instruction length can be read at one time. For example, in a system having an instruction having a length of 2, 4, or 6 bytes, if 2 bytes are used as a unit, it is necessary to arrange at least three register files (or RAM).

The capacity of each register file (or RAM) is the number of words (cumulative multiplication of 2) that is larger than the number of register files (or RAM) used and the width of the required instruction buffer capacity. Choose. (Example) Required instruction buffer capacity: 30 bytes Number of register files (RAM) used: 4 Width of register file (RAM) used: 2 bytes 30/4/2 = 3.75 → 4 words As a pointer Registers are provided on the write side and the read side, and the bit width is the number of bits that can be represented by the combination of a value obtained by dividing the total capacity of the instruction buffer by the width of the register file (or RAM). (Example) In the case of the example configured with the width of 2 bytes, the number of words of 4 words, and the number of 4 as described above, the total capacity is 2 bytes × 4 words × 4 = 32 bytes log2 (32/2) ≦ 4 and thus 4 bits. Width.

The write pointer indicates the head position where writing is performed in the next instruction fetch. According to the transfer instruction from the memory device, the fetch amount is updated by the number divided by the width of the register file (or RAM) used.

The read pointer indicates the head position of the next instruction to be executed. According to an instruction execution start instruction from the instruction execution control device, the length of the instruction whose execution has started is updated by the number divided by the width of the register file (or RAM) used.

The value obtained by subtracting the value of the read pointer from the value of the write pointer becomes the length of the valid instruction sequence in the instruction buffer. However, when both pointers point to the same value, it is all It is not possible to determine whether is valid or all are invalid.

Therefore, a valid flag indicating that there is a valid instruction fetched in the instruction buffer is provided (of course, a flag indicating that the instruction is full in the instruction buffer may be prepared).

Next, the write align and the read align will be described. In the instruction buffer method, fetch data needs to be divided into a plurality of register files (or RAM) and written simultaneously. It is only in the following cases that the byte position of fetch data sent from the fetch circuit and the register file (or RAM) to be written always match.

That is, the fetch amount is always constant, and
This width is the same as the total write width of the register files (or RAM) forming this instruction buffer system (register file of 2 byte width (or 8 bytes when four RAMs are arranged)).

In other cases, the byte position of fetch data and the register file to be written (or RA
M) does not match. For example, in the case of a configuration in which four 2-byte-wide register files (or RAMs) A, B, C, and D are arranged, when the first 2-byte fetch is performed, the 2-byte register file ( Or R
AM) and then fetch 4 bytes, write the first 2 bytes to B register file (or RAM) and the latter 2 bytes to C register file (or RAM). There is a need.

When 4 bytes are fetched subsequently, the first 2 bytes are written to the D register file (or RAM) this time, and the latter 2 bytes are written to the A register file (or RAM). There is a need to.

Therefore, a circuit for rearranging the fetch data from the fetch circuit according to the value of the write pointer at that time, that is, a write align is provided.
In this instruction buffer method, when fetching an instruction from the register file (or RAM), the register file (or RA that should be fetched according to the value of the read pointer).
M) and their addresses, and the fetched data must be rearranged in the correct order and sent to the instruction controller. This rearrangement circuit is called read-align.

The reason why rearrangement on the read side is necessary can be explained in the following cases. In the case of a configuration in which four 2-byte-wide register files (or RAMs) A, B, C, and D are arranged, if the 2-byte instruction from A is executed first, the next instruction starts from B. Thus, if a 4-byte instruction is executed here, the first 2 bytes of the instruction must be taken from B and the next 2 bytes from C. If a 4-byte instruction is executed next, the first 2 bytes are from D and the next 2 bytes are from A.
You need to take it out from.

The register file (or RAM) from which the instructions executed in this way are fetched is different every time. Therefore, rearrangement is also required on the lead side.
When fetching an instruction from the instruction buffer, it is usually called a decode cycle. In this cycle, it is necessary to perform a lot of processing such as reading a general-purpose register for address calculation and reading a micro instruction in a micro computer. The machine cycle may be determined by the instruction fetch speed from the instruction buffer. However, generally, the read speed of the register file and the RAM is slower than that of the FF. Therefore, if the RAM or the register file is simply used instead of the FF, the speed of reading the instruction from the instruction buffer becomes slow. According to the present invention, a part or all of the instructions whose execution is started are stored in the register file (or RA
Instead of M), the FF (Flip-Flop) is used. This utilizes the fact that reading of FF ((Flip-Flop) is faster than that of a register file or RAM.

The portion requiring high speed is set as FF, and that portion is set from the instruction buffer immediately before the instruction execution start cycle. In addition, register file (or RA
The read side of the instruction buffer composed of
It will be configured so that it can lead an extra amount of width that needs to be converted.

The capacity of the FF is, for example, 1 in the case where only the first byte of the instruction code needs to be speeded up.
It becomes a part-time job. If the instruction buffer is empty or if the branch destination instruction is fetched, the fetch data of the corresponding portion of the first instruction is set to FF when fetching to the instruction buffer. If the instruction buffer is full of instructions, when the instruction is started, the relevant portion of the next instruction is set in the FF from the portion provided on the read side.

In order to perform the read control from the instruction buffer, the read side of the instruction buffer constituted by the register file (or RAM) has the length of the portion constituted by this FF which is the read width determined by the maximum instruction length described above. It is expanded to suit the size.

For example, when three register files (or RAMs) each having a 1-byte width are arranged according to the above-mentioned example, another register file (or RAM) is added when 1 byte FF conversion is required, Also, 3
In the case where FF conversion of bytes is necessary, another two register files (or RAM) are added.

According to the present invention, a new branch destination instruction fetch method is used in response to the use of the write pointer and the read pointer. That is, a unit for selecting the fetch from the fetch unit for normal instruction prefetching and the fetch from the fetch unit of the branch destination instruction string and storing it in the instruction buffer is provided, and the write pointer / read pointer / valid flag is used for the branch determination operation. It has been taken into consideration. For example, in the case where the branch determination cycle and the fetch of the branch target instruction sequence are the same cycle, if the branch determination is satisfied, the fetch data from the fetch unit of the branch target instruction sequence is registered in the instruction buffer. The write address is set to the address 0, the read pointer is set to that address, and the write pointer is obtained by adding the fetch amount, thereby canceling the instruction string existing in the instruction buffer until immediately before.

[0046]

First Embodiment (Embodiment of Case where Width of Instruction Buffer Has Width Equal to Fetch Amount) FIG. 1 shows that the minimum unit of instruction length is 2 bytes, the width that can be fetched at one time is 8 bytes, and the maximum instruction length is 6 bytes. An embodiment of an instruction buffer in which the first byte of the instruction is composed of FF for speeding up the byte is shown.

As a condition on the write side, it is necessary to arrange four or more 2-byte width register files 600, 610, 620, 630 (or RAM: hereinafter referred to as RF) so as to have an 8-byte width. is there.

As a condition on the read side, assuming that 2 bytes is a unit, 6 bytes, which is the maximum instruction length, and 4 or more RF60s, so that 1 byte for the next instruction can be read at the same time.
It is necessary to arrange 0, 610, 620, and 630.

As the capacity, it is necessary to arrange four or more RFs each having a 2-byte width depending on the conditions on the write / read side. The number is 4 because there is no need to arrange more than necessary.
By arranging four 2-byte width RFs, the RF can select the following capacity from the number of words. Table 10
Indicates the correspondence between the number of words and the total capacity in the case of this embodiment. For example, if the number of words is 4, the total capacity is 32.
It becomes a part-time job.

[0050]

[Table 10]

In the configuration of FIG. 1, a word and a total capacity of 32 bytes are selected. That is, since the width fetched at one time is 8 bytes, the width that can be fetched at one time is one word. In this embodiment, since the total capacity of the instruction buffer is 4 words, four basic units each composed of four RFs each having a width of 2 bytes are arranged side by side to form an instruction buffer. In addition, RF600, 610, 620 and 6 in FIG.
(0), (1), ... (f) shown in 30 are R
It is the name given to each word in F, which is just (0), (1), ... (f) followed by (0), (1),
... and so on. Circular register (ie mode is 1
6) is configured. Pointer 16 minimum units (0), (1), ... As shown in FIG.
In order to be able to address (f), pointers (write pointer 700 and read pointer 80
The width of 0) will be 4 bits.

The write pointer 700 indicates the head position where writing is performed by fetching the next instruction. Depending on the fetch amount indicated by the signal 201 in the fetch circuit 200, +1 (in the case of 2-byte fetch), +2 (4
A circuit 705 for providing (byte), +3 (6 bytes), and +4 (8 bytes) is provided. That is, after writing a certain instruction, the length (number of bytes) of the written instruction is added to the write pointer 700.

The write address circuit 701 controls the RF write address and write enable signal according to the value of this pointer. The write addresses for RF600, 610, 620, and 630 are 601 and 6 respectively.
11, 621, and 631, and write enables are indicated at 602, 612, 622, and 632, respectively.

Write pointer 700 and write address 6
The relationship between 01, 611, 612 and 631 and write enable 602, 612, 622 and 632 is shown in FIG.
Shown in. That is, the addresses 601, 611, 621, and 631 are RF600 ((0), (4),
(8), (c)), RF610 ((1), (5),
(9), (d)), RF620 ((2), (6),
(A), (e)) and RF630 ((3), (7),
It is a local address that points to (b) and (f).
The values of these addresses 601, 611, 621 and 631 are calculated corresponding to the write pointer 700.

FIG. 2 shows this calculation relationship. For example, if the write pointer 700 is 0000, RF600, RF6
10, addresses 601 and 6 of RF620 and RF630
11, 612 and 631 are 0, 0, 0, 0, respectively. A 601 of 0 means that address 601 points to word (0) of RF 600. 61
If 1 is 0, it means that address 611 is RF610
Means to refer to the word (1) of. Although the address of each RF is selected by the write pointer 700, whether to write a command to each RF is determined by the write enable signal of each RF. These write enable signals are determined by the second table in FIG. For example, if the fetch amount signal 201 ((2) in Table 2) is 00 and the lower 2 bits of the write pointer ((1) in Table 2) is 00, RF600, RF610, RF6
20 and write enable signals 602, 6 of RF630
12, 622 and 632 are 1, 0, 0 and 0, respectively. That is, only RF600 is selected.

The read pointer 800 indicates the head position of the next instruction to be executed. When an instruction is executed according to an instruction from an instruction execution control unit (not shown), the instruction length of the instruction (normally this is found from the instruction code of the instruction to be executed, so in this example, a read-align circuit that controls the fetching of the instruction +1 (for a 2-byte instruction), +2 (4
And a circuit 805 for performing +3 (6 bytes). That is, after reading a certain instruction, the length (number of bytes) of the read instruction is added to the read pointer 800.

The read address circuit 801 controls the RF read address according to the value of this pointer. RF
The read addresses for 600, 610, 620, and 630 are 603, 613, 623, and 633, respectively.
Indicated by. FIG. 5 shows the relationship between the read address circuit 801 and the write addresses 603, 613, 623, and 633.
Shown in. Read addresses 603, 613, 623, and 633 are RF600, RF610, and RF620, respectively.
And a local address pointing to RF 630. As can be seen from FIG. 5, the read pointer 800 is 0000.
Then RF600, RF610, RF620 and RF6
30 read addresses 603, 613, 623 and 63
3 is 0, 0, 0, 0, respectively. The fact that 603 is 0 means that the read address 603 points to the word (0) of the RF 600. The fact that 613 is 0 means that the read address 613 points to word (1) of RF 610, and so on.

The valid flag 1150 is a flag indicating that valid data is held in the instruction buffer.
When this flag is 0, it is assumed that valid data is not held.

The value of the valid flag 1150 is determined by the valid flag updating circuit 1155. The valid flag updating circuit 1155 has a fetch amount signal 201 and an execution instruction length signal 1
In addition to 001, a write pointer 700, a read pointer 800, and a signal 1159 for forcibly invalidating the contents of the instruction buffer when a branch of a branch instruction is taken are given.

The conditions for updating this flag are shown below. (Set condition) [(No branch judgment) + (No branch taken)] & [(Number of bytes held in the instruction buffer) + (Number of bytes written)-(Instruction length at which execution starts)> 0 ] + [Branch taken] & [Branch destination fetch is performed] (Reset) [(No branch judgment) + (Branch not taken)] & [(Number of bytes held in the instruction buffer) + (Bytes written Number)-(instruction length at which execution is started) = 0] + [branch taken] & [branch destination fetch not performed] The number of bytes held in the instruction buffer is the difference between the write pointer 700 and the read pointer 800. , And the value of the valid flag 1150, as shown in FIG.

The write-align circuit 900 that rearranges the fetch data 210 sent from the fetch circuit 200 so that it can be written to RF includes RF 600, 610,
Write data for 620 and 630 for 9
Output to 10, 911, 912, and 913.

The write align circuit 900 is controlled by the fetch amount 201 and the value of the write pointer 700, but depending on the configuration of the fetch circuit 200, the head position address 211 sent from the fetch circuit 200 is also required.

As the fetch data from the fetch circuit 200, if the leading data of the fetch is always sent to the byte 0 of the fetch data line 210 as shown in FIG. 4A, the write align circuit 900 causes the write align circuit 900 of FIG. It may be controlled like the write align (A). In this case, only the lower 2 bits of the write pointer are exclusively used for the control. On the other hand, when the fetch data is sent from the fetch circuit 200 to the fetch data line 210 as shown in FIG. 4B, the write align circuit 900 operates as shown in FIG.
It may be controlled like the write align (B). That is, FIG. 3 shows the operation of the write align circuit 900 for rearranging. Next, this operation will be described in more detail.

When the start of the transfer data from the fetch circuit 200 is always in byte 0 (A), the value of the fetch amount signal 201 (00: 2 bytes, 01: 4 bytes, 1
The transfer data from the fetch circuit 200 is sent to the output 910, 911, 912 or 913 of the write align circuit 900 only by the number of bytes designated by 0: 6 bytes, 11 to 8 bytes). Also, transfer data byte and output 9
The correspondence with 10, 911, 912 and 913 is determined by the lower 2 bits ((2) in FIG. 3) of the write pointer. For example, as can be seen from the write line (A) in FIG. 3, if the lower 2 bits ((1) in FIG. 3) of the write pointer 700 are 00 and the fetch amount signal 201 ((2) in FIG. 3) is 01. The first 2 bytes (I01) of the fetched data are output to 910, and the last 2 bytes (I23) of the transferred data are output to 911. Also,
Lower 2 bits of the write pointer 700 ((1) in FIG. 3)
Is 01 and the fetch amount signal 201 ((2) in FIG. 3)
Is 01, the first 2 bytes of the transferred data (I0
1) is output to 911, and 2 bytes (I23) after the transferred data are output to 912.

On the other hand, when the first byte of the transfer data from the fetch circuit 200 is not always byte 0 (B)
As shown in the write align (B) of FIG. 3, the value of the fetch position signal 210 (00: byte 0 is the beginning, 0
The position of the head byte designated as 1: byte 2 is the head, 10: byte 4 is the head, 11: byte 6 is the head) and the data transferred by the write align circuit 900 is arranged by the lower 2 bits of the write pointer. Change. For example, if the fetch position signal 211 ((3) in FIG. 3) is 01, the first byte is in byte 2, as shown in FIG. 4 (b). In this case, if the lower 2 bits of the write pointer ((1) in FIG. 3) are 00, I2 of the transferred data
No. 3 (actually the first 2 bytes) is output to the output line 910, I45 is output to the output line 911, and I67 is output to the output line 9
12 and outputs I01 to the output line 913 (in this case, the rearrangement operation is shown). If the lower 2 bits of the write pointer are 01, I23 (actually the first 2 bytes) of the transferred data is output to the output line 911, I45 is output to the output line 912, and I67 is output to the output line 913. , I12 to the output line 910.
That is, the write align circuit 900 rearranges the fetched data according to the head position signal 211 of the fetched data and the lower 2 bits of the write pointer. Figure 4
4A is a diagram showing the data and the fetch amount in the fetch circuit 200 in the case of FIG. 3A, and FIG.
FIG. 4 is a diagram showing the data in the fetch circuit 200, the head position of the data, and the fetch amount in the case of FIG. 3B.
Read-align circuit 1000RF600, 610, 62
The instruction sequences fetched from 0 and 630 are rearranged by the read align circuit 1000 and sent to an instruction execution control unit (not shown). In the read align circuit 1000, the head portion of the instruction to be fetched is output to the output line 1010,
The next part is output to the output line 1011 and the next part is output to the output line 1012. (Output line 101
1, whether the output line 1012 is required depends on the maximum length of the instruction to be fetched. In this example, the minimum unit is 2 bytes,
Since it is assumed that there is a maximum 6-byte instruction, three sets of 2-byte width output line 1010, output line 1011 and output line 1012 are set. The rearrangement control in the read align circuit 1000 is performed by the read pointer 8
A value of 00 is used.

In the structure having the speed-up register 1100, it is necessary to fetch the part following the instruction fetched for execution and send it to the speed-up register. For this purpose, the read-align circuit 1000 is provided with an output 1020.

This output 1020 is the read pointer 80.
It is controlled by the value of 0 and the instruction length which is usually found from the instruction code of the fetched instruction. The state of these controls is shown in FIG. That is, the lower 10 bits of the read pointer ((1) in FIG. 6) and the instruction length signal 1001 ((2) in FIG. 6) output 1010,
Reference numerals 1011 to 1012 and 1020 indicate the correspondences (not one-to-one correspondence) with the outputs RF600, 610, RF620 and RF630 of the instruction buffer. For example, if the lower 2 bits ((1) in FIG. 6) of the read pointer is 00 and the instruction length signal 1001 is 01 (2 bytes),
The output of RF600 is output to 1010, the output of RF610 is output to 1011, and the output of RF620 is output to 1012. Also, the output of the RF 610 is output to 1020, that is, the next command to be executed and the first 2 bytes are 102
Output to 0 and write to the high speed register 1160. If the lower 2 bits of the read pointer are 01 and the instruction length signal 1001 is 16 (4 bytes), the output of RF610 is output to 1010, the output of RF620 is output to 1011 and the output of RF630 is output to 1012. Also RF
The output of 630 is output to 1020. In this case, a rearrangement operation is represented.

In order to speed up the instruction reading from the instruction buffer, this is a register for latching the head portion (here, 1 byte as described above) of the instruction buffer. This register has an output 91 of the write align circuit 900.
The leading 1 byte of 0 (described later in detail) and the output 1020 (1 byte width) of the read align circuit 1000 are selectively input.

Since the RAM is slower in reading the instruction than the register, the head portion of the instruction buffer is latched in the register. The contents of this register are read align circuit 10
It is the first 1 byte of the output 1020 of 00 or the output 910 of the write align circuit 900. Normally, the contents of this register are output 1020 of the read align circuit 1000.
Is. If the branch instruction is a branch taken, that is, if the instruction in the buffer is invalid, the content of this register is set to the output 914 of the write align circuit 900.

Next, the overall operation of the instruction buffer will be described with reference to FIG. Control (initial value) Write pointer 700 = 0000 Read pointer 800 = 0000 Valid flag 1150 = 0 Instruction fetch When the fetch from the fetch circuit 200 is performed, the instruction buffer knows this by a signal not shown, and RF600
To 630 and the write pointer 700 and the valid flag 1150 are updated.

As to the control of the write address and the write enable, as can be seen from FIG. 2, the write address circuit 701 uses the write pointer to control the RF600 and RF6.
10, write addresses of RF620 and RF630 are determined. In addition, this write address circuit 701
Are RF600, RF610, RF620 and RF depending on the write pointer and the instruction length of the fetched instruction.
The write enable signal of 630 is controlled. The valid flag 1150 is normally turned on when a fetch is performed. This is because the number of bytes written in the above equation is 0.
This is because, in the above case, the instruction length to be executed is no more than the number of bytes already held in the instruction buffer.

The write align circuit 9 is added to the speed-up register.
The first byte of 910, which is the output of 00, is directly written when the instruction buffer is empty, and when the instruction length of the instruction to be executed is equal to the number of bytes held, and when the branch destination instruction is fetched. Only in case. This is because the value held in the speed-up register 1100 is the first byte of the instruction to be executed. Therefore, when the instruction is held in the normal instruction buffer, the read-align circuit 10 is used.
Output 1020 of 00 to get 1 byte of the subsequent part of the instruction to be executed and set it, and if the instruction buffer is empty, set it to the beginning when it is written to the fetched instruction buffer In fetching when the instruction instruction buffer becomes empty as the instruction is executed, this fetch data is set because it becomes the beginning of the next instruction, and it is retained until the branch is taken. This is because the instruction on the non-branch side that had been abandoned is discarded and the newly fetched branch destination instruction is executed next, so the leading part is set. Execution of normal instruction The length of a normal instruction can be found by looking at the instruction code. For example, the instruction length can be known as follows from the value of the first two bits of the instruction code.

[0073]

[Table 11]

When this instruction length is equal to or less than the byte length held in the instruction buffer and the other instruction start conditions are satisfied, the instruction execution control unit (not shown) gives an instruction to fetch the instruction and the read pointer 800, Valid flag 11
50 and the speed-up register 1100 are updated. The control of the read address is shown in FIG. The control of the read align circuit is shown in FIG. That is, as can be seen from FIG. 5, the read address circuit 801 uses the read pointer to read each RF.
Determine the local read address of. Further, as can be seen from FIG. 6, the read align circuit 1000 controls the read align circuit by the read pointer and the instruction length signal. Execution of branch instruction If the branch is not taken due to the execution of the branch instruction, normal instruction fetch and execution are performed. When a branch is taken by executing the branch instruction, the following control is performed. Case where branch destination fetch is performed when branch is successful This means a case where, when a branch is taken in a branch determination cycle, the fetch data from the fetch circuit 200 is the branch destination in that cycle. Data write and pointer operation It is assumed that the fetch data 210, the fetch amount 201, and the fetch position 211 are sent from the fetch circuit 200 as in the case of normal fetch. Although a plurality of methods can be considered for controlling the write enable, the write pointer, and the read pointer, the following three examples will be given here. (First example) A method of controlling the write position from the value of the write pointer at that time as in the normal case as shown in FIG. 2 and setting the value of the write pointer before update to the value of the new read pointer.

This method is a method in which the write position is the same as the normal method, and the read pointer is set to the written position so that the head of the next instruction to be executed is the written position. (Second example) The write address is fixed to 0, and the write address and write enable are set to 0 by the write pointer in FIG.
In this case, the write pointer is updated by the fetch amount and the read pointer is set to 0000.

This method is a method of operating as if the pointer was initialized by the branch taken. (Third example) fetch amount 201 and fetch position 21
A method of updating the write pointer and the read pointer by controlling the write address and the write enable as shown in FIGS. That is, if the fetch position 211 is byte 0,
The read pointer is set to 0, byte 1 is set to 1, byte 4 is set to 2, byte 6 is set to 3. The write pointer is set to a value equal to ((read pointer) + fetch amount / 2). For example, if the fetch position signal 211 is byte 2,
If the fetch amount signal 201 is 4 bytes, the read pointer is set to 1 and the write pointer is set to (1 + 4 /
Set in 2). At the same time, RF600, RF610,
The write address of RF620 and RF630 is set to 1, 0, 0, 0 respectively, and RF600, RF61
The write enable signals of 0, RF620, and RF630 are set to off, on, on, and off, respectively. That is, 4-byte data is set to the 0 position of RF610 and RF620, respectively.
Write at 0 position of.

Fetch amount = 0: 00, 1:01, 2: 1
0, 3:11. This method is a method in which the fetch data is not substantially rearranged. As shown in FIG. 8, since the data fetched from the fetch circuit 200 is written in the RF600, RF610, RF620 and RF630 without changing the order, the write data is written. Align circuit 900
Then, it is not necessary to rearrange the fetch data. Therefore, the fetch operation ends early. This third method is effective in the case where there is no time margin in the fetch operation when the branch is taken. Therefore, the time required to fetch the next instruction is effective in a severe case.

[0078]

Embodiment 2 Embodiment of the case where the width of the instruction buffer has a write width wider than the fetch amount FIG.
A write width indicates a 10-byte instruction buffer by arranging five register files each having a word width of 2 bytes. The capacity of this instruction buffer is 20 words. The RF 600, 610, 620,
(0) shown in 630 and 640,
(1) ,. ． ． ． , (19) are the same as in the case of FIG.
The name given to each word in F, which is just (0), (1) ,. ． ． ． , (19) and then (0), (1) ,. ． ． In this way, it constitutes the ring register. The second embodiment differs from the first embodiment in that RF640 is used. Along with this, it is necessary to change address generation, write enable generation, write align, read align, and the like. In FIG. 9, the same parts as those in FIG. 1 use the same numbers. Next,
Each part of the second embodiment will be briefly described from the description of the first embodiment.

To address 20 words, the pointer has a 5-bit structure. Further, here, as an example, the relationship between the pointer and the address as shown in Table 12 is used.

[0080]

[Table 12]

In the relationship shown in Table 12, the upper 2 bits of the pointer indicate the address in each RF, and the lower 3 bits indicate the RF position. In the second embodiment, the width of the instruction buffer is 10 bytes and the width of the fetch amount is 8 bytes.
Since it is a byte, one RF is not always used among the five RFs. In this respect, the method of generating this address (Table 1
2) is different from the address generation method of the first embodiment (FIGS. 2 and 5). In Table 12, the RF corresponding to the address marked with () is the unused RF. Further, the value in the parentheses is a value that is easy to date code. Example 2
Then, the read address and the write address are generated by this table 12.

The write pointer 700 indicates the head position where writing is performed in the next instruction fetch. +1 (in the case of 2-byte fetch), + according to the fetch amount (indicated by the signal 201) indicated by the fetch circuit 200
A circuit 705 for 2 (4 bytes), +3 (6 bytes), and +4 (8 bytes) is provided.

The write address circuit 801 controls the RF write address and write enable signal according to the value of this pointer. RF600, 610, 620, 6
The write addresses for 30 and 640 are 6 respectively.
01, 611, 621, 631, and 642. Write enable is 102, 112, 12 respectively
2, write pointer 800 and write enable 602
Table 13 shows the relationship between 612, 622, 632, and 642.

[0084]

[Table 13]

The read pointer 800 indicates the head position of the next instruction to be executed. When an instruction is executed by an instruction from an instruction execution control unit (not shown), the instruction length of the instruction (normally this is found from the instruction code of the instruction to be executed, so in this example, a read-align circuit that controls the fetching of the instruction A circuit 805 for +1 (in the case of a 2-byte instruction), +2 (4 bytes), and +3 (6 bytes) is provided according to the signal 601 from 600.

The read address circuit 801 controls the RF read address according to the value of this pointer. RF
Read addresses for 600, 610, 620, and 630 are shown as 603, 613, 623, 633, and 643, respectively. These relationships are the same as those of the write pointer, and the relationships in Table 12 can be used.

The valid flag 1150 is a flag indicating that valid data is held in the instruction buffer, and when this flag is 0, it is assumed that valid data is not held.

The value of the valid flag 1150 is determined by the valid flag update circuit 1155, but the valid flag update circuit 1155 has a fetch amount signal 201 and an execution instruction signal 10.
01, write pointer 700, read pointer 8
00, and a signal 159 for forcibly invalidating the contents of the instruction buffer when the branch of the branch instruction is taken.

The update condition of this flag is described in the first embodiment.
Is the same as. The number of bytes held in the instruction buffer can be obtained as shown in Tables 14 to 17 from the values of the write pointer 700, read pointer 800, and valid flag 1150.

[0090]

[Table 14]

[0091]

[Table 15]

[0092]

[Table 16]

[0093]

[Table 17]

The speed-up register 1100 is a register for latching the head portion (here, 1 byte as in the previous example) of the instruction buffer in order to speed up the instruction reading from the instruction buffer.

In this register, the first 1 byte (described later) of the fetch circuit 200 and the read align circuit 1000 are stored.
Output 620 (1 byte width) is selectively input. The write align circuit 900 is controlled by the fetch amount 201 and the value of the write pointer 700.
Depending on the configuration of 0, the head position address 211 sent from the fetch circuit 200 is also required.

When the fetch head data is always sent from the fetch circuit 200 to byte 0 of the fetch data line 210 as in the case of fetch data 4 (a),
The write align circuit 900 may be controlled as in the write align (A) in Table 18. In this case, only the lower 3 bits of the write pointer are exclusively used for the control.

[0097]

[Table 18]

On the other hand, when the fetch data is sent from the fetch circuit 200 to the fetch data line 210 as shown in FIG. 4B, the write align circuit 900 causes the table (1
It may be controlled like the write align (B) of 1).
The write-align (A) control relationship and the write-align (B) control relationship in Table 19 are different from the write-align (A) control relationship and the write-align (B) control relationship in FIG. 3 of the first embodiment, respectively.

[0099]

[Table 19]

The first byte 1020 to be sent to the speed-up register 1100 is the first byte of the fetch data, and the value of byte 0 is always in the (A) type alignment, and the fetch position in the (B) type alignment. Bytes of each are sent.

The instruction sequences extracted from the RFs 600, 610, 620, 630, and 640 are rearranged by the read-align circuit 1000 and sent to an instruction execution control unit (not shown).

In the read align circuit 1000, the head portion of the instruction to be fetched is 610 and the next portion is 61.
1 and the next part to 612.
Whether the output line 611, the output line 612, or the like is needed depends on the maximum length of the instruction to be fetched. In this example, the minimum unit is 2
Since it is assumed that there is a maximum of 6 bytes for each instruction, 3 sets of 2-byte width outputs 610, 611 and 612 are set.

The rearrangement control in the read align circuit 600 is performed by the value of the read pointer 800. In the configuration having the speed-up register 1100, it is necessary to fetch the part following the instruction fetched for execution and send it to the speed-up register. For this purpose, the read-align circuit 1000 is provided with an output 1020.

Table 20 shows the states of these controls. Table 12 shows the read-alignment control relationship of the second embodiment and Table 13 shows the instruction holding amount in the instruction buffer. However, since these are clear from the description of the first embodiment, the description thereof will be omitted.

[0105]

[Table 20]

[0106]

According to the present invention, since the instruction buffer is composed of a register file or RAM, high integration can be achieved. Further, in the present invention, the portion requiring high speed is F
Since it is composed of F, it is possible to achieve high integration and high speed.

Further, according to the present invention, it is possible to efficiently process a branch instruction even when the instruction buffer is composed of a register file or a RAM.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 shows control of a write address circuit 701.

FIG. 3 shows control of a write align circuit 900.

FIG. 4 shows a distribution state of data on a fetch line 210 according to a fetch amount and a fetch position.

FIG. 5 shows control of a read address circuit 501.

FIG. 6 shows control of the read align circuit 1100.

FIG. 7 shows the correspondence relationship between the difference between the write pointer and the read pointer and the number of bytes in the instruction buffer.

FIG. 8 shows control of a write and a pointer that do not require rearrangement on the write side when a branch is taken.

FIG. 9 is Embodiment 2 of the present invention.

FIG. 10 is a conventional example.

[Explanation of symbols]

200 fetch circuit 600, 610, 620, 630 register file 700 write pointer 701 write address circuit 800 read pointer 801 read address circuit 900 write align circuit 1000 read align circuit 1100 speed-up register 1150 valid flag 1155 valid flag update circuit

Claims (5)

[Claims] 1. A memory for storing a program, and an instruction buffer for fetching and storing an instruction from the memory prior to execution of the instruction, the instruction buffer having a width with a minimum instruction length as a unit. File or R
AMs are arranged side by side so that instructions can be fetched from memory at one time.
An instruction buffer system characterized in that AM is controlled by a write pointer and a read pointer. 2. The instruction buffer system according to claim 1, wherein the instruction buffer has a flip-flop for storing a part or all of an instruction whose execution is started. 3. A pipeline control method for fetching a branch destination instruction sequence in the same cycle as the branch determination or in a cycle before the branch determination, when a branch instruction is executed. 2. The instruction buffer system according to claim 1, wherein the instruction stream on the branch side is invalidated. 4. The fetch amount from the memory is not constant,
Alternatively, when the width of the instruction buffer is larger than the width fetched at one time, the fetch data is rearranged based on the fetch amount and the value of the write pointer, and the data is written to the target register file or RAM. The instruction buffer method described. 5. The instruction buffer system according to claim 1, wherein when fetching an instruction to be executed from a register file or a RAM, the instructions are rearranged according to the value of the read pointer.