JPS60246172A - Picture reader - Google Patents

Abstract

PURPOSE:To obtain a picture where missing of black information and ''white level distortion'' are less and the line density in the main scanning direction is converted at a high speed by retarding an original picture signal for a prescribed time, ORing and ANDing the original picture signal and the retarded signal, selecting the OR output when an output just before the sampling is at low level and selecting the AND output when high level so as to output the result. CONSTITUTION:The delay circuit 2 retards the original picture signal for a prescribed time corresponding to the line density. The OR circuit 3 ORs the original picture signal and the signal retarded by the delay circuit 2 and the AND circuit 4 ANDs the original picture signal and the signal delayed by the delay circuit and output the result. A sampling circuit 5 uses a sampling clock for line density, selects an output of the OR circuit 3 when the output state just before the sampling point is at low level and selects the output of the AND circuit 4 at a high level. Then a picture signal where missing of black information and white level distortion are less and the line density is converted is obtained at the output of the sampling circuit 5.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an image reading device having an image processing circuit that obtains a binary original image signal from an image drawn on a document, etc. The present invention relates to an image reading device having a function of converting into an image signal with a coarse linear density in the scanning direction.

[Conventional technology]

Generally, this type of image reading device uses a fluorescent light or the like to illuminate an image drawn on a document or the like to be read through a reading white that is opened in the main scanning direction.

(reading) The light scattered through the mouth is reflected by a mirror, and the reflected light is guided through a lens to a one-dimensional solid-state image sensor (such as a CCD) in an image processing circuit, which converts it into a binary image. Output a signal.

At this time, the line density in the sub-scanning direction (vertical direction) of the obtained binary image signal (hereinafter referred to as original image signal) is:

It is determined by the speed of the motor that drives the document in the sub-scanning direction, but if a pulse motor (also called a stepping motor) is used for this motor, the speed can be changed by adding the pulse motor to the cell motor or by switching the pulse speed.

It is possible to easily change the line density of the image signal in the sub-scanning direction. On the other hand, the linear density of the original image signal in the main scanning direction (horizontal direction) is arbitrarily determined by the distance from the original through the mirror to the CCD of the image processing circuit (hereinafter referred to as light travel distance), so image processing At the stage of the original image signal output from the circuit.

To change the line density of the original image signal in the main scanning direction.

What is necessary is to change the above-mentioned light travel distance. However, changing the light travel distance requires a complex mechanical mechanism.

Therefore, it has been desired to electrically process the original image signal output from the image processing circuit without changing the light traveling distance to obtain an image signal whose linear density in the main scanning direction has been converted.

[Problem that the invention seeks to solve]

Hitherto, known methods for electrically converting the linear density in the main scanning direction of this type include (1) selectivity, (2) logical method, and (2) arithmetic method (run length domain conversion method). The selection method is to select at a certain ratio when converting from a dense image to a coarse image, and as a result, pixels are thinned out. However, in a binary image, there is usually information in black, so there is a drawback that "black information is missing".Also, the logic method uses the logical sum of the original signal and a signal delayed for a certain time. This is a method of selecting at a certain ratio, and although this can prevent the loss of black information, it has the disadvantage of causing "white collapse".
The arithmetic method is a method that improves the drawbacks of ■ and ■ above, but
It has the disadvantage that it requires a large number of calculations and makes high-speed conversion difficult.

[Means for solving problems]

An image reading device according to the present invention includes: at least one delay means for delaying an original image signal for a predetermined time; an AND circuit for calculating a logical product of the original image signal and the output of each of the delay means; and an OR circuit that calculates a logical sum with the output of the means.

Input the outputs of the AND circuit and the OR circuit.

At the timing of the sampling clock corresponding to the image signal to be converted, when the output state immediately before the timing is low level, the output of the OR circuit is selected, and when the output state immediately before the timing is the NO level, the AND circuit is selected. means for selecting the output of the selection means, so that the output of the selection means is an image signal with less loss of black information and crushed white, and whose linear density in the main scanning direction has been converted to a high speed. It is characterized by being able to obtain

〔Example〕

Embodiments of the present invention will be described below with reference to two drawings.

FIG. 1 is a block diagram showing two embodiments of the present invention, in which the line density in the main scanning direction is 708 lines/xm, 472 lines/xm, and 354 lines/xm. It can be converted into an image signal with a line density of H.

Four types of linear densities can be used in one device. In addition, the ratio of the linear density of 9.45 lines/im, 7.08 lines/im, 472 lines/IIl+, and 354 lines/im is 8:
6:4:3, the width of one pixel is 1/240 each
inch, 1/180 inch, 1/120 inch and 1/90 inch.

Referring to FIG. 1, an image processing circuit 1 outputs a digital original image signal having a line density of 945 lines/1111 lines in the main scanning direction. The delay circuit 2 delays the original image signal by a predetermined time corresponding to the line density. In this example, the linear density is 7.08 lines/square.

If the synchronous clock of 9.45 fins/ii+ is delayed by one cycle, and the density of fins is 472, then the synchronous clock of 945 fins/ii+ is delayed by 1 period.
Delay by the period and further, if the line density is 3.45 lines, 9.4
5/IIjl synchronous clocks are delayed by 1 cycle and 2 cycles. The OR circuit 3 performs the logical sum of the original signal and the signal delayed by the delay circuit 2, and the AND circuit 4 performs the logical sum of the original signal and the signal delayed by the delay circuit 2.

The logical product of the original image signal and the signal delayed by the delay circuit is calculated and output. The sampling circuit 5 performs sampling using the sampling logic for each linear density, selects the output of the OR circuit 3 when the output state immediately before the sampling point is low level, and selects the output state immediately before the ramping point. When is at a high level, the output of the AND circuit 4 is selected and output.

Besides, at the output of the sunfring circuit.

The line density is 7.08 lines/IIm, with less loss of black information and crushed white information, and the synchronization clock.

72 cycles corresponding to 472 books/drunk and 354 books/guan.

Outputs the delay clock delayed by one cycle and one cycle,
The sampling circuit 5 selects one of these delay clocks and outputs it to the delay circuit 2. FIG. 2 shows a circuit diagram showing the block diagram of FIG. 1 in detail. Frequency divider 7 has 1 frequency 2662.4k
Input the Hz clock a, divide it by 2 to get a linear density of 945 lines/dragon clock m, and divide it by 4 to get a linear density of 4.72 lines/dragon clock n.
Output as . Frequency divider 8 is.

Clock b with a frequency of 1000 kHz is divided by 2 to output a linear density of 354 lines/dragon clock 0, and clock b
is also the linear density of 7.08 lines/Click p for Ill.

The clock generation circuit 6 inputs the clock m for a linear density of 9.454'u and outputs a synchronous clock C with a linear density of 9.45 lines/II. Linear density: 4.71/Im and 35
Outputs 4/dragon delay clock t.

Further, the setting circuit 9 outputs a 2-bit linear density conversion command l to the clock selection circuit 5a in the sampling circuit 5, outputs a 1-circuit selection command j to the OR and AND circuits 3 and 4, and converts the original image signal and the conversion signal. A selection command q is output to the sampling circuit 5. A table of selection states for each instruction is shown in FIG.

Referring to FIG. 3(a), it is shown what the clock selection circuit 5a selects in response to the linear density conversion command l. That is, when the linear density conversion command l is "oo'", the delay clock k is selected as the delay clock, the synchronized clock c j F) is outputted as a clock delayed by 1/2 period, and the linear density is 945 lines/clock as the sampling clock.
Outputs the clock m for dragons, and similarly to Rishita, i is "01"
” delay color, ri k and linear density 7.08 lines/I
When the clock p for M is I i 10, the delay clock t is selected and the clock delayed by one cycle from the synchronous clock C and the clock n for linear density 4.72E/11 are
When l is '11', delay clock t and linear density 354
Output clock 0 for book/intoxication, respectively.

Referring to FIG. 3(b), it is shown what the OR and AND circuits 3 and 4 select in response to the 1-circuit selection instruction J. When i is O'', the linear density is 7.08 lines. and 4,72
Select the one for book/dragon, and select the one for Zllll with a linear density of 3.54 lines when u 1 u.

Referring to FIG. 3(c), when the original picture signal and converted signal selection command q is 0'', the line density is 9.45 lines/dragon's original picture signal is selected, and when the line density is u 1 +'', the line density is 9.45 lines. $/u+
The original image signal has a line density of 7.08 lines/j1m, respectively.
Select the image signal converted to 4.722E%u and 3.54 lines/home.

Next, the operation will be explained in detail for each linear density.

A. In the case of linear density 9.45 lines/shape (original picture signal) At this time, the setting circuit 9 sets the linear density conversion command i to "oo", arbitrarily sets the circuit selection command J, and selects the original picture signal and the conversion signal. Set command q to "0".

Synchronization is established, and this synchronized original image signal is inputted to the serial/grallel conversion circuit 5b via the sampling circuit 5 (original) 5c.

The line density selected by the clock selection circuit 5a is 9.45 lines/
It is serialized by the serializing clock m of I11 and output as an 8-bit parallel signal.

B. In the case of linear density 7.08 lines/IIm At this time, the setting circuit 9 sets the linear density conversion command i to "01".
", the circuit selection command j is set to 0", and the selection command q of the original picture signal and the converted signal is set to "P1".Therefore, in the clock selection circuit 5a, the clock selection circuit 5a uses the 1/2 period of the synchronous clock C as a delay clock. A delayed clock is output, and a line density of 708 lines/dragon clock p is output as a sun-silling clock.

Also, since the 2-circuit selection instruction j is 11 Q II,
In the OR and AND circuits 3 and 4, OR/GO) 3a and AND/GO) 4a are selected, and the flip-flop 1 is selected.
The original image signal is output from 0 and the delay circuit 2a converts the original image signal to 1.
A signal obtained by calculating the logical sum and logical product of the signals delayed by /2 periods is output. Furthermore, an instruction for selecting the original image signal and the converted signal q
Since 1''', the sampling circuit 5 selects the orte 5d.

At the timing of the sampling clock p, when the output QA of the serial/normal parallel conversion circuit 5b immediately before the timing is at a low level P O'', the output of the OR circuit 3a is output to the output QA immediately after the timing, and the output of the OR circuit 3a is output to the output QA immediately before the timing /・When the output QA of the Clarel conversion circuit 5b is at a high level 11111, the output of the AND circuit 4a is outputted to the output terminal immediately after the corresponding timing. Therefore, the equivalent circuit at that time is as shown in FIG. 4 (,). An example of a time chart is shown in FIG. 4(b). In FIG. is selected, and when the input terminal DK of the flip-flop 52 has a small output and the output Q of the flip-flop 52 is at a high level, the output of the AND circuit 4 is selected and outputted to the input terminal of the flip-flop 52. The signal input to the input terminal is output to the output terminal Q at the timing of the sampling clock p for 708 images per sequence.In addition, the OR circuit 3 receives the original image signal and this original image signal with a periodic clock in the delay circuit 2a. A signal delayed by 1/2 period of the periodic clock C is inputted to the AND circuit 4, and an original image signal and a signal in which this original image signal is delayed by 1/2 period of the periodic clock C are inputted to the AND circuit 4.

In the case of C1 linear density 472 lines/dragon, in this case, the setting circuit 9 converts linear density conversion command 1 to
``1 circuit selection instruction j is set to ``0'' and original image signal and converted signal selection instruction q is set to ``1.'' Therefore, in the clock selection circuit 5a, ``t as a delay clock, that is, 1 cycle of synchronization clock C. Outputs the delayed black and ri and uses a linear density of 472 lines/dragon clock n as a sampling clock.
Output.

Also, since the two circuit selection command j is "o", in the OR and AND circuits 3 and 4, the OR gate 3a and the AND gate 4a are selected, and the flip-flop 10 is selected.
The original image signal output from the delay circuit 2a and this original image signal are output from the delay circuit 2a.
A signal obtained by performing a logical sum and a logical product with a signal delayed by one period is output. Furthermore, if the selection command q for the original picture signal and the converted signal is "1", the sampling circuit 5 will be set to ``1''.
5d is selected, and at the timing of the sampling clock n, when the output QA of the serial/no-parallel conversion circuit 5b immediately before the timing is low level "0", the OR circuit 3a
The output of the AND circuit 4a is outputted to the output QA immediately after the timing, and when the output QA of the serial/no-cleral conversion circuit 5b is at a high level "1'' immediately before the timing, the output of the AND circuit 4a is outputted to the output QAK immediately after the timing.

Therefore, the equivalent circuit at that time is expressed as shown in FIG. 5(,), and FIG. 5(b) shows an example of a time chart. In FIG. 5(a), the delay circuit 2a outputs a signal obtained by delaying the original image signal by one period of the synchronization clock C, and the clock terminal cp of the 7RinonoFlotso 52a receives the following signal:
The configuration is the same as that shown in FIG. 4(,) except that the linear density of 472 lines/dragon sampling clock n is input.

In the following case, when the linear density is 354 lines per unit, the setting circuit 9 executes the linear density conversion command "1".
1'', the circuit selection command J is set to 1'', and the original image signal and conversion signal selection command q is set to "1". Therefore, the clock selection circuit 5a outputs t as a delayed clock, that is, a clock delayed by one period from the synchronization clock 9, and outputs a clock 0 for 1 rtan with a linear density of 3.54 lines as a sampling clock.

Also, since the 1-circuit selection command j is ゛1''', in the OR and AND circuits 3.4, 3a).

3b and andoo) 4g and 4b are selected, respectively.
The original image signal output from the flip-flop 10, the signal obtained by delaying this original image signal by one period in the delay circuit 2a, and this 1
The delay circuit 2b outputs a signal obtained by ORing and ANDing the three signals, the signal delayed by one period, the signal delayed by one period, that is, the signal by which the original image signal is delayed by two periods.Furthermore, the original image signal Since the conversion signal selection command q is 1'', the sampling circuit 5 selects 5d.

At the timing of sampling clock 0, when the output Q of the serial/no-clarel conversion circuit 5b immediately before the timing is low level "0", the output of the OR circuit 3b is output to the output QA immediately after the timing, When the output QA of the 1,000-channel conversion circuit 5b is at a high level P1'', the output of the AND circuit 4b is outputted to the output QA immediately after the timing.

Therefore, the equivalent circuit at that time is expressed as shown in FIG. 6(fa), and FIG. 6(b) shows an example of a time chart. In FIG. 6(,), the delay circuit 2a,
2b output signals obtained by delaying the original image signal by one period and two periods of the synchronization clock 4, respectively.

The OR circuit 3 calculates the logical sum of the original image signal and the three signals output from the delay circuits 2a and 2b, and the AND circuit 4 calculates the logical product of the original image signal and the three signals output from the delay circuits 2a and 2b. The configuration is the same as that shown in Fig. 4 (a) and Fig. 5 (to)), except that the clock terminal of the flip-flop 52 is input with a linear density of 3.54 lines/suncilling clock of 0. be.

In the above embodiment, when converting an original image signal with a linear density of 945 lines/wn to an image signal with a linear density of 7.08 lines/mm, 4.72 lines/1ran, and 354 lines/wn, the delay circuit at that time is The maximum delay amount in 2 is respectively.

Line density: 945 lines/1/2 period of the cabinet's synchronous clock C.

One period and two periods were used. However, this maximum delay amount is
This value is not determined to be optimal, but is determined experimentally. therefore.

The maximum delay amount should not be limited to the value of 9 in this embodiment. For example, when the line density is 708 lines/III+, the maximum delay amount is 1/3 to 172 cycles of the synchronous clock C.

When the line density is 4.72 lines/layer, the maximum delay amount is the time of the front mounting including one period of the synchronous clock C, and the line density of 35
In the case of 4 lines/Twn, the maximum delay amount may be selected from a certain range, such as 5/3 to 2 cycles of the synchronous clock C.

〔Effect of the invention〕

As is clear from the above description, according to the present invention.

The original image signal is delayed for a predetermined time, the original image signal and the delayed signal are ORed and ANDed, and sampled with the sampling clock to be converted, and when the output immediately before sampling is low level, the output of the OR is selected. , When the line density in the main scanning direction is made coarser by selecting and outputting the AND output when the level is high, "missing black information"
This has the advantage of being able to convert and obtain an image signal with less ``whitewashing'' at high speed.

[Brief explanation of the drawing]

Fig. 1 is a professional diagram schematically showing an embodiment of the present invention, Fig. 2 is an example of the block diagram of Fig. 1, and (a) is the original image signal (line density 9.45 lines/frame). The linear density is 7.08 lines/11
Figure 4(b) shows an example of the time chart of the equivalent circuit in Figure 2 when converting to an image signal of tIn, and Figure 5(a) shows the original image signal (° linear density 9° 45 lines). /lll1
Figure 5(b) is an example of the time chart of the equivalent circuit shown in Figure 2 when converting 1I) into an image signal with a line density of 4.72 lines/kaku, and Figure 6(,) is the equivalent circuit in Figure 2 when converting the original image signal (line density 9.45 lines/shape) to an image signal with a line density of 354 lines/., and Figure 6 (b) is an example of the time chart. FIG. 1... Image processing circuit, 2... Delay circuit, 3...
・OR circuit, 4...AND circuit, 5...sampling circuit. 6...Clock generation circuit. Figure 3 (a,) (b) (C)

Claims (1)

[Scope of Claims] 1. In an image reading device having an image processing circuit that obtains a binary original image signal from an image drawn on a document or the like, at least one delay means for delaying the original image signal for a predetermined period of time; , an AND circuit for calculating the logical product of the original image signal and the output of each of the delay means, an OR circuit for calculating the logical sum of the original image signal and the output of each of the delay means, the AND circuit and the OR circuit. Input the output of , and at the timing of the sampling cloth corresponding to the image signal to be converted. means for selecting the output of the OR circuit when the output state immediately before the timing is low level, and selecting the output of the AND circuit when the output state immediately before the timing is high level; The image reading device is characterized in that the image signal to be converted is obtained which has a rougher line density in the main scanning direction than the original image signal.