JPS62221270A - Image processor capable of enlargement/reduction - Google Patents

Abstract

PURPOSE:To prevent the marginal part of an original from being enlarged and to eliminate that a picture is recorded from the edge of a recording paper by modifying the start address of the writing of a picture data into an output buffer circuit corresponding to an enlargement/reduction processing. CONSTITUTION:An analog picture signal read by a picture reading means 60 such as CCD, is converted to a 16-gradation level picture data by an A/D converter 61. This picture data is shade corrected by a shading correction circuit 62, supplied to a picture processing circuit 2, and subjected to a real time enlargement/reduction processing with a specified magnification. Thus processed picture data is binary-coded by a binarization circuit 23 based on a threshold data stored in a threshold table 69, and supplied to an output buffer circuit 90. The circuit 90 is a circuit to control the timing of the read and the write of the picture data, and the timing is modified corresponding to the enlargement/ reduction processing.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides image processing that can be enlarged and reduced in size by using data interpolation to reduce the size of an original image when it is enlarged! Aa
Regarding.

[Background of the Invention] When a photoelectric conversion element such as a CCD is used as a single image reading means in an image recording device that can enlarge or reduce an original image, the pixel data of the original image read by the photoelectric conversion element is hand.

Generally, an enlarged/reduced image signal is obtained by increasing or thinning out appropriate image data according to the enlargement/reduction magnification.

Figure 25 shows the magnification and
FIG. 2 is a block diagram of main parts showing an example of a processing system for executing reduction.

In the figure, 4o is a memory for image data, and the input terminal 41 thereof is supplied with image data read by an image reading means after being subjected to enlargement/reduction processing. Output available at output terminal 42.

The image data is supplied to a recording device or the like and an enlarged/reduced image is reproduced.

When enlarging/reducing, the amount of image data stored in the memory 40 is limited by the recording width of the recording device, but in this case, the generation timing of the address generator 47 for the memory 40 is controlled according to the enlargement/reduction. be done.

Therefore, the first and second counters 4 can be preset.
3.44 are provided, and respective preset values PI, P2
Clock CLK2 of a predetermined frequency (Fig. 26C
), the first and second output pulses CI,
C2 is generated (FIGS. 26D and E), the 7 lip-flop 45 is set by the first output pulse cl and reset by the second output pulse C2, so that the window pulse wP shown in FIG. 26F is generated. It is formed. This window pulse WP is supplied to the gate circuit 46 as a gate pulse, and the clock CLK2 is supplied to the address generator 47 by the width W1 of the window pulse WP. However, this clock CLK2 is a clock synchronized with the enlarged/reduced image data.

As a result, since the address data for the memory 4o is generated for the period Wl, the horizontal effective area signal (
Image data regulated by H-VALID (B in the same figure)
), the image data corresponding to one period w1 is stored in the memory 40.
(G in the same figure).

Therefore, if the preset values PI and P2 are changed according to the magnification of enlargement/reduction, the width Wl of the window pulse WP changes in accordance with this change.

This limits the amount of image data written to memory 40.

In the case of reduction, the window pulse wP and the horizontal valid area signal (H-VALID) are processed with the same width. On the other hand, in the case of enlargement, the number of image data increases, so
Taking this into consideration in advance, the horizontal effective area signal (H-VALI) is
The width of the window pulse WP is made narrower than the width of D) to reduce the number of data.

[Problems to be Solved by the Invention] By the way, the above-mentioned conventional image processing apparatus causes the following problems.

That is, in the configuration shown in FIG. 25, although the amount of image data to be written to the memory 4o is limited depending on the magnification/reduction ratio, the write address is always the first address (O address) will be specified.

In particular, when applied to an image processing device where the reading device or the recording device reads or records a document based on the center of the document or recording paper, depending on the magnification, the image to be recorded may appear on the recording paper. The image may end up outside the transcription area.

For example, as shown in FIG. 27, when W is the maximum reading width of the image reading means, the image data of the original 52 is read based on the center line of the document mounting table 51, and the image data of the original 52 is read using this center line as a reference. When an image is recorded at the same magnification, it is recorded as shown in FIG. 28B, but when it is reduced, it is recorded as shown in FIG. 28A.

This is because the first write address in the memory 40, that is, the O address, corresponds to the write start position of the output device (recording device such as a laser printer).

Therefore, when the size of the recording paper 53 to be recorded is small, it is possible that it will be outside the transfer area of the recording paper.
In that case, the reduced image cannot be correctly recorded on the recording paper.

Even when the size of the recording paper 53 is large, there is a drawback that the reduced image is recorded on the edge of the recording paper 53.

Furthermore, during the enlargement process, the margin portion of the original document is also enlarged, resulting in an enlargement as shown in FIG. 28C. Therefore, there is a possibility that the required range of images cannot be recorded on the predetermined recording paper 53.

Therefore, this invention solves the above-mentioned conventional problems.
The present invention proposes an image processing device with enlargement/reduction functions that prevents the occurrence of missing images to be recorded.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention uses enlargement and
An output buffer circuit for storing image data is provided after the image processing circuit where the reduction process is performed, and the start address for filling the image data into the line memory provided in this output buffer circuit is determined during the enlargement/reduction process. This feature is characterized in that it can be changed accordingly.

[Function] Instead of writing image data from the first address in the line memory, if the writing start address is automatically changed according to the enlargement/reduction ratio, recording paper size, etc., when the image is reduced, the recording paper In particular, if the type of paper is such that the image is not recorded from the edge of the paper, and the image is recorded based on the center, the reduced image can be recorded correctly regardless of the size of the recording paper.

When enlarging, since the front and back of the enlarged image data are not used as image data for recording, even the margins are not enlarged, so that the necessary image area can be recorded correctly.

[Example] Hereinafter, reference will be made to Figure 1 and subsequent figures for a case where an example of an image processing device capable of scaling up and down, related to this Ijl, is applied to a type of processing based on the center line view. This will be explained in detail.

FIG. 1 shows a schematic configuration of an image processing apparatus according to the present invention.

The image information of the original 52 is obtained by an image reading means 6 such as a CCD.
It is read as 0 and converted into an analog image signal. Second
The figure shows the relationship between the image signal and various timing signals, and shows the water motion effective area signal (H-VALID) (B in the same figure) 41C.
Corresponding to the maximum original reading @W of the CD 60, the image signal shown in F in the figure is read out in synchronization with the synchronous clock CLK (E in the figure).

In FIG. 1, an image signal is converted by an A/D converter 61 into image data having 1, for example, 16 gradation levels (0-F), and 0 image data is subjected to shading correction in a shading correction circuit 62. This is to correct shading caused by uneven sensitivity of the CCD 60, non-uniformity of the optical system, uneven illuminance of the irradiation lamp, etc. Therefore, read the manuscript information before reading it! A uniform density plate (
information (1947 minutes) of a white board, etc.) is read by the CCD 60, and this data is stored in the memory 63 as non-uniform data. This nonuniform data for shading correction is supplied to the correction circuit 62 together with the original image data, and shading correction is performed for each pixel.

The shading-corrected image data is sent to the image processing circuit 2.
Data indicating a zero magnification is supplied from the main control circuit 70, and the enlargement/reduction processing is performed in real time at the specified magnification.

The image data subjected to image processing is sent to the binarization circuit 23,
The image data after the binarization process is supplied to the output buffer circuit 90. The circuit 90 is provided to control the writing or reading timing of image data, and is controlled based on the writing and reading start address data sent from the main control circuit 70.

The image data obtained from the output buffer circuit 90 is ultimately supplied to the image data memory 64 to store the image data, or directly supplied to the output device 65 to output the desired image information. recorded. As the output device 65, a recording device using a laser printer, an LED printer, or the like can be used.

Note that 71 is an operation key for externally setting the magnification, and 66 is a reference claw 2 generation circuit. The reference clock output from the reference clock generation circuit 66 is supplied to a timing control circuit 67 to form various timing signals necessary for image processing. That is, C.C.D.
In addition to driving timing signals (transfer lock, etc.),
A timing signal 1 for driving the address ant circuit 68 for the memory 63, a timing signal for the image processing circuit 2, a timing signal for the threshold table 69 for z-value conversion, etc. are generated.

FIG. 3 is a block diagram showing an example of the image processing circuit 2. As shown in FIG.

In this example, 1.5% between 0.5x and 2.0x
This is a case where it is possible to enlarge or reduce the image in increments (as an approximation of 1784).

Here, also in this invention, in principle, the enlargement process increases the image data, and the reduction process is an interpolation process that thins out the image data. The enlargement and reduction in the main scanning direction shown in FIG. I am trying to do this by changing the movement speed of.

Slowing down the movement speed in the sub-scanning direction enlarges the original image,
If you speed it up, it will shrink.

In FIG. 3, a timing signal generation circuit 1O is used to obtain timing signals etc. for controlling the processing timing of the entire image processing circuit 2, and includes a CCD 60.
Similarly, the synchronization clock (CLK), horizontal valid area signal (H-VAL III), vertical valid area signal (V
-VALID) and a horizontal synchronization signal (H-5YNC).

In addition to the above-mentioned timing signals, the timing signal generation circuit 1O also outputs a clock CKL2 having twice the frequency of the synchronization clock CLK in order to process in real time a magnification of up to 2x.

A series of image data having 16 gradation levels sent out from the CCD 60 is sent to two latch circuits 11 .
12, and image data DI and Do of two adjacent pixels among the 4-bit image data are latched at the timing of the synchronous clock. These latch data are used as address data for the memory 13 for interpolation data.

The interpolation memory 13 is a data table in which new image data (hereinafter this image data will be referred to as interpolation data) referenced from two adjacent image data is stored.
ROM etc. are used.

As the address data of the interpolation memory 13.

In addition to the pair of latch data D0.01 described above, a data selection signal SD is used.

The data selection signal SD is a pair of latch data DO, D
It is used as address data for determining which data from among the data table group selected by I is to be used as interpolation data.

The data selection signal SD is determined by the set magnification for enlargement or reduction, as will be described later.

Figure 4 shows latch data DO, DI and data selection signal S.
An example of interpolation data S selected by D is shown.

In Fig. 4, S is interpolated data (4 bits) output with 16 gradation levels, and since the image data 00.01 used as latch data each has 16 gradation levels, the interpolated data S is is 16X16=
It contains 256 data blocks.

The figure shows the theoretical value (5 decimal places) at each step when Do = O, DI = F, and the value of the interpolated data S actually stored in the case of positive slope and negative slope, respectively. Show about.

Actually, interpolated data S is stored in the form shown in FIG. However, this data is DO=O, DI=0
This is an example of the case of ~F.

In FIG. 5, ADR5 is a base address, and when DO=4, DIII (data selection signal SD when taking levels from O to F (data from 0 to F arranged horizontally)) and.

The actual address for the interpolation memory 13 is obtained by adding the address data Am)R3, which indicates the relationship with the interpolation data S to be outputted, and the value of the data selection signal SD on the horizontal axis.

The interpolated data S output from the interpolation memory 13 is latched by the latch circuit 14.

One part, 1B, is an interpolation data selection memory in which a data selection signal SD is stored. A data table is also used here, and data used as an address for selecting interpolation data (hereinafter referred to as data selection signal SD) is stored.

FIG. 6 shows a part of the data selection signal SD used when enlarging one image. The example data is when the magnification rate M is 124/84, and the magnification can be set at intervals of 1784. A middle mark indicates invalid data.

In this way, if the magnification can be set at intervals of 1184, the repetition period will be 64, as shown in Figure 6.
becomes. Also, when the expansion rate is 124/84, the sampling interval is 84/124 (= 0.51613
), the sampling position (theoretical value) with respect to the repetition period and the data selection signal S referred to at that time.
The relationship with D is as shown in the figure.

In the data selection signal SD at the repetition period "0",
The former data (0) has a sampling position of (0,00
000), and the latter data (8) has a sampling position of (0,51813).
This is the data selection signal SD at the time. These pairs of data selection signals SD differ depending on the value of the repetition period.

Note that when the repetition period is 15.32 and 48, the value of the latter data selection signal SD does not exist, which indicates that only one piece of data exists in that period.

These data are actually stored in the complementary +111 data selection memory 16 in a state as shown in FIG. 7th
In the figure, the data selection signal S is referenced by the base address ADR3 (vertical axis) and the number of steps (It axis).
The data on the right side of D indicates data for write clock control (referred to as processing timing signal TD), as will be described later.

When the processing timing signal TD is "1", it becomes a 1M write enabled state (write enable), and when it is "0", it becomes a write inhibited state. Therefore, data "OO" in the figure indicates invalid data.

Figure 8 shows the interpolation data selection signal SD used during image reduction.
The example data showing a part of the data table is when the reduction rate M is 3ale4.

A single mark in the figure indicates thinned-out data, and this data selection signal is also stored in the memory in a state as shown in figure ttS9.

Now, in the interpolation data selection memory 16 mentioned above, the operation keys 71 are connected to the upper 7 bits of address terminals A7 to A13.
The magnification signal set by is supplied as address data. This magnification signal is transmitted to the main control circuit 7 as described above.
Q is also supplied.

Further, the counter output of the counter circuit 15 is supplied as address data to the lower 7 bits of address terminals AO to A8. Therefore, the counter circuit 15 is supplied with the synchronous clock CLK2.

An interpolation data selection signal S is sent from the complementary data selection memory 16.
In addition to D, a processing timing signal TD is output.

As described above, the processing timing signal TD is selected to be "1" when interpolation data exists, and to be "0" when there is no interpolation data or when data is to be thinned out.

The data selection signal SD and the processing timing signal TD are latched by the latch circuit 17. The latch timing is regulated by the synchronization clock CLK2.

The processing timing signal TD controls the timing of the interpolated data S to be latched in the latch circuit 14. Therefore, the processing timing signal TD is temporarily
Supplied by 1,000 circuits 18.

It is delayed by the access time of interpolation memory 13.

The processing timing signal TD delayed by a predetermined time (one period of the synchronous clock CLK2) is supplied to the gate circuit 19 as its gate signal.

The gate circuit 19 is supplied with the synchronizing clock CLK2, and is closed when the processing timing signal TD is "L".
It is controlled to be open when it is "0", and a clock is output only when it is "1".

The synchronizing clock CLK2 output from the gate circuit 19 is used as a latch pulse for the latch circuit 14, and latches only valid data among the interpolated data S output from the interpolation memory 13.

The synchronous clock CLK2 is also used as a write clock for the output buffer circuit 90 at the subsequent stage.

What has been described above is the main configuration of the image processing circuit 2. After the output data obtained from the image processing circuit 2 is once binarized, it is processed by the output buffer circuit 90 (details will be described later).
The image data is supplied to an output device 65 or an image memory 64 via.

An example of a circuit configuration for binarization processing will be explained with reference to FIG. 3 again.

In the figure, the threshold table 69 includes a main scanning counter 20 that counts write clocks, a sub-scanning counter 21 that counts horizontal synchronization signals, and these counters 20.
．． The dither matrix 22 outputs a dither threshold value based on the count value of 21.

Then, in the binarization circuit 23, the image data output from the latch circuit 14 is compared with the dither threshold value from the dither matrix 22, and converted into 2fIa for each pixel.

Next, the image processing operation of the image processing apparatus 2 described above will be described in detail, starting with the enlargement processing operation, with reference to FIG. 10 and subsequent figures. [For JI's convenience, the magnification rate M is 124/84
(=1.94) times.

The tJSto diagram is an analog representation of the relationship between original data and interpolated data.

D indicates original data, and S indicates output data after interpolation.

The relationship between the image information level and the interpolated data at this time is as shown in FIG. Further, the relationship between the sampling pitch and the data selection signal SD during interpolation at this time is as shown in FIG.

A timing chart of signals in each section during this interpolation process is shown in FIG.

Therefore, the original image data obtained from the CCD 60 is now D0(0), DI(F), D2(F), D
3(0), D4(0) (the gradation level of each image data is shown in parentheses), DI(F) is output from the latch circuit 11 and D is output from the latch circuit 12 in synchronization with the synchronous clock.
o(0) is output.

In part, the data table shown in FIG. 7 is referred to based on the borrow rate signal set externally and the output of the counter circuit 15, and the data selection signal SD is 0.8; 0, 8.1,
9.1,9. ... (Fig. 11E) is output, and the processing timing signal TD is 1, 1, 1 . ...(F in the same figure) is output.

The interpolation memory 13 refers to the interpolation data table using the image data DO1DI and the data selection signal SD, and outputs necessary interpolation data S (G in the figure).

That is, since the data selection signal SD is 0 and 8 between one image data D 0 (0) and DI (F), 0 and 8 are output as the interpolation data SO and St.

Between image data D1(F) and D2(F), since data selection signal SD is O and 8, interpolated data S
2 and S3, F and F are output.

Since the data selection signal SD is 1 and 9 between image data D2(F) and 03(0), interpolated data S4
And E and 7 are output as S5.

Since the 1 selection means SD is 1 and 9 between the image data D3(0) and D4(0), 0 and O are output as the interpolation data S8 and S7.

After that, the image data D5. Regarding DB, . . . , the interpolation data S is read in the same manner as described above.

Therefore, if the data after interpolation is represented by an X mark, it can be seen that image data having a predetermined level between the original image data is interpolated and output as shown in FIG. 1O.

In this way, the interpolated data SO to S7 are sequentially read out using the interpolation method for the actual image data DO to D4,
These interpolated data S are sequentially sent to the latch circuit 14 (■ in the figure).

On the other hand, the processing timing signal TD output from the latch circuit 17 is delayed by the latch circuit 18 by a time t (see FIG. 11), but this delay time t is, as described above, This is the time required for access, and the time required for the latch circuit 14 to read the interpolated data S.

Since the on/off of the gate circuit 19 is controlled by the processing timing signal TD from the latch circuit 18, the latch circuit 14 performs a latching operation only when the gate circuit 19 is on, and does not perform a latching operation at other times. Not possible.

Next, the reduction process will be explained.

FIG. 12 is an analog diagram of an image signal in the case of reduction processing, and is image data Do.

DI, D2, D3, . . . are marked O, and interpolated data So, 31. . . . is represented by an x mark. Fig. 13 shows a timing chart of the signals at that time, and Fig. 154 shows the relationship between the original image data D and the interpolated data S used at that time.
The relationship of D is as shown in FIG.

Note that the reduction rate M illustrated here is 33/64 (-0,5
2), and the gradation level of the image data is the same as in the case of the enlargement process described above.

Two adjacent image data (
For example, one image data DI, Do) is supplied to the interpolation memory 13 as an address signal, an externally set reduction magnification (33/84) is supplied to the interpolation data selection memory 16, and a synchronization clock CLK2 is supplied to the counter circuit. 15
The counting is the same as in the case of the enlargement process described above.

As is clear from FIGS. 8 and 9, selection memory 1
From 6 onwards, it is used as the data selection signal SD.

O9 trees; 19 trees; 1 tree, E, O;... are output, and the processing timing signal TD is 1,0°1.
0,0,0,1. ... is output. However, since the tree is invalid data, O data is stored in the interpolation data selection memory 16.

Therefore, interpolated data S as shown in FIG. 13 is read out from the interpolated data memory 13.

That is, since the data selection signal SD is O and a tree between the image data D 0 (0) and Di (F), only 0 is output as the interpolation data 5 (=SO).

Between image data DI(F) and 02(F), since the data selection signal SD is equal to F, interpolation data Sl
As, F is outputted as 0 image data D 2 (F) and D
Between 3(0) and D9M selection %SD are both books, so no interpolation data S is output.0 Image data D Between 3(0) and D4(0), 1 selection. Since the data SD is E and the book, only 0 is output as the interpolation data S2.

Subsequent image data D4. D5. . . . The interpolation data S is read out in the same manner as described above.

In this way, the actual image data DO, DI.

. . . The interpolated data So, Sl, . . . are sequentially read out and the interpolated data S is sequentially transferred to the latch circuit 14. Ru.

On the other hand, the processing timing signal TD is 0.1,0°0.0.
1... (F in the same figure), the gate circuit 19
Since the write clock output from so is as shown in FIG.
, st, . . . are output (I in the same figure).

As mentioned above, when reducing the size, new image data is given between the original pixels of the original image information and that image data is output, and some of the image data of the original pixels is thinned out or left as is. These output image data are generally referred to as interpolation data.

In the embodiment described above, if the magnification of enlargement or reduction is changed, the data selection signal SD output from the selection memory 16 for interpolation data changes, and the memory 13 for interpolation data is addressed accordingly to perform the corresponding interpolation. It will be clear that data S is output.

Now, the image data that has been subjected to the enlargement/reduction processing and has been binarized is supplied to the output buffer circuit 90. Data write timing and write address for the line memory provided at 90 are controlled. The reason why the write timing and write address are controlled according to the magnification will be explained with reference to FIGS. 14 and 15.

For example, if the maximum image reading size of the CCD 60 is 84 format and its resolution is 18 dots/cm,
The memory capacity for 1247 minutes is 4096 bits. Therefore, the 14th line memory for storing one image data is
A line memory with a capacity of 4096 bits as shown in the figure is prepared.

Then, image data is written based on the intermediate address (2048th address).

That is, the image data of the first half of the image data is written to the address before the intermediate address, and the image data of the latter half of the image data is written to the address after the intermediate address.

The line memory is cleared immediately before writing.

Therefore, when reducing an image, for example, when reducing an image to 1/2, the write start address of the line memory will be set to the address corresponding to 174 of the memory capacity (1024fIi-th address). In this case, the reduced image data is written into the line memory in the state shown in FIG. 14A.

On the other hand, the read start address is set to 0 address as in the normal case. Therefore, Figure 15A
A reduced image is recorded as shown in .

This is because one image data is "O" from the 0 address to the 1023 address, so that period is considered white and recorded on the recording paper, and recording based on the reduced image data starts from the 10247 address. This is because it becomes

In this way, if image data is written centering on the middle address and the 0 address is used as a reference when reading, the image will be recorded at the center 1iAlt7A of the recording paper 53.

For this reason, the write start address when reducing is
The settings are as follows.

Writing start address=(4ose-4osex reduction magnification)/2 Image data is written centering on the intermediate address even when the image is enlarged.

If the maximum magnification is 2x, the image data at that time will be twice the image data at the same magnification. In that case, the area of the recorded image will be four times as large.

For example, even if an attempt is made to double the size of an 84-size original, if the maximum size of recording paper is up to 84-size, the entire enlarged image cannot be recorded on the recording paper.

Taking this into account, it is possible to obtain a more natural enlarged image by limiting the image data to be written in advance, taking into account the maximum size of the recording paper.

Therefore, when enlarging an image, as shown in FIG. 14B, both the write start address and the read start address start from address 0 as in the normal case, but the data amount is 1/2 of the enlarged image data. Up to 2048 bits before and after the data (corresponding to the position of the center edge of the enlarged image) are stored in the line memory. In other words, only the maximum number of bits (4096 bits) in the line memory will be written.

Therefore, when the enlargement ratio is 12B/84, the data from the first data to the 2047th bit of the enlarged image data is ignored, and writing to the line memory starts from the 2048th bit data, and from this point on, a total of 409
Data up to the 6th bit will be written.

Similarly, when the magnification rate is +27/84, writing of image data starts from the 2016th bit, and data corresponding to the total 4096th bit is written from there, and when the magnification rate is 12B/84, the writing of image data starts from the 2016th bit. Writing of image data starts from the bit, and from this point on, a total of 40
Data up to the 96th bit will be written.

It goes without saying that even if other enlargement ratios are set, the image data to start writing according to the enlargement ratio will be selected, so detailed explanation thereof will be omitted.

Note that when data is written to the line memory from the middle of the enlarged image data in this way, the image data corresponding to the center part of the original image is written, so unnecessary parts may be enlarged. The probability of occurrence of image loss due to this is greatly reduced.

In summary, the write start address during enlargement/reduction is set as shown in FIG. 16.

FIG. 17 and subsequent figures are circuit diagrams showing an example for realizing the above-described operation.

FIG. 17 shows an example of the output buffer circuit 90. The output buffer circuit 90 includes a pair of line memories too, 101.
are provided, and one line of image data is supplied to each. The reason for providing the pair of line memories ioo and tot is to alternately supply image data for one line so that writing and reading of image data can be processed in real time. Line memories 100 and 101 have a capacity of 4096 bits as described above.

Writing and reading to and from the line memories 100 and 101 are all performed as follows. - First, when writing data to the line memory, a write clock obtained via the clock control circuit 120 (clock generated in the image processing circuit 2) is used, and when reading data, a read clock for the output device 65 is used. Therefore, these clocks are sent to each address counter 104 via the first and second switches 102 and 103 for clock selection.
, 105.

The first and second switches 102 and 103 are controlled in a complementary manner so that when one line memory is in the write mode, the other line memory is in the read mode. The switch control for this is the control circuit 10.
Horizontal period control signal output from 7 (18th
Figure C) is used.

The address counters 104 and 105 are further supplied with address data for determining the write start address and read address for the line memories Zoo and lot through third and fourth switches 108 and 109, respectively. Also the third and fourth switches 108, 109. When one address counter is in the write mode, the other address counter is in the read mode, and these switches 108 and 109 are also controlled in a complementary manner as shown in FIG. 18C. A horizontally periodic control signal is supplied.

The write start address is preset in address counters 104 and 105 in synchronization with the horizontal synchronization signal (FIG. 18A).

Outputs from the line memories 100 and 101 are selected by the fifth switch 110 and then supplied to the output device 65 described above. Since the fifth switch 110 is for selecting image data from the line memory in the read mode, a signal having the opposite phase to the control signal shown in FIG. 18C is used.

FIG. 19 shows an example of the clock control circuit 120, in which the write clock to the clock input terminals of the address counters 104 and 105c7) is controlled by the sixth switch 121, and the write clock is controlled by the counter 122.
is supplied to

The counter 122 is used during enlargement processing, and an enable pulse PE (an inverted version of the horizontal effective area signal (H-VALID) shown in No. 1811B) is supplied to a terminal E, and preset data PO is supplied to a terminal PR. Supplied.

The counter 122 starts from the rising edge of the enable pulse PE.
A carry signal is obtained from the counter 122 when the counter 122 counts up to the preset data PO.

The preset data PO is address data corresponding to the enlargement ratio as shown in FIG. 16, and is generated by a main control circuit 70 which will be described later.

The flip-flop 123 is set by the carry signal, and is supplied to the sixth switch 121 as its gate signal via the OR game 124. It is assumed that when the gate signal is "1", the sixth switch 121 is controlled to be closed.

or game) 124 is a mode signal PS indicating reduction/enlargement
is supplied.

Therefore, at the time of expansion, the carry signal causes the sixth switch 121 to be closed, and the write clock is supplied to the switches 102 and 103. As a result, the line memory 100 has a write clock of 2048 pitro CM.
The write mode starts from 2.0 (=2.0), and the write start address is 0 address. This allows the first
As a result of the image data being written at the timing shown in Figure 8 and F, the enlarged image is recorded with the central line reference as shown in Figure 15B.

The write start address (data) is generated by the main control circuit 70 shown in FIG.

In FIG. 20, 75 is a CPU, 76 is a ROM in which a control program is stored, and 77 is a ROM in which write address data shown in FIG. 16 is stored.

Since the magnification set with the operation key 71 is supplied to the CPU 75 via the I10 port 78, the write start address corresponding to that magnification is sent to the third or fourth switch 108, 109 mentioned above via the I10 port 79. will be supplied.

Incidentally, in the above description, the invention is applied to an image processing apparatus that reads an image based on the center of the document and records the image based on the center of the recording paper, but the present invention can also be applied to other image processing apparatuses. can do.

First, when both image reading and image recording are processed with one side of the document (recording paper) as a nof standard, the image reading start position of the CCD 60 and the recording start position m
(For laser printers.

Since the recording beam start position 21) of the laser beam is the same, the present invention can be applied without any problems.

Second, in an image processing apparatus of the type in which image reading is performed based on the center line of the document and image recording is processed based on one side of the recording paper, input/output to and from the output buffer circuit 90 and the start address are becomes as follows.

In this case, the write start address to the line memories too and lol is always the O address. On the other hand, the readout start address cannot be determined only by the magnification signal and differs depending on the size of the document.

So this kind of image processing? In position c.

A reading start address is determined from a signal indicating the document size and the magnification.

As shown in FIG. 21, the case where the size of the document 52 to be read is A4 size will be described below.

As mentioned above, when it is 18 dots/m, A
The number of bits for the width of 4 size is 210mm x 18dotg/sm = 338
Since it is a 0 pit, if the maximum read original size is 34 size, the value obtained by multiplying the width Y in FIG. 21 by the magnification becomes the read start address for the line memory.

Therefore, the read start address at the same magnification is (4(19
6-3360) / 2 = 388 bits.

The value of the write and start address at any magnification is
As shown in Figure 2, the original size is A4.

Thirdly, in an image processing apparatus of the type in which image reading is performed based on one side as shown in FIG. 23 and image recording is processed based on the center line of the recording paper, the output buffer circuit 90 The writing and start address to is determined as follows.

In this case, the maximum number of bits for A4 size (3360 bits) and the maximum number of bits for 34 size (4096
The write start address is determined from the bit). That is, write start address=(409B-3380X magnification)/2. At this time, the read start address is 0 address.

When the write start address becomes negative (at the time of expansion), that value becomes the value of the read start address. Therefore, the write start address at this time is 0 address.

FIG. 24 shows the values of write and read start addresses at arbitrary magnifications.

In this way, the writing or reading start address can be changed depending on the reading or writing reference position of the document. Further, the writing start address to the line memories too and ioi may be changed depending on the paper size of the recording paper.

In addition, in the above-mentioned embodiment, the enlargement/reduction ratio is set to 128/8.
Under the condition that it is possible to select from 4 to 33/84 in l/64 increments, the timing generation circuit lO
The synchronization clock CLK2 obtained by is set to have twice the frequency of the reference synchronization clock, but this frequency is determined by the maximum expansion rate.

For example, when the maximum enlargement rate is selected to be three times, the frequency of the synchronization clock CLK2 is set to three times the frequency of the reference synchronization clock. Therefore, the frequency of the synchronization clock CLK2 is changed depending on the maximum enlargement ratio used.

The memories 13 and 16 may use RAM instead of ROM, and the memory 13 may use an arithmetic circuit instead.

[Effects of the Invention] As explained above, in this invention, the start of the write address to the line memory provided in the output buffer circuit is controlled according to the magnification, so that the enlargement/reduction is based on the center on the reading side. The same effect as that achieved in the above method can be obtained, and the recording is also performed with the center of the recording paper as a reference.

As a result, the reduced image may be recorded unevenly.

There is no risk of the image being recorded outside the transfer area of the recording paper, and even when the image is enlarged, there is no risk of it being enlarged to the margins, so the required image can be recorded correctly. .

Furthermore, since the present invention obtains interpolated data while referring to a data table, it has remarkable effects such as better image quality and faster processing than conventional methods.

[Brief explanation of drawings]

FIG. 1 shows I! of an image recording device capable of enlarging @reducing according to the present invention. Figure 2 is a waveform diagram for explaining other operations; Figure 3 is a diagram showing an example of an image processing circuit; Figure 4 is a diagram showing an example of interpolation data used when enlarging an image. , Fig. 5 is a diagram showing an example of interpolation data used at that time, Fig. 6 is a diagram showing an example of selection data used at the time of image enlargement, and Fig. 7 is a diagram showing an example of the data selection signal and processing timing signal at that time. A diagram showing the contents of the data table. The fjSa diagram is a diagram showing an example of the data selection signal used at the time of image reduction. FIG. 9 is a diagram showing the contents of the data table of the data selection signal and processing timing signal at that time.
Figure O is a signal waveform diagram for explaining the image enlargement processing operation, Figure 11 is a timing chart at that time, Figure 12 is a signal waveform diagram for explaining the image reduction processing operation, and Figure 13 is a timing chart at that time. , FIG. 14 is a diagram for explaining the line memory, FIG. 15 is an explanatory diagram of a recorded image, FIG. 16, FIG. 22, and FIG. 24 are diagrams each showing an example of the write start address, etc., and FIG. A system diagram showing an example of the output buffer circuit, FIG. 18 is a waveform diagram for explaining its operation, FIG. 19 is a system diagram showing an example of the main control circuit, and FIG. 20 is a system diagram showing an example of the output buffer circuit.
The figure is a system diagram showing an example of a clock control circuit, and FIGS. 21 and 23 are diagrams showing other examples of image reading and image recording. Fig. 25 is a system diagram showing an example of the main parts of a conventional image processing device that can be enlarged/reduced, Fig. 26 is a waveform diagram to explain its operation, Fig. 27 is an explanatory diagram of the image reading system, and Fig. 28 FIG. 2 is a diagram showing an image recording state. 2... Image processing circuit 10... Timing signal generation circuit 11.12, 14, 17.18... Latch circuit 13.
... Interpolation data memory 15 ... Counter circuit 16 ... Interpolation data selection memory 19 ... Gate circuit 22 ... Dither matrix 23 ... Binarization circuit 60 ... Image reader IR (CCD) 65... Output device 70... Main control circuit 90... Output buffer circuit Zoo, 101... Line memory 104.105... Address counter 120... Clock control circuit D... Image data S ...Interpolated data SD...Data selection signal CLK2...Synchronized clock TI)...Processing timing signal Patent applicant Konishi Roku Photo Industry Co., Ltd.) Fig. 4 Data selection signal SD Fig. 5 →Number of steps 1 +7 +8 +9 +A +B +C
+0 +E +F0. 0-00000 0
-511'++1Ofl All
iin'l! 11M111 411774') 11
4 m data selection signal SD ADRS +O+1 +2 +3 +4 +5 +8 data selection memory 16. +7 +8 +9 +A +B +C+D
+E +F Invalid data content l In case of large ratio 124/84) Figure 11: 5o31 Loincloth S) 3 b4 b5 b6 5
7 Data selection memo 1 Figure 9 → Contents of step number 16 (G ret rate 33/84) Figure 13 Figure 14 ＼ Mosquito-1j Figure 20 Figure 27 " (JJ, X I〒) Figure 22 Figure 24

Claims (4)

[Claims] (1) In an image processing device capable of enlarging/reducing an image using image data read by photoelectrically converting image information, an output buffer circuit for the image data is provided,
An image processing device capable of enlarging and reducing, characterized in that a writing start address of the image data to the output buffer circuit is changed in accordance with the enlarging and reducing processing. (2) The image processing device that can be enlarged and reduced as claimed in claim 1, wherein a write start address to the output buffer circuit is changed in accordance with an enlargement/reduction magnification. (3) The image processing device that can be enlarged and reduced according to claim 1, wherein the writing start address to the output buffer circuit is changed according to the size of the recording paper. (4) An image processing device that can be enlarged and reduced according to claim 1, wherein the writing start address to the output buffer circuit is changed depending on the reading or writing reference position of the original. .