JPS62221275A - Picture processing system capable of enlargement/ reduction - Google Patents

Abstract

PURPOSE:To record a picture with a specified magnification even when the resolution of reading and that of recording are different from each other by designating the resolution of reading corresponding to the resolution of recording of a recorder selected from the host computer side. CONSTITUTION:The picture information of an original 52 is read by a CCD 60 that is a reading means, and supplied to a picture processor 200. The picture- processed picture data is supplied to plural recorders 65A-65C provided in an output device 65, so that a desired picture is recorded. To the device 200, a host computer 300 is connected, and a picture data and a control command are transferred through a bus 301. Also, in accordance with a command from the computer 300, the reading resolution of the CCD 60 is determined corresponding to the recording resolution of the selected recorder. As a result, a recording picture that satisfies the specified magnification can easily be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a host computer that executes image processing such as enlarging and reducing a read image based on instructions from the host computer side. The present invention relates to an image processing system that can be enlarged and reduced, and has an image processing device.

[Background of the Invention] In an image recording bag capable of enlarging or reducing an original image, image data output from this image processing device is transmitted to a host computer and displayed on a display device or the like provided on the host computer. There are image processing systems that display images.

In such an image processing system, in order to enlarge or reduce an image, a photoelectric conversion element such as a COD is used as an image reading means, and the enlargement/reduction magnification is Enlarge/remove image data by increasing or thinning out appropriate image data.
A reduced image signal is obtained.

[Problems to be Solved by the Invention] By the way, in such conventional image processing systems, various types of image processing are executed based on instructions from the host computer side. Also.

In such an image processing system, a plurality of recording means are provided on the output device side connected to one image processing apparatus, and an appropriate recording means can be selected from among them by instructions from the host computer side.

In this case, the reading resolution of the COD, which is the image reading means, and the recording resolution of the read image data in the recording means are usually the same.

On the other hand, as recording devices have become more popular in recent years, recording means having a recording resolution different from the reading resolution may be connected and used. In such an image processing system, the magnification designation from the host computer is made only to the image reading means. Therefore, if the reading resolution and the recording resolution are different, one image will not be recorded correctly even if the specified magnification is used as is.

For example, if the reading resolution is 16 dots/cm and the recording resolution is 8 dots/colole, the recorded image will be 2 times the original image even if the externally set magnification is 1x. It will be recorded twice.

On the other hand, when the reading resolution is 8 dots/millimeter and the recording resolution is 16 dots/mi+, the image will be reduced to 1/2 and recorded.

Conventionally, no measures have been taken to solve this inconvenient problem, so if the reading resolution and recording resolution are different, it is necessary to ensure that the original image is recorded correctly at the specified magnification. , the specified magnification is changed in advance and set.

However, such a changing operation is not only very complicated, but also a source of errors.

Therefore, in the image processing system as described above, even when a recording means having a recording resolution different from the reading resolution is connected to perform image processing, the present invention provides an image processing system that can be specified by the host computer. This paper proposes an image processing system that can be enlarged and reduced so that recorded images can be obtained according to the specified magnification.

[L stage for solving problems] In order to solve the above-mentioned problems, in this invention, one image information is photoelectrically converted and read image data is supplied to an image processing device to perform image enlargement/reduction processing. The image data is then enlarged and inputted into the host computer.
A reducible image processing system, characterized in that the actual reading resolution of the image reading means is changed by instructions from the host computer side in accordance with the recording resolution of the recording device provided on the image processing device side. That is.

[Effect] Reading 1 [11] If the resolution and the recording resolution are different,
The reading resolution is changed to match the recording resolution.

In order to change the reading resolution, the host computer adjusts the magnification designation data based on the reading resolution corresponding to the recording resolution of the selected recording means and the magnification designation data set on the keyboard. This corrected magnification signal (hereinafter referred to as a corrected magnification signal) is a signal for ensuring that an image is recorded correctly at the magnification set on the keyboard.

This corrected magnification signal is supplied to an image processing circuit within the image processing device for enlarging/reducing the image.

As a result, this image processing circuit executes enlargement/reduction processing based on the corrected magnification designation data, and the enlarged/reduced image data is supplied to the recording means side.

[Example] Hereinafter, an example of an image processing system according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

However, in the example shown below, the center line (vertical direction) of the document
This is a case where the present invention is applied to an image processing system of the type that performs image processing based on .

As shown in FIG. 29, such a center-based image processing device processes the image data of the original 52 using the center edge of the table 51 as a reference, where W is the maximum reading width of the image reading means. The image is recorded based on this central border.

Therefore, when the image is at the same size, it is recorded as shown in FIG. 16C, when it is reduced, it is recorded as shown in FIG. 16A, and when it is enlarged, it is recorded as shown in FIG. 16B, respectively.

Note that in order to read and record images based on the center edge in this manner, a certain amount of special image processing is required. If we simply read the image and recorded the data, as shown in Figure 30, it would be fine at the same size (B), but when reduced it would be as shown in Figure A, and when enlarged it would be as shown in Figure C. This is because it will be recorded as such.

Now, FIG. 1 shows an example of an image processing system according to the present invention.

The image information of the original 52 is read by the C0D 60, which is a reading means, and this image signal (analog) is sent to the image processing device 2.
The processed image data is supplied to G00 and subjected to various image processing.
Multiple recording devices 65A to 65C provided in c2J65
A desired image is recorded.

A host computer 300 is connected to the image processing apparatus 200 and issues various image processing instructions to the image processing apparatus 200. Therefore, a plurality of buses are connected between the image processing device 200 and the host computer 300.

Bus 301 is a data bus for transferring image data and control commands, bus 302 is a control bus for controlling the transmission timing of image data, and bus 302 is a control bus for controlling the transmission timing of image data.
03 is a control bus for transferring control commands for further controlling the control commands. A bus 304 is a control bus (selection bus) for selecting a recording device 65.

Host computer 300 is controlled based on control signals input through keyboard 400.

600 is a display device, and the host computer 300
It is used to display information entered into the computer or to display a single-task menu.

Also, is the mouse 500 a display device? It is used to input coordinates required when laying out the image displayed in 1600 and to select a work menu.

Note that details regarding the image processing operation based on commands from the host computer 300 will be described later.

FIG. 2 is a system diagram showing a schematic configuration of an image processing apparatus 200 suitable for application to the above-described image processing system.

The image information of the original 52 is obtained by an image reading means 6 such as a CCD.
The relationship between the 0 image signal read at 0 and converted to an analog image signal and various timing signals is as shown in Figure 3, and the horizontal effective area signal (H-VALID)
(B in the same figure) Corresponding to the maximum document reading width W of the J*CCD 60, the image signal shown in F in the same figure is read out in synchronization with the synchronous clock CLK (E in the same figure).

In FIG. 2, an image signal is sent to an A/D converter 61, and 0 image data, which is converted into image data having 16 gradation levels (0-F), for example, is subjected to shading correction in a shading correction circuit 62. This is to correct shading caused by uneven sensitivity of the CCD 60, non-uniformity of the optical system, uneven illuminance of the irradiation lamp, etc. Therefore, before reading the document information, the CCD 60 reads information (one line) from a uniform density plate (white plate, etc.) provided in the non-image area of the reading device, and this data is stored in the memory 60 as non-uniform data.
It is stored in 3. This nonuniform data for shading correction is supplied to the correction circuit 62 together with the original image data, and shading correction is performed for each pixel.

The shading-corrected image data is sent to the image processing circuit 2.
The main control circuit 70 supplies data indicating a zero magnification (a corrected magnification signal, which will be described later), and the magnification/reduction processing is performed in real time at a specified magnification.

The image data subjected to image processing is sent to the binarization circuit 23,
Binarization is performed with reference to threshold data (for example, dither matrix data) stored in the threshold table 69. 2
The image data after the value conversion process is supplied to the output buffer circuit 90. The output buffer circuit 90 is provided to control the writing or reading timing of image data, and is controlled based on the writing and reading start address data sent from the main control circuit 70.

The image data obtained from the output buffer circuit 90 is finally supplied to the memory 64 for one image data and the image data is stored therein, or directly supplied to the output bag 2165 to record the desired image information. 0 image memory 6
4 is built in the host computer 300. As the output device 65, a recording device using a laser printer, an LED printer, or the like can be used.

Note that a magnification signal is supplied to the terminal 71, and reading resolution designation data is supplied to the terminal 72. Both the magnification signal and the reading resolution designation data are specified by the keyboard 400, and both of these are The signal is supplied to the main M control circuit 75 via the host computer 300.

The reading resolution designation data is also used as a selection signal for the recording device 65.

The main control circuit 70 automatically adjusts the magnification for recording an image at a designated magnification based on the magnification signal and reading resolution data. This corrected magnification signal is supplied to the image processing circuit 2 described above. The adjustment of the designated magnification will be described later. 66 is a reference clock generation circuit.

The reference clock output from the reference clock generation circuit 66 is supplied to a timing control circuit 67 to form various timing signals necessary for image processing. In other words, C.G.
In addition to timing signals for DNA utility (transfer port 7, etc.), timing signals for driving the address control circuit 6B for the memory 63, timing signals for the image processing circuit 2, and threshold values for the threshold table 69 for binarization processing are provided. Timing signals etc. are generated.

FIG. 4 is a block diagram showing an example of the image processing circuit 2. As shown in FIG.

In this example, 1.5% between 0.5x and 2.0x
(As an approximation to 1784) This is a case where it is possible to scale up and down in increments.

Here, also in this invention, in principle, the enlargement process increases the image data, and the reduction process is an interpolation process that thins out the image data. The enlargement and reduction in the main scanning direction shown in FIG.
The moving speed of the photoelectric conversion element or the image information is changed using the system.

Slowing down the movement speed in the sub-scanning direction enlarges the original image,
If you speed it up, it will shrink.

In FIG. 4, a timing signal generation circuit 10 is for obtaining timing signals etc. for controlling the processing timing of the entire image processing circuit 2, and includes a CCD 6
Similarly to 0, the synchronization clock (CLK), horizontal valid area signal (H-VAL In), vertical valid area signal % (V
VALID) and a horizontal synchronization signal (H-5YNC).

In addition to the above-mentioned timing signal, the timing signal generation circuit 1O also outputs a clock CKL2 having twice the frequency of the synchronization clock CLK in order to process the multiplication factor up to 2x in real time.

A series of image data having 16 gradation levels sent out from the CCD 60 is sent to two latch circuits 11 .
12, and image data DI and DO of two adjacent pixels among the 4-bit image data are latched at the timing of the synchronous clock CLK. These latch data are used as address data for the memory 13 for interpolation data.

The interpolation memory 13 is a data table in which new image data (hereinafter this image data will be referred to as interpolation data) referenced from two adjacent image data is stored.
ROM etc. are used.

In addition to the above-mentioned pair of latch data DO, DI, the address data of the interpolation memory 13 includes a data selection signal S.
D is used.

The data selection signal SD is a pair of latch data DO, D
It is used as address data for determining which data from among the data table group selected by I is to be used as interpolation data.

The data selection signal SD is determined by the set magnification for enlargement or reduction, as will be described later.

Figure fjS5 shows an example of interpolated data S selected by the latch data DO, DI and the data selection signal SD.

In the figure, S is interpolated data (4 bits) output with 16 gradation levels, and since the image data DO and D1 used as latch data each have 16 gradation levels, the interpolated data S is , 16X16=2
It contains 56 data blocks.

The figure shows the theoretical value (5 decimal places) at each step when Do = O, DI = F, and the value of the interpolated data S actually stored in the case of positive slope and negative slope. Show about.

Actually, interpolated data S is stored in the form shown in FIG. However, this data is D port = 4. DI=O
-F is an example.

In FIG. 6, AI)R3 is the base address, and when DO=4, the data selection signal 50 (horizontally arranged 0
The actual address for the interpolation memory 13 is obtained by adding (1) to the base address ADR3 and the data selection signal SD on the horizontal axis, which shows the relationship between the data from F to F) and the interpolated data S to be output.

The interpolated data S output from the interpolation memory 13 is latched by the latch circuit 14.

On the other hand, 16 is an interpolation data selection memory in which a data selection signal SD is stored. A data table is also used here, and data used as an address for selecting interpolation data (hereinafter referred to as data selection signal SD) is stored.

FIG. 7 shows 6 example data showing part of the data selection signal SD used when enlarging an image, when the magnification ratio M is 124/84, and the magnification can be set at an interval of 1784. Inside, Honda shows invalid data.

In this way, if the magnification can be set at intervals of 1/84, the repetition period will be 64, as shown in Figure 7.
becomes. Also, when the expansion rate is 124/84, the sampling interval is 84/124 (= 0.51813
), so the sampling position for the repetition period is 2
The relationship between 1 (theoretical value) and the data selection signal SD that is referred to is as shown in the figure.

In the data selection signal SD at the repetition period rQJ,
The former data (0) has a sampling position of (0,0Q
(IQQ), and the latter data (8) is the data selection signal SD when the sampling position is (0,518
13) is the data selection signal SD. These pairs of data selection signals SD differ depending on the value of the repetition period.

Note that at repetition periods of 15.32 and 48, the value of the latter data selection signal SD does not exist, which indicates that only one piece of data exists in that period.

These data are actually stored in the interpolation data selection memory 16 in a state as shown in FIG.

In FIG. 8, of the data selection signal SD referenced by the base address ADR3 (vertical axis) and the number of steps (horizontal axis), the data on the right side is data for write clock control (processing timing signal TD).

When the processing timing signal TD is “1”, writing is enabled 7! i (write enable) and ° When “O”,
The state becomes write-protected. Therefore, the data “00” in the figure
″ indicates invalid data.

Figure 9 shows the interpolation data selection signal SD used during image reduction.
Six example data showing a part of the data table are for the case where the reduction ratio M is 33/64.

In the figure, this data selection signal TD, which indicates Honda's thinned-out data, is also stored in the memory 16 in a state as shown in FIG.

Now, the above-mentioned interpolation data selection memory 16 is supplied with a correction magnification signal as address data to its upper 7 bit address terminals A7 to A13. The corrected magnification signal is supplied from the main control circuit 70 as described above. Further, the counter output of the counter circuit 15 is supplied as address data to the lower 7 bits of address terminals AO to A8. Therefore, the counter circuit 15 has a synchronous clock CL.
K2 is supplied.

An interpolation data selection signal S is sent from the interpolation data selection memory 16.
In addition to D, a processing timing signal TD is output.

As described above, the processing timing signal TD is selected to be 1'' when interpolated data exists, and ``0'' when there is no interpolated data or when data is to be thinned out.

The data selection signal SD and the processing timing signal TD are latched by the latch circuit 17. The latch timing is regulated by the synchronization clock CLK2.

The processing timing signal TD controls the timing of the interpolated data S to be latched in the latch circuit 14, and therefore the processing timing signal TD is once supplied to the latch circuit 18.

It is delayed by the access time of interpolation memory 13.

The processing timing signal TD delayed by a predetermined time (one period of the synchronous clock CLK2) is supplied to the gate circuit 19 as its gate signal.

The gate circuit 19 is supplied with the synchronizing clock CLK2, and is closed when the processing timing signal TD is "1''.
It is controlled to be open when it is "O", and a clock is output only when it is "I".

The synchronization clock CLK2 outputted from the gate circuit 19 is used as a latch pulse of the latch circuit 14, and latches valid data among the interpolated data S outputted from the interpolation memory 13. The synchronous clock CLK2 is also used as a write clock for the output buffer circuit 90 at the subsequent stage.

What has been explained above is the main configuration of the image processing circuit 2. After the output data obtained from the image processing circuit 2 is once converted into a z-value, it is sent to the output buffer 7 circuit 90 (details will be described later).
The image data is supplied to an output device 65 or an image memory 64 via.

An example of the circuit configuration for z-value processing will be explained with reference to FIG. 4 again.

In the figure, a main scanning counter 20 counts the write clock of the tA value table 69, and a sub-scanning counter 21 counts the horizontal synchronization signal.

It has a dither matrix 22 that outputs a dither threshold value based on the count values of these counters 20 and 21.

Then, in the binarization circuit 23, the image data output from the latch circuit 14 is compared with the dither threshold value from the dither matrix 22, and binarized for each pixel.

Next, the image processing operation of the image processing apparatus 2 described above will be described in detail, starting with the enlargement processing operation, with reference to FIG. 11 and subsequent figures. For convenience of explanation, the magnification rate M is 124/84 (=
194) Double.

FIG. 11 is an analog diagram of the relationship between original data and interpolated data, where D indicates the original data and S indicates the output data after interpolation.

The relationship between the image information level and the interpolated data at this time is as shown in FIG. Further, the relationship between the sampling pitch and the data selection signal SD during interpolation at this time is as shown in FIG.

A timing chart of signals in each section during this interpolation process is shown in FIG.

Therefore, the original image data obtained from the CCD 60 is now D Q (0), D I (F), D 2 (F).
, D3(0), D4(0) (the gradation level of each image data is shown in parentheses), DI(F) is sent from the latch circuit 11 in synchronization with the synchronous clock,
Do(0) is output from.

On the other hand, the data table shown in FIG. 8 is referred to based on the externally set magnification signal and the output of the counter circuit 15, and the data selection signal SD is o, a; o, a; 1.
, 9.1.9; ... (Fig. 12E) are output, and the processing timing signal TD is 1, 1, 1 . ...(FIG. F) is output.

The interpolation memory 13 refers to the interpolation data table using the image data DG, DI and the data selection signal SD, and outputs necessary interpolation data S (G in the figure).

That is, since the data selection signal SD is 0 and 8 between the image data D 0 (0) and DI (F), O and 8 are output as the interpolation data SO and Sl.

Since the data selection signal SD is 0 and 8 between image data DI(F) and 02(F), interpolation data S2
And as S3, F and F are output.

Between image data D2(F) and 03(0), since the data selection signal SD is 1 and 9, the interpolated data S
E and 7 are output as 4 and S5.

Since the 1 selection means SD is 1 and 9 between the image data D3(0) and D4(0), 0 and 0 are output as the interpolation data S8 and S7.

After that, the image data D5. Regarding DB, . . . , the interpolation data S is read in the same manner as described above.

Therefore, the data after interpolation is represented by an x mark.

As shown in Figure t511, it can be seen that image data having a predetermined level between original image data is interpolated and output.

In this way, the interpolated data SO to S7 are sequentially read out using the interpolation method for the actual image data DO to D4,
These interpolated data S are sequentially sent to the latch circuit 14 (I in the same figure).

On the other hand, the processing timing signal TD output from the latch circuit 17 is delayed by a time t (see FIG. 12) in the latch circuit 18, but this delay time t is, as described above, This is the time required for access, and the time required for the latch circuit 14 to read the interpolated data S.

Since the on/off state of the gate circuit 19 is controlled by the processing timing signal TD from the latch circuit 18, the latch circuit 14 performs a latching operation only when the gate circuit 19 is on, and does not perform a latching operation at other times. Not possible.

Next, the reduction process will be explained.

FIG. 13 is an analog diagram of an image signal in the case of reduction processing, and is image data DO.

Di, D2, D3, . . . are represented by O marks, and interpolated data SO, 31, . . . are represented by × marks. FIG. 14 shows a timing chart of the signals at that time, and the relationship of the data selection signal TD used at that time is as shown in FIG. 9 (FIG. 10).

Note that the reduction ratio M illustrated here is 33/84 (・0.5
2), and the gradation level of one image data is the same as in the case of the enlargement process described above.

Two adjacent image data (
For example, one image data (Di, Do) is supplied to the interpolation memory 13 as an address signal, an externally set reduction magnification (33/84) is supplied to the interpolation data selection memory 16, and a periodic clock CLK2 is supplied to the interpolation data selection memory 16. circuit 15
The counting is the same as in the case of the enlargement process described above.

As is clear from FIG. 9 and FIG. 1θ, the data selection signal SD is output from the selection memory 16.

09 lines; F2 lines: 9 lines, E, O, ...... are output, and the processing timing signal TD is 1,0°1,
Q, O, O, l, . . . are output. However, since the book is invalid data, 0 data is stored in the interpolation data selection memory 16.

Therefore, interpolated data S as shown in FIG. 14 is read out from the interpolated data memory 13.

That is, since the data selection signal SD is 0 and a tree between the image data D0(0) and Dt(F), only O is output as the interpolation data 5 (=SO).

Between the image data DI(F) and 02(F), since the data selection signal SD is equal to F, the interpolated data S1
As, F is outputted as 0 image data D 2 (F) and D
Between 0 image data D3(0) and D4(0), the selection data SD is Since it is E and a book, only 0 is output as the interpolation data S2.

Subsequent image data D4. D5. . . . The interpolation data S is read out in the same manner as described above.

In this way, the actual image data Do, DI.

. . . Data is obtained by interpolation method, and interpolated data SO, S1 . ... are read out sequentially.

The interpolated data S is sequentially transferred to the latch circuit 14.

On the other hand, the processing timing signal TD is 0,1,0°0.0.
1... (F in the same figure), the gate circuit 19
Since the written data 7 output from 7 becomes as shown in FIG. 14H, certain data are thinned out and interpolated data
, Sl, . . . are output (I in the same figure).

As mentioned above, when reducing the size, new image data is given between the original pixels of the original image information and that image data is output, and some of the image data of the original pixels is interrupted. , which outputs the value as is,
These output image data are generally referred to as interpolation data.

In the embodiment described above, if the magnification of enlargement or reduction is changed, the data selection signal SD output from the selection memory 16 for interpolation data changes, and the memory 13 for interpolation data is addressed accordingly to perform the corresponding interpolation. It will be clear that data S is output.

Now, the image data that has been subjected to enlargement/reduction processing and 2-1 conversion processing is supplied to the output buffer circuit 90.
In this output buffer circuit 90, data write or read timing and write or read address for the line memory provided in this output buffer circuit 90 are controlled according to the magnification/reduction ratio. The reason why these timings and addresses are controlled according to the magnification will be explained with reference to FIGS. 15 and 16.

For example, if the maximum image reading size of CCD60 is 84 format and its resolution is 18 doLs/■ intestine,
Considering that the amount of image data for 1247 minutes is 4096 bits and the zero magnification is up to 2, a line memory with a capacity of 8192 bits as shown in FIG. 15 is prepared as a line memory for storing image data.

Then, as a result of recording, image data is written or read out so that the center (2048 pittros) becomes the reference.

Therefore, when reducing one image, for example, when reducing an image to 1/2, the line memory write start address is 40.
Since it will be set to an address corresponding to 1/4 of 96 bits (address number 1024), in that case, the reduced image data will be stored in the line memory as shown in Figure A of i15. .

On the other hand, the read start address is set to 0 address. Therefore, a reduced image is recorded as shown in FIG. 16A.

This is because the image data from the O address to the 1023rd address is "0", so that period is considered white and recorded on the recording paper, and recording based on the reduced image data starts from the 1024th address. This is because it becomes

For example, when the reduction ratio is 32764, the reduced image data is written from 1024 addresses. Similarly 33/θ4
When the reduction rate is , data is written from 992 addresses, and 34
When the reduction ratio is /84, data will be written from address 960.

In this way, the image data is written so that the result is centered, and the image is recorded with the 0 address as the standard (or the center line of the recording paper 53). Become.

For this reason, the write start address when reducing is
The settings are as follows.

Write start address=(409B-4098X reduction magnification) 72 When enlarging an image, since image data increases, the read start address is controlled in the opposite way to when reducing.

If the maximum magnification is 2x, the image data at that time will be twice the image data at the same magnification.

In that case, the area of the recorded image will be quadrupled.1 For example, even if you try to double the size of a 34-size document, if the maximum size of the recording paper is up to 84-size, the entire enlarged image will be printed on the recording paper. cannot be recorded.

Considering this, it is possible to obtain a more natural enlarged image by limiting the image data to be written in advance according to the maximum size of the recording paper.

Therefore, when enlarging one image, as shown in FIG. 15B, a total of 4 bits, 2048 bits before and after 1/2 of the enlarged image data amount (corresponding to the position of the center ml of the enlarged image), are used as a reference.
096 bits will be read.

Therefore, when the enlargement ratio is 12B/84, the data from the first data to the 2047th bit of the enlarged image data is ignored, and reading from the data of 2048 pittros to the line memory is started, and from this a total of 40 bits are ignored.
96 bits of image data will be read out.

In contrast, the write address is set to "0".

Similarly, when the magnification is 127/84, reading starts from the 2016th bit, and when the magnification is 124/64, reading starts from the 1984th bit, and from this a total of 4096 bits of image data are read. It turns out.

Needless to say, even when setting another magnification rate, image data from the readout start address corresponding to the magnification rate is selected.

For this reason, the readout start address at the time of enlargement is set as follows.

Read start address = (408B x enlargement magnification - 4096)/2 Note that when writing data to the line memory from the middle of enlarged image data in this way, image data corresponding to the center part of the original image is written. Therefore, the probability that an image will be missing due to enlargement to an unnecessary portion is greatly reduced.

To summarize the above, the write start address that is generated during enlargement/reduction is set as shown in FIG. 17.

FIG. 18 and subsequent figures are circuit diagrams showing an example for realizing the above-described operation.

FIG. 18 shows an example of the output buffer circuit 9o. The output buffer circuit 9o includes a pair of line memories 100, 10.
1 is provided, and each is supplied with image data for one life. The reason for providing the pair of line memories 100 and 101 is to alternately supply one line of image data so that writing and reading of image data can be processed in real time. Line memory 100. The lot used has a capacity of 8192 bits as described above.

Writing and reading from the line memory Zoo, 101 is controlled as follows.

First, when writing data to the line memory, the write clock generated in the image processing circuit 2 is used, and when reading data, the read clock for the output device 65 is used. 2 switches 102.103 to respective address counters 104.105.

The first and second switches 102 and 103 are controlled in a complementary manner so that when one line memory is in the write mode, the other line memory is in the read mode. The switch control for this is the control circuit 10.
Horizontal period control signal output from 7 (19th
Figure C) is used.

Each address counter 104, 105 is further supplied with address data for determining a write start address and a read address for the line memories 100, 101 via third and fourth switches 108, 109. The third and fourth switches 108, 109 are also controlled in a complementary manner so that when one address counter is in the write mode, the other address counter is in the read mode. 109 is also supplied with a horizontal period control signal as shown in FIG. 19C.

The write start address or read start address is preset in the address counter 104 or 105 in synchronization with the horizontal synchronizing signal (FIG. 19A).

Line memory 100. After one of the outputs from the lot is selected by the fifth switch 110, it is supplied to the output device 65 described above. Since the fifth switch 110 is for selecting image data from the line memory in the read mode, a signal having an opposite phase to the control signal shown in FIG. 19C is used.

In addition, this FIG. 19 shows a timing chart at the time of reduction, and in the same figure, E is for the line memory 100, and F in the same figure is shown.
, G indicate the writing and reading timings of image data to and from the line memory 101, respectively.

The write start address (data) is generated by the main control circuit 70 shown in FIG.

In FIG. 20, 75 is a CPU, 76 is a ROM in which a control program is stored, and 77 is a ROM in which write address data shown in FIG. 17 is stored.

Since the magnification set on the keyboard 400 is supplied from the host computer 300 side to the CPU 75 via the I10 port 78, the write start address corresponding to that magnification is sent to the third or fourth switch mentioned above via the I10 port 79. 108.109.

The main control circuit 70 is supplied with reading resolution designation data as described above. In this example, as shown in FIG. 1, three recording devices 2i65A to 65 with different recording resolutions are
A case is shown in which C can be selected on the host computer 300 side.

First recording device i! The reading resolution of 165A is 16
dots/■ When recording, the second and third recording devices 65
Each reading resolution of B and 65C is 12dots/ms
, 8 dots/ms.

Selection of these reading resolutions is made by the host computer 30.
This is done by a command signal from the 0 side.

Reading resolution (digital data) is I10 po) 15
1 to the CPU 75.

In the CPU75, this reading resolution and the keyboard 40
From the magnification signal set at 0, a new magnification for correctly recording the image at the specified magnification is determined by calculation or by referring to the data table. In the case where a signal is generated, an example of the data table is shown in the second example.
Shown in Figure 1.

As mentioned above, the reading resolution of the CCD 60 is 16
dots/■■, and when the recording resolution of the recording device is the same as the reading resolution, the same data as the specified magnification is selected as the correction magnification signal.

However, when the recording resolution is 8 dotg/as, the reading resolution is twice the recording resolution, so for example, when the specified magnification is set to 2x,
As the correction magnification signal, 1 and 0 (84/64) times are selected.

In the image processing circuit 2, enlargement/reduction processing is executed based on this corrected magnification signal, so in the above example, even if the specified magnification is 2x, data processing is performed by regarding it as the same magnification. However, since the recording resolution of the recording device is l/2,
Even if the image data is the same size, the recorded image will be doubled.

Therefore, the relationship between the designated magnification and the corrected magnification signal is as shown in FIG.

In addition, when the recording resolution is l 6 dots/mm, the reduction rate of 0.5 times means that the recording resolution is 8 dots/■■
In this case, it is 1B/111.
4x is the revised magnification.

When the designated magnification is equal magnification or reduced magnification, a corrected magnification signal corresponding to each magnification is selected.

In this way, even if the host computer 300 selects a recording device with a recording resolution different from the reading resolution, by using the corrected magnification signal,
Images can be recorded at externally specified magnifications.

Next, the operation of the image processing system shown in FIG.
This will be explained in detail with reference to the figures below.

(1) From the host computer 300 to the image processing device 212
When transferring control commands to 00 bias.

This will be explained with reference to the timing chart in FIG. 22. When transferring a control command, the host computer 300 sets the command data valid signal OBF on the command control bus 302 to "L" and transfers the DB on the data bus 301.
Loads the 8-bit control command of O-DB7. CPU
75, the command data valid signal 0BF (A in the same figure) is “L”.
”, the command control bus 302
There is a negative logic 7-knowledge signal "-'tACK" (B in the same figure).
), and at the same time take in the control command data DBO-DB7 established on the data/Hess 301 (C in the same figure).The taken control command data is CP
Sent to U75. The CPU 75 decodes the sent control command and performs the corresponding operation.

For example, in the case of a command specifying a magnification of 1, a magnification selection signal is output to the image processing circuit 2 and displayed on a display section (not shown) provided on the host computer 300. In this case, the magnification displayed is the magnification set on the keyboard 400. (2) Image processing bag f! 1200 to the host computer 300.

Theory I while referring to the timing chart shown in FIG.
Do J+. The CPU 75 receives 5 TB of command data strobe pulses on the command control bus 302 (FIG. 23A).
8 bits of image data or control commands DBO to DB are output on the data bus 301 in synchronization with this.
7 (C in the same figure).

When the host computer 300 receives the STB pulse,
Control commands DBO~D are sent to the internal latch circuit (not shown).
B7 is latched and the command data import signal IBF (B in the same figure) of the command control bus 302 is set to H". At this point, the host computer 300 has not yet read the captured command data DBO-DB7. Therefore, the host computer 300 cannot receive or receive the next data.After completing reading the control command in synchronization with the rising edge of the STB pulse, the host computer 300
Set the signal to L''.

When the CPU 75 confirms that this IBF signal has become "L", it transfers the next image data or control command.

After the transfer of the control commands shown in (1) and (2) is completed, the document information reading operation is started.

(3) Jg draft information reading operation This will be explained with reference to the timing chart shown in FIG. When the host computer 300 becomes ready to read image information, it outputs a reading start command (not shown) through the image signal control bus 302. After the CPU 75 on the image processing device 200 side decodes this command, Start reading the original information.

1 when the image processing circuit 2 starts enlarging/reducing processing.
The host computer 30 receives the start pulse STP pulse (FIG. 24A) read through the image @gokawa control bus 302.
Output to the 0 side.

When the host computer 300 receives this STP pulse, it puts the internal image memory 64 into a writing state (B in the same figure), and lowers the image signal line sync signal VLS (C in the same figure) to "L" to 1. Synchronize the lines. Here, a state where the VLSc signal is "L" indicates a valid image area, and a state where the VLSc signal is "H" indicates an ineffective image area (planking area).

After confirming that the VLS signal has become L", the image processing device 200 side outputs binary image data DO to D7 (
D) in the figure is output onto the data bus 301. In this case, for image processing, the data bus 3 is
Image data DO-07 established on 01 is written into the image memory 64. When the image processing device 200 reads one page of document image information, it issues a reading end signal VEND.
(FIG. F) is output onto the image signal side control bus 302,
This completes the original information reading operation.

By the way, in the above example, the image is read with the center of the document as the reference point, and the image processing device uses the center of the recording paper as the reference point.
I gave an example where a sword is applied.

This output Ij+ can also be applied to other image processing devices. In that case, the output bar, writing of image data to the alpha circuit 90, etc. are slightly different.

First, when both single image reading and image recording are processed with one side of the original (recording paper) as the standard, the image reading start position of the CCD 60 and the recording start position (for laser printers) , the recording beam start position of the laser beam) are the same.

Second, there is a type of image processing in which image reading is performed based on the center line of the document, and image recording is performed based on one side of the recording paper! Ici! For i, the write and start address to the output backup circuit 11390 is as follows.

In this case, the write start address to the line memories 100 and 101 is always the O address.

On the other hand, the readout start address cannot be determined only by the magnification signal and differs depending on the size of the document.

Therefore, in this type of image processing apparatus, the readout start address is determined from a signal indicating the document size and the magnification.

As shown in FIG. 25, the case where the size of the document 53 to be read is A4 size will be described below.

As mentioned above, when +8 dots/■■.

The number of bits for the width of A4 size is 210mm x 18dots/mm = 3380
Since it is a bit, if the maximum read original size is 84 size, the value obtained by multiplying the width Y by a magnification in FIG. 25 becomes the read start address for the line memory.

Therefore, the read start address at the same magnification is (409B
-3380) / 2. = 388 bits.

The value of the write and start address at any magnification is
As shown in FIG. 6, however, the original size is A4.

Thirdly, in an image processing apparatus of the type in which image reading is performed based on one side as shown in FIG. 27, and image recording is processed based on the center ml of the recording paper, the The write and start address of is determined as follows.

In this case, the maximum number of bits for A4 size (3360 bits) and the maximum number of bits for 84 size (4096 bits)
The write start address is determined from the bit). That is, write start address=(409B-3380X magnification)/2. At this time, the read start address is 0 address.

When the write start address becomes negative (at the time of expansion), that value becomes the value of the read start address. Therefore, the write start address at this time is the O address.

FIG. 28 shows the values of write and read start addresses at arbitrary magnifications.

In addition, in the above-mentioned embodiment, the enlargement/reduction ratio is set to 128/8.
Under the condition that it is possible to select from 4 to 33/84 in l/64 increments, the timing generation circuit lO
The synchronous clock CLK2 obtained by the above is set to have a frequency twice that of the reference synchronous clock, but this frequency is determined by the maximum magnification ratio.

For example, when the maximum magnification rate is set to 3iΔ,
The frequency of the synchronization clock CLK2 is 3 times that of the reference synchronization clock.
Therefore, the frequency of the periodic clock CLK2 is changed depending on the maximum enlargement ratio used.

The writing start address to the line memories 100, 101 may be changed according to the paper size of the recording paper instead of changing according to the document reading or writing reference position.

) The MoIJ 13.16 may use a RAM instead of the ROM (7), and the memory 13 may use an arithmetic circuit instead.

[Effects of the Invention] As explained above, in this invention, by specifying the reading resolution corresponding to the recording resolution of the recording device selected on the host computer side, this additional reading resolution and the magnification set on the host computer side can be adjusted. Since a corrected magnification signal is generated from the signal and enlargement/reduction processing is executed based on this corrected magnification signal, even if the reading resolution and recording resolution are different, the specified magnification from the host computer side Images can be recorded with .

From this, the present invention has the practical benefit of being able to easily and reliably form a recorded image that matches the specified magnification. In this case, the magnification is automatically corrected, so there is no need to specify the magnification while considering the selected recording resolution.
The magnification designation operation can be greatly simplified.

In addition, at this time, the display on the host computer side will display the magnification specified on the keyboard rather than the corrected magnification.6 If the corrected magnification was displayed on the display, it seems that the magnification was specified incorrectly. This is because there is a risk of creating an illusion.

Furthermore, since the start of the write address to the line memory is controlled according to the magnification, the same effect as when enlarging/reducing is performed based on the center of the reading side can be obtained, and the same effect can be obtained for recording. The center of the recording paper will be recorded as eight proboscises.

As a result, there is no risk that the reduced image will be recorded unevenly or that the image will be recorded outside the transfer area of the recording paper, and even when enlarging one image, there is no risk that the margin will be enlarged, so the required image It has characteristics such as being able to record correctly.

Furthermore, since the present invention obtains interpolated data while referring to data tuples, the image quality is better than that of conventional methods, and high-speed processing is possible.
It has remarkable effects.

[Brief explanation of drawings]

Fig. 1 is a system diagram showing an example of an image processing system suitable for applying the present invention, and Fig. 2 is a system diagram showing an example of an image processing system suitable for applying the present invention, and Fig. 2 shows a rapid image recording that cannot be enlarged or reduced! a! Fig. 3 is a waveform diagram to explain its operation, Fig. 4 is a system diagram showing an example of an image processing circuit, and Fig. 5 is a diagram showing an example of interpolation data used when enlarging an image. , FIG. 6 is a diagram showing an example of the interpolated data table at that time, FIG. 7 is a diagram showing an example of content selection data of the data table used when enlarging the image,
Figure 8 is a diagram showing the contents of the data table of the data selection signal and processing timing signal at that time, Figure 9 is a diagram showing an example of the data selection signal used during image reduction, and Figure 10 is the data selection at that time. A diagram showing the contents of a data table of signals and processing timing signals, FIG. 11 is a signal waveform diagram for explaining the image enlargement processing operation, FIG. 12 is a timing chart at that time, and FIG. 13 is an explanation of the image reduction processing operation. FIG. 14 is a timing chart at that time, FIG. 15 is a diagram for explaining the line memory, FIG. 16 is an explanatory diagram of recorded images, and FIGS. 17, 26, and 28 are diagrams for explaining the recorded image. FIG. 18 is a system diagram showing an example of the output buffer circuit, FIG. 19 is a waveform diagram for explaining its operation, and FIG. 20 is a system diagram showing an example of the main control circuit. , FIG. 21 is a diagram showing the relationship between the corrected magnification signal determined by the designated A8 rate and the reading resolution, tjS22 to FIG. 24 are waveform diagrams for explaining the operation of the 111g1 processing system, and FIGS. 25 and 27 Figure 29 shows another example of image reading and image recording.
The figure is an explanatory diagram of the image reading system, and FIG. 30 is a diagram showing the image recording state at that time. 2... Image processing circuit 60... Image reading means (COD) 65... Output device 't1 (recording device) 70... Main control circuit 90... Output buffer circuit 200... Image processing device 300...Host computer 400...Keyboard 700...Selection switch D...Image data S...Interpolation data SD...Data selection signal TD...Processing timing signal Patent applicant Roku Konishi Photo Industry Co., Ltd.'tJ4) Figure 5 Data selection signal SD Figure 6 → Number of steps +8 +9 +A +B +C+D
+E +F3 contents 00-000000! 'ill;F103Jlj
J glare 1a: Jj (J listening, 708-10 3
BM = 124/64 ADRS +0 +1 +2 +3 +4
+5 data selection +8 +7 +8 +9 +A +B +
C + o + E + F Mori 16 contents q Vast rate 124
/64) low 00000 0 40
4 (179710R40, 72730 S-n Σ-Punishment SD Contents of 1st data selection memory 1 6 (MyJ433/84 increase) Fig. 12 bo':) I b2 b3 ”) 4 Ss
S6 57 Figure 14 S) 0 52 Ss Figure 15 Figure 16 Bar small time Answer input 1f
Side 1 Clear Figure 17 Figure 21 180nS Data 11 Surprised Figure 26 Figure 28

Claims (2)

[Claims] (1) Image processing that allows for enlargement and reduction in which image data read by photoelectric conversion of image information is supplied to an image processing device, which performs image enlargement/reduction processing, and then inputs the image data into a host computer. The system is characterized in that the actual reading resolution of the image reading means is changed by an instruction from the host computer according to the recording resolution of a recording device provided on the image processing device. An image processing system that can be enlarged and reduced. (2) The actual reading resolution is changed based on the recording resolution and a magnification signal set on the host computer side. An image processing system that can be enlarged and reduced as described in Section 1.