JPS62169278A - Picture processor - Google Patents

Abstract

PURPOSE:To perform the magnification and the reduction of a picture with good picture quality with a simple circuit constitution using an interpolation by reading out an interpolated data based on an interpolation data selection signal outputted corresponding to a set condition. CONSTITUTION:A picture processor 1, after converting a bit of read picture information, such as an original, etc., to an electrical signal, A/D-converting, and applying a shading correction, outputs it as, for example, the picture data of 16 gradation level. A picture processor 2 prepares the data which interpolates the picture data between the picture elements of the bit of picture information, and reads out the interpolation data based on the interpolation data selection signal outputted corresponding to the set condition, and performs a magnifying process or a reducing process with a magnification set from the outside. A picture processed data is recorded at a recording device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device that enlarges or reduces an image using an interpolation method.

(Prior Art) Image recording devices that enlarge or reduce original images and record them have been developed. To enlarge or reduce the image, we continuously interpolate between the pixels of the original image read by a solid-state image sensor to obtain an image signal with a shape close to a curve, and then change the sampling period according to the enlargement or reduction ratio. I was getting a scaled image.

If this is done, many calculations or complicated calculations must be performed in order to fill in data between pixels of the solid-state image sensor, resulting in a disadvantage that the circuit becomes complicated. Alternatively, there is a conventionally known method of changing the period of the readout lock, that is, the transfer lock, of the original image read by a solid-state image sensor (Japanese Patent Laid-Open No. 146358/1983).
issue). That is, when performing enlarged recording, the transfer lock cycle is made longer than when recording at the same size, and conversely, when performing reduced recording, the transfer lock cycle is shortened. However, with such a method, it is not possible to obtain interpolated data that supplements data between arbitrary pixels, especially in the case of enlargement. In the above method, the transfer lock used for enlarged recording and reduced recording is created using the reference clock used for equal-magnification recording, so a circuit for this purpose is required. Also, changing the transfer lock cycle for enlarging or reducing requires controlling the exposure amount (time).
A circuit for this will also be required. Furthermore, in the above method, when enlarging or reducing, the image is recorded using image data sampled with a transfer lock at a predetermined cycle. Therefore, for example, when enlarging a diagonally shaded area, the jaggedness becomes worse and less smooth than when magnified at full size. There is also the problem that image quality deteriorates.

(Objective and Structure of the Invention) The present invention has been made in view of the above points, and its main purpose is to enlarge or reduce an image with good image quality using an interpolation method with a simple circuit configuration, or to improve pixel density. It is also possible to perform conversions, and to achieve this purpose,
Interpolation data for interpolating image data between pixels of image information is prepared in advance, and the interpolation data is read out based on an interpolation data selection signal output according to set conditions.

(Example) The present invention will be explained below based on the drawings.

FIG. 1 shows a schematic configuration of an image recording device using an image processing device according to the present invention, where l reads image information of a document or the like using a photoelectric conversion element such as a CCD and converts it into an electrical signal, and A /D conversion, shading correction, etc., and outputting the image data as image data of, for example, 16 gradation levels (0 to F); The image processing device 3 is a recording device such as a laser printer or an LED printer that records an image using image-processed data.

FIG. 2 is a block diagram of an embodiment of an image processing apparatus according to the present invention. ) This is an example of an image processing device that reduces and enlarges images in increments.

In principle, enlargement processing is performed by increasing the image data, and reduction processing is performed by thinning out the image data. Enlargement and reduction in the main scanning direction are performed by electrical signal processing, and enlargement and reduction in the sub-scanning direction are performed by thinning out the image data. The exposure time of the COD is kept constant, and the moving speed of the CCD or image information is changed.Slowing down the moving speed in the sub-scanning direction will enlarge the image, and increasing it will reduce the image.

In the figure, 10 is a timing signal for timing the entire processing circuit based on a synchronization clock, a horizontal effective area signal, a vertical effective area signal, and a horizontal synchronization signal, which are timing signals from an image reading device (see FIG. 1) not shown. 11.12 is a series of 16-gradation image data (4 bits) sent from the image reading device (see Figure 1). This is a latch circuit that latches image data D and D of two adjacent pixels (for example, data read from a document) using a synchronous clock. 13
is a ROM-configured interpolation data memory that stores a table of image data between two adjacent pixels (hereinafter referred to as "interpolation data J"), and the addresses are image data D, D.
A data selection signal SD is given to indicate which position data to output after linear interpolation. Data selection signal (4 bits) in Table 0 showing a part of the interpolation data table in Attached Table IA
SD will be described later, but it is determined by the set magnification for enlargement and reduction.

Also, S is interpolated data (4 bits) output at 16 gradations. Since image data D and D can each have 16 gradations, the interpolation data table contains 16X1.
6=256 types of data blocks are included. Actually, it is stored in the interpolated data memory 13 in the form of Appendix IB.

Returning again to FIG. 2, 14 is a latch circuit that holds interpolated data read out from interpolated data memory 13, and 15
16 is a counter circuit that counts the double period synchronization clock CLK2 generated from the timing generation circuit IO;
is the interpolation data selection data 5D (4 bits) which is addressed and stored in advance according to the set enlargement/reduction magnification (A-A) and the count value (to) of the counter circuit 15, and the enlargement/reduction time. This is an interpolation data selection memory that outputs processing timing data TD (1 bit), and a part of the selection data table is shown in Appendix 2A. And when thinning out, set it to "0" 0 The selected data shown as an example has an enlargement ratio of 124/84 and a reduction ratio of 33/6.
These are two examples when the magnification is 4, but in reality the magnification is 32/
Daples are stored for each magnification in steps of 1/64 between 84 and 128/134. Further, the interpolation data selection memory is stored in the form of Appendix 2B. 17 is interpolation data selection data SD and processing timing data TD.
A latch circuit 18 holds the processing timing data TD output from the latch circuit 17 in synchronization with the synchronization clock CLK2, and delays the processing timing data TD by the necessary access time in the interpolation data memory 13 in synchronization with the synchronization clock CLK2. , 19 are gate circuits that are opened and closed according to the processing timing data from the latch circuit 18 to control whether to pass or block the synchronized clock CLK2, and are opened when the processing timing data TD is "1" and are "0". Closed. The output from this gate circuit 19 becomes the write clock for the recording device 3.

The circuit configuration explained above (the part surrounded by the broken line in Figure 2)
is an image processing apparatus according to the present invention, and the diagram shows a main scanning counter 20 for counting write clocks, a sub-scanning counter 21 for counting horizontal synchronizing signals, and a circuit configuration necessary for recording an image. counters 20, 21
A dither matrix 22 that outputs a dither threshold value based on the count value of , and a binarization circuit 23 that compares the image signal output from the image processing circuit with the dither threshold value of the dither matrix 22 and binarizes it are shown. There is.

Next, FIGS. 3 and 4 show the operation of the above image processing device.
This will be explained using figures.

FIG. 3 shows a time chart of signals in each part of the image processing device shown in FIG. 2, and FIG. It shows the section. As an example for explanation, the enlargement ratio is assumed to be 124/64 (=1.94).

Next, the operation of the image processing device will be explained.

FIG. 3 is a timing chart showing the mutual time relationships among the horizontal synchronization signal, horizontal effective area signal, vertical effective area signal, synchronization clock CLK, and image data input from the image reading device to the timing generation circuit IO of the image processing device. Yes, 4th
The figure shows a timing chart of signals in each part of the image processing device shown in Fig. 2 in the case of enlargement processing, and Fig. 5 shows the relationship between image data and interpolation data necessary for explaining the image enlargement processing. It is something that The enlargement ratio illustrated here is 124/84 (=1.94).

The image data output from the image reading device (see Figure 1) is D (0), D (F), D (F), D (0), D.
(0) (The gradation level of each image data is in parentheses), the latch circuits 11 and 12 synchronize with the synchronous clock, and the latch circuit 11 outputs D (F), and the latch circuit 12 outputs D ( 0) is output and the interpolation data memo January 3 address terminals (A4 to A7) and (to to A
) respectively.

On the other hand, the counter circuit 15 counts the synchronized clock CLK2 generated from the timing generation circuit 10, and transfers the count value to the address terminal of the interpolation data selection memory 16 (
Ao-A, ,), and address terminal (to A7~).
The magnification set externally is input to . Since the interpolation data selection memory 6 stores a table of interpolation data selection data as shown in Appendix 2B, the address terminal (
Addressed by the values entered in A-A) and (to...), the interpolation data selection data SD is 0°8;0,
8.1.9. ...;7. 0 and 1, 1, 1 . as processing timing data TD. ...Outputs 1.0.

The latch circuit 17 has a synchronous clock CLK.

It holds the selection data SD and the processing timing data TD in synchronization with the data memory 3 and outputs it to the address terminal (to) of the interpolation data memory 3 and the latch circuit 18.

Interpolation data memory 3 has address terminals (A to A1,)
and the image data D and D of two adjacent pixels input to (A, ~A7) and the address terminal (Ao 1
The interpolation data S is read out from a table of interpolation data stored in advance in accordance with the selection data SD inputted in 0 to A3) and output. That is, image data D(0) and D
(F), the selection data SD is 0 and 8, so l O and 8 are output as the interpolation data S and S, and between the image data D (F) and D (F), the selection data SD is 0 and 8. Since SD is O and 8, F and F are output as interpolated data S and S, and one image data D
Between (F) and D(0), the selection data SD is 1 and 9.
Therefore, 1 and 7 are output as interpolation data S and S, and since selection data SD is 1 and 9 between image data D(0) and D(0), O1! is output as interpolation data S and S! :Outputs O.

The same interpolation data reading as described above is performed for the subsequent image data D, DB, . . . .

In FIG. 5, image data D, D, D, D, D...
The interpolated data S, S, . . . S are represented by X marks, that is, the actual image data D, D, D.

Interpolated data S, S by interpolation method for D, D.

S2 "3"4'"'5"6"7 are created and sequentially sent to the latch circuit 14.

On the other hand, the processing timing data TD sent from the latch circuit 17 is delayed by the time t in the latch circuit 18 (
4), this delay time t is determined by the interpolation data memory 13.
This is the time required for data access in latch circuit 1.
It is necessary to read the interpolated data in step 4. The gate circuit 19 receives processing timing data TD from the latch circuit 18.
It opens and closes when the timing data TD is "L" and closes when the timing data TD is "O". As can be seen from the timing chart in FIG. 4, in the case of enlargement processing, the processing timing data TD indicates that the output of the counter circuit 15 is "0" to "30".
1", 31 is "0"', then "1" continues from 32 to 64, 65 is "O", and further 97 and 127 are O", so the gate circuit is only 110". Close 19.

The gate circuit 19 allows the synchronous clock CLK2 to pass when it is open, cuts off the synchronous clock CLK2 when it is closed, and the output of the gate circuit 19 is input to the latch circuit 14 as a write clock.

In this embodiment, the count value of the counter circuit 15 is 31.
The write clock stops at 65, 97, and 127.

The interpolated data S read from the interpolation memory 13 is sequentially sent out as enlarged image data from the latch circuit 14 to the binarization circuit 23 in response to a write clock.

A main scanning counter 20 counts write clocks from the gate circuit 19, and a sub-scanning counter 21 counts horizontal synchronizing signals. The dither matrix 22 is addressed by the count values of these counters 20, 21 and outputs dither query values.

The z-value conversion circuit 23 compares the enlarged image data sent from the image processing device with a dither threshold value, converts it into a binary value, and outputs it to the recording device 3 as gradation-controlled binary data.

Next, the reduction process will be explained.

FIG. 6 shows a timing chart of signals in each part of the image processing device a in the case of reduction processing, and FIG. 7 shows the relationship between image data and interpolation data necessary for explaining the image reduction processing. . The reduction ratio shown here is 33/8
4 (=0.52).

It is assumed that the gradation levels of the image data D, D, D, D, D are the same as in the case of the enlargement process described above.

The image data of two adjacent pixels (for example, image data D and D) are output from the latch circuits 11 and 12 to the interpolation data memory 13 as address signals, and the set magnification (33764) is input to the interpolation data selection memory 16. The point that the synchronization clock CLK2 is counted by the counter circuit 15 is the same as in the case of two consecutive enlargement processes.

From the interpolation data selection memory 6, from the selection data table stored therein, O9 tree;F, *;E, 0;...Kimoto is obtained as interpolation data selection data SD, and 1. 0,1,0,0.0・
..., 0,0 is output. However, while the tree is invalid data, interpolation data S is read from the interpolation data memory 3. That is, image data D (0) and D (F
), the selection data SD is 0, so only O is output as the interpolation data S, and between the image data D (F) and D (F), the selection data is F. Since it is zero, only F is output as interpolation data S, and between image data D (F) and D (0), since the selected data is a tree and a book, no correction data is output, and the image data Since the selection data between D(0) and D(0) is E and book, only O is output as interpolated data S. The same interpolation data readout as described above is performed for the subsequent image data D, D, . . . . FIG. 7 shows image data D, D, D, D, D,...
is represented by an O mark, and interpolated data S, S, S, ... are represented by an X mark, that is, the actual image data D, D,
D.

D, D, . . . are thinned out by interpolation to create interpolated data S, S, S, . . . and sent to the latch circuit 14.

On the other hand, the processing timing data TD outputted from the interpolation data selection memory 6 is 1,0;1°0;,0;...
;0,0, so the write clock output from the gate circuit 19 is as shown in FIG. The interpolated data S read out from the interpolated data memory 3 is sent to the latch circuit 1 as reduced image data by this write clock.
4 to the binarization circuit 23 in sequence. Reduced image data D, D, D output from the latch circuit 14.

... are thinned out to become interpolated data S, S, S, ....

This interpolated data is compared in magnitude with a dither threshold value by the binarization circuit 23 and outputted to the recording device 3 as binary data. Note that when reducing as described above, image data is output between the original pixels of the original image information, and some of the image data of the original pixels is thinned out or left as is. These output image data are generally referred to as interpolated data.

In the above embodiment, if the magnification of enlargement or reduction is changed, the interpolation data selection data SD output from the interpolation data selection memory 16 changes, and the interpolation data memory 13 is addressed accordingly and outputs the interpolation data S.

In addition, in the above embodiment, the synchronous clock CLK2 generated by the timing generation circuit 10 is changed from the basic synchronous clock because the magnification of enlargement and reduction can be selected from 33/64 to 128/84 in 1/64 increments. The frequency was doubled, but this is determined by the maximum magnification ratio.
For example, if you want to be able to magnify up to 3 times, it is necessary to arbitrarily change the frequency according to the magnification, such as setting the frequency to 3 times that of the basic synchronization clock.

Further, in the above embodiment, the ROM was used as the interpolation data memory 13 and the interpolation data selection memory 16, but instead of this, R
AM may be used, and an arithmetic circuit may be used instead of the interpolation data memory 13.

(Effects of the Invention) As explained above, in the present invention, interpolation data for interpolating image data between pixels of image information is stored, and the interpolation data is read out. is easy to find. In addition, if the embodiment is used, there is no need to change the transfer lock cycle according to the magnification or reduction ratio as in the past, so there is no need for a complicated lock generation circuit, and there is no need to control the exposure amount. It disappears. In other words, since image processing is performed using the same clock when enlarging and reducing images as when using original magnification, the timing of circuit operation is simplified and processing at a specific magnification becomes possible.

Furthermore, since the present invention does not interpolate image data and then sample it with a clock of a different cycle as in the past, there is no need to use a particularly high-speed ROM as an interpolation data memory. Since the enlargement and reduction processing is performed using data obtained by interpolating data, the image quality is improved compared to conventional methods, and high-speed processing is possible.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an image recording device using the image processing device according to the present invention, FIG. 2 is a block diagram of an embodiment of the image processing device according to the present invention, and FIG. 3 is a diagram showing the image processing according to the present invention. ? Time chart of signals in each part of C position, 4th
The figure is a time chart to explain image enlargement, Figure 5 is a part of image data to explain image enlargement, Figure 6 is a time chart to explain image reduction, and Figure 7 is a time chart to explain image reduction. This is part of the image data for explanation. 10...timing generation circuit, 11, 12゜14.1
8.19...Latch circuit, 13...Interpolation data memory, 15...Counter circuit, 16...Interpolation data selection memory, 19...Gate circuit Patent applicant Roku Konishi Photo Industry Co., Ltd. Agent Patent Attorney Hiroshi Suzuki Male Table 113

Claims (4)

[Claims] (1) It has interpolation data output means for outputting interpolation data for interpolating image data between pixels of image information, and interpolation data selection means for outputting an interpolation data selection signal according to set conditions, An image processing apparatus characterized in that interpolation data is read out from the interpolation data output means based on an interpolation data selection signal. (2) The reading of the interpolation data is based not only on the interpolation data selection signal but also on the image data of one or more adjacent pixels of the read image information and the interpolation data. The image processing device according to scope 1. (3) The image processing device according to claim 1, wherein the interpolation data selection means includes a processing timing. (4) The image processing device according to any one of claims 1 to 3, wherein the condition is a magnification.