JPS6354868A - Picture processor using processing clock corresponding to maximum magnification - Google Patents

Abstract

PURPOSE:To simplify the constitution of a circuit, a processing timing being not varied even when the magnification is varied by making a processing clock at a maximum magnification, N-times be a frequency of larger than the N-times of the synchronous clock of a picture signal. CONSTITUTION:Because an inside processing clock is made to be the clock CLK2 of the two times frequency of a transfer clock (synchronous clock) CLK1, a timing at a whole circuit does not vary even when the magnification varies within the extent of two times. Therefore, in the case of N-times of the magnification, it is enough for the clock of the frequency larger than N-times of the synchronous clock to be the processing clock. The clock CLK2 is used for an input to a counter 406. In this case, because the pitch of the magnification is one sixtyfourth, the data of a data selection ROM 405 come the repeat of the sixtyfour. Then, because the processing clock is made to be the two-times of the synchronous clock on the basis of a consideration that the magnification is up to two-times, the data increase in the case of enlarging, and the data are thinned out in the case of minifying.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus in which processing timing does not change even if the magnification is changed.

[Background of the invention]

2. Description of the Related Art Japanese Patent Laid-Open No. 146358/1983 has been proposed as an image processing apparatus for enlarging/reducing image data.

This is designed to perform enlargement or reduction processing by changing successive clocks (that is, transfer locks) from an image reading element such as a CCD according to the magnification.

For example, if the time it takes for a laser printer as a recording device to perform one scan is Tw, and the number of pixels present during scanning is N, then the transfer lock frequency fo of the printer is fo = N77w Similarly, transfer from a CCD If the lock is f, then f
= N/T where T is the period during which the CCD performs one scan.

Here, f>fo...Reduction f<fo...enlarge becomes.

However, in this method, in order to change the transfer lock, it is necessary to control the exposure amount of the CCD used, and the circuit tends to be complicated. Furthermore, the circuit for changing the frequency of the transfer lock is complicated, which poses a problem especially when the magnification step is made fine. Furthermore, since this method performs scaling simply by sampling, the image quality after processing is not good.

Therefore, the inventors prepared interpolation data in the ROM in advance for interpolating the data between pixels of the read image information, and combined the read image data with the interpolation data selection data according to the set magnification condition. Based on this, we proposed an interpolation method that reads out the interpolated data and performs scaling processing.

[Purpose of the invention]

An object of the present invention is to simplify the circuit configuration by preventing the processing timing from changing even if the magnification is changed when performing scaling processing using such an interpolation method.

[Structure of the invention]

For this reason, in the present invention, the processing clock at the maximum magnification N times is set to a frequency that is N times or more higher than the synchronization clock of the image signal.

〔Example〕 The present invention will be explained in detail below.

(1) Basic configuration of the three image processing devices FIG. 1 shows a block diagram of the image processing device.

1 is an image reading device that performs enlargement/reduction processing on document information according to a specified magnification and outputs the result; 2 is a laser printer and LED that performs recording using binary data obtained by the image reading device 1;
It is a recording device such as a printer.

The image reading device 1 includes a document reading section 3 and an enlargement/reduction circuit 4.
is built-in. The document reading unit 3 reads the document using a photoelectric conversion element such as a CCD and converts it into an electrical signal.
After A/D conversion and shading correction, etc., the image data is output as original image data. The enlargement/reduction circuit 4 performs an enlargement/reduction process on the original image data from the document reading section 3 in accordance with a magnification set from the outside in synchronization with a timing signal. The converted image data, which has been enlarged or reduced, is then stored in two formats according to the recording device 2 at the subsequent stage.
Converted to value data.

(2), Original reading section The configuration is shown in FIG. A document is read by a CCD 300, amplified to a predetermined level by an amplifier 301, and then input to an A/D converter 302. This A/D converter 3
At step 02, the input analog signal is converted into a digital signal using the voltage of the reference power supply 303 as a reference.

In this example, 6 bits convert from 0 to 63 levels. A shading correction circuit 304 corrects optical illuminance unevenness in the image signal read by the CCD 300, and corrects the image signal converted into a 6-bit digital signal by the A/D converter 302. Thereafter, this shading-corrected image data is used as original image data D.
Call it a. This original image data Da is sent to the enlargement/reduction circuit 4. The above processing timing is performed by a signal from the synchronization control circuit 305. This synchronous control circuit 305 operates based on a signal from a crystal oscillator 306.

FIG. 3 is a timing chart showing timing signals generated in this synchronization control circuit 305. CLKI is an image transfer lock and serves as a clock for the A/D converter 302, shading correction circuit 304, and others. Also,
The horizontal synchronization signal 1 (
-3YNC occurs. This signal H-5YNC is a CCD
It is also a read start shift pulse SH. φ1 and φ2 are signals having a period twice that of the image transfer lock CLKI and different in phase, and are clocks for shifting the analog shift registers of the odd and even parts of the CCD, respectively. C.C.
In the read image data signal VIDEO from D300, the first image data is read out from the output of the shift pulse SH, and then the second, third, and so on, 5000 bits are read out, but the first to fourth bits are the dummy data of the CCD. The main scanning valid signal H-VALID becomes active only in the 5th to 4756th section and is extracted. Signal R3 is a pulse that resets the shift register of CCD 300' for each shift and occurs at the trailing edge of the image data. MWE is a shading start signal, which is generated in the section of the signal II-VALID of the first line that becomes active immediately after image reading starts. The timing of the sub-scanning direction is determined by the sub-scanning effective signal V-V during the document reading period.
ALID becomes active.

(3) Shading correction The principle of shading correction is shown in FIG. In a bag, in which an image is read by irradiating a lamp onto an original and condensing the reflected light with a lens, a non-uniform optical image called shading is obtained due to optical problems with the lamp, lens, etc. In FIG. 4, when the image data in the main scanning direction is Vl, V2, . . . Vn, the level is decreasing at both ends in the main scanning direction. Therefore,
In order to correct this, the shading correction circuit 304
The following processing is performed. In FIG. 4, VR is the maximum value of the image level, and vl is the 1st bit image level when reading the white color of a white board with uniform density as a reference (not shown). If the image level when the image is actually read is dl, then the tone level of the corrected image is d1'
becomes as follows.

di' = dlx VR/Vl Correction is performed for each bit so that this correction formula holds true.

FIG. 5 shows the internal configuration of the shading correction circuit 304. 3042 is a shading amount storage RAM for reading one line of a signal corresponding to a white board, and 3041 is a shading correction ROM that corrects an image signal based on the information stored in the shading amount storage RAM 3042 when reading an image.

When performing shading correction, first, the read image data for one line of the white plate is stored in the shading amount storage RAM 3.
042. At this time, the shading start signal MWE and address signal AD are sent from the synchronization control circuit 305.
R, the image transfer block CLKI is input, and the signal MWE and tough block CLKI are input to the Nantes gate 30.
43 to the write enable terminal W of the shading amount storage RAM 3042, and the read image data is stored at the address specified by the address signal ADR.

Next, when reading the original, the A/D converted image data is transferred to the address terminal AO of the shading correction ROM 3041.
-Enter in A5. Also, the shading century [RAM
The shading data stored in the terminals 3042 and 3042 are respectively controlled by the address signal ADR and sent to the terminals 11 and 11.
01-l106 to shading correction ROM304
1 to terminals A6 to All. Pre-calculated data is written in the shading correction ROM 3041 so that calculations using the above correction formula can be performed.

As a result of the above, using the read image data and shading data as address signals, the shading correction ROM 30
41 is accessed, and shading-corrected original image data Da is obtained from output terminals 01 to 06.

(4) Principle of Enlargement/Reduction The principle of enlargement/reduction is as shown in FIG. 6, for example, when enlarging (sampling at a magnification of 124/64). That is, although this FIG. 6 shows the sampling timing, the step width of the sampling timing is set to 64/124 (=0.51613), and by comparing the positions of adjacent pixel data of the original image data,
Selection data for selecting predetermined interpolation data is obtained, thereby obtaining interpolation data, which is used as converted image data. In this example, the original image data is
, D2. D3. D4, and each gradation level is 0.
F, F, O, O. The unit distance between each original image data is 1. Therefore, the selected data is normalized according to the sampling position, and becomes o, ooooo→0 (So) 0.51613-8 (Sl) 1.03226→O(S2) 1.54839→8 (S3). The left side is the sampling position. The number in parentheses on the right side indicates the sampling order, and the symbol on the left side indicates the selected data. The interpolation data obtained by this selection data, that is, the converted image data is 0 (So) in the example of FIG.
, 8(Sl), F(S2>, F(S3)...) The symbol to the left of the parentheses is the converted image data.

On the other hand, in reduction (sampling at a magnification of 33/64),
Proceed as shown in FIG. Step width is 64/33
(=1.93939). Each original image data is the same as in FIG. In this case, the original image data is thinned out, and the number of obtained converted image data is reduced. The selection data in this case is normalized and becomes o, ooooo → 0 (So) 1.93939 → F (Sl) 3.87879 → E (S2), and the converted image data is 0 (So), F (Sl) ,0
(S2)...

(5) Enlargement/reduction circuit In the following explanation, it is assumed that the input original image data Da is 4 bits, and the magnification is 0.5 to 2.0 in 1.5% increments, and as an approximation of 1.5%, Use.

In principle, the circuit is configured to perform the same operation as if the sampling period had changed; when enlarging, the converted image data increases more than the original image data, and when reducing, the original image data is thinned out. The number of converted image data decreases.

The enlargement/reduction of the original image in the main scanning direction is electrically performed using the enlargement/reduction circuit 4, and the enlargement/reduction in the sub-scanning direction is performed by changing the moving speed of the sub-scanning while keeping the exposure time of the CCD 300 constant. Let's do it.

In other words, if the sub-scanning speed is slowed down, the image will be enlarged, and if it is made faster, it will be reduced.

The timing generation circuit 400 receives a clock CLK which is a timing signal from the synchronization control circuit 305 of the document reading section 3.
I, horizontal synchronization signal H-SYNC1 main scanning direction valid signal H
-VALID, a timing signal for the entire circuit is generated based on the sub-scanning direction valid signal V-VALID. In that signal, there is a clock C with twice the frequency of the clock CLKI.
There is also LK2.

The input 4-bit original image data Da is shifted by latches 401 and 402 that receive CIJI, and is obtained as Dal and Da2 shifted by one pixel. This becomes the address signal of the interpolation ROM 403 stored as . Attachment 1 shows part of the table contents of interpolated data, and is actually written in the ROM 403 in the form of Attachment 2, in which interpolated data Db obtained by linear interpolation between two points is stored. The addresses of this interpolation ROM 403 are terminals A4 to A7. Original image data Dal of each of the two points input to A8 to All.

Da2 and selection data SD (input to terminals AO to A3) indicating which linearly interpolated position is to be output are given. And interpolation RO? I 403 outputs 4-bit interpolation data Db stored in advance to latch 404 when addresses from these three parties are given.

On the other hand, the data selection table 405 includes a magnification set externally and a clock CL from the timing generation circuit 400.
It is addressed by the count value of a count circuit 406 that counts K2, and outputs a selection data signal SD and a processing timing signal TD during enlargement/reduction from the table. The processing timing signal TD is synchronized with the clock CL by 2 in the latches 407 and 408, and then input to the gate circuit 409, which controls whether the clock CLK2 is passed or blocked. The clock controlled by the gate circuit 409 becomes a write clock CLK3, which will be described later.

124/64 (enlarged) in attached table-3, 33/ in attached table-4
Part of the contents of the data selection table 405 in the case of 64 (reduction) is shown. In these, among the 8 bits of output data, the upper 4 bits are the data that becomes the above-mentioned selection data SD of the interpolation ROM 403, and the lower 4 bits (
In this case, only 0 and 1) is processing timing data TD for controlling whether 'IJ' or 'OJ' outputs the write clock CLK3. Figure 9(a),
(b) shows a timing chart for 124/64 (enlarged) and 33/64 (reduced).

The image data Db converted during enlargement (124/64) is shown in Appendix-5. At the time of the converted image data 5o-S9, the write clock CLK3 is outputted and sent to the binarization circuit 410 at the subsequent stage.

On the other hand, in the case of reduction (33/64), since some data is thinned out, the converted image data Db is output as shown in Table 6. Here, when the converted image data is invalid data or thinned-out data, the write clock CLK3 is not output. Invalid data is the circuit reference clock CLK2.
data that is output during reduction because it is set to twice the reference clock CLKI, and thinned data is data that is output at a timing when converted image data Db is not created from original image data Da during reduction.

The converted image data Db obtained by the enlargement/reduction processing as described above is sent to the subsequent binarization circuit 410 in synchronization with the write clock, and is compared with the threshold value of the dither ROM 411 containing the and output to the recording device 2 as binary data. The dither ROM 411 is a sub-scanning counter 41 that counts the horizontal synchronization signal H-5YNC.
2 and the count value of the main scanning counter 413 that counts the write clock CLK3.

(6)0 Key points of the present invention As mentioned above, the internal processing clock can be transferred and locked (
Since the clock CLK2 has twice the frequency of CLKI ("synchronous clock"), the timing of the entire circuit will not change even if the magnification changes within 2 times. Therefore, at the maximum magnification N times, the synchronization A clock with a frequency N times or more higher than the clock may be used as the processing clock.

In this embodiment, the above clock CLK2 is used as an input to the counter 406 in FIG. In this embodiment, since the magnification step is 1764, the data selection ROM 405
The data is 64 repetitions. Since the processing clock is set to twice the synchronization clock considering the magnification up to 2x, as mentioned above, in the case of enlargement, the data increases,
As mentioned above, in the case of reduction, data will be thinned out, and the data selection ROM will have 128 repetitions.

FIG. 10 shows an explanatory diagram that further simplifies the output state of scaled data. (a) is the same size and is output at a ratio of 1:1, so there is no increase or decrease in the number of data.

The first part of the input data is output during one cycle of the synchronous clock, and the second part becomes invalid data.

('b) is an example of enlargement, and depending on the magnification, two pieces of data are output during one cycle of the synchronous clock. Furthermore, at a timing when data does not increase, the rear part becomes invalid data.

(C1 is an example of reduction, and the timing at which data is thinned out during one cycle of the synchronization clock occurs depending on the magnification.

(6) Summary of the Embodiment As described above, in this embodiment, the overall magnification does not change depending on the specified magnification, so the circuit configuration is simplified. In addition, although this embodiment has been described in the main scanning direction (one-dimensional), it may also be carried out in a two-dimensional direction including the sub-scanning direction.Also, in this embodiment, the circuit is configured using a ROM table. This makes it easy to determine the timing of the operation. Furthermore, since the data selection ROM has information on the magnification, it is possible to set a specific magnification. Furthermore, since the system does not interpolate the image data and then sample it with a clock of a different cycle, there is no need to prepare a particularly high-speed ROM for the interpolation ROM, etc.
For example, in the case of performing enlargement processing up to 2 times, a speed twice as fast as the image reading lock is sufficient. Furthermore, in this embodiment, since the image data is scaled up and down using completely interpolated data, the image quality is good and high-speed processing is possible.

〔Effect of the invention〕

As described above, according to the present invention, since the processing clock at the maximum magnification N times is set to a frequency N times or more of the synchronization clock of the image signal, the overall processing timing does not go out of order, and the circuit configuration is simplified.

-Norito Nito [Part 1] (Example of the contents of the interpolation table) Attachment-1 [Part 2] -W Jinji [Part 3] Ichibetsul Nito [Part 4] 4CF11. bUOUUC4υl'lZ,4;('IF
)υshi4? , l'1.3. J'151]υIJ41'?
14. , jlZ5LIWADR5+O+1 +2 +
3 ↓4 +5 ↓6 +7 +8 +9 +
A +B +C40+E +F adjacent original image data Annex-3 (+24/64 data selection R content) - Separate sunye (33/64 data selection ROM content) Annex-5 Annex-6

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the image processing device, Fig. 2 is an internal block diagram of the document reading device, Fig. 3 (al, (bl) is a timing chart of document reading, and Fig. 4 is a diagram showing the principle of shading correction. 5 is a detailed diagram of the shading correction circuit, FIG. 6 is an explanatory diagram of sampling in the case of enlargement magnification, FIG. 7 is an explanatory diagram of sampling in the case of reduction magnification,
Figure 8 is a circuit diagram of the enlargement/reduction circuit, Figure 9 (al, (b)
is a timing chart of enlargement and reduction, Fig. 10(a) ~
(C1 is an explanatory diagram of enlargement/reduction. Agent Patent Attorney Tsuneaki Nagao 1 Figure 3 (a) -V/ILID □■ ADRCLKI OutE Figure 9 (a) 1214/64 Hawaii 22 ( b) 33/S gradient 11 Queen 2, 1゛Figure 10 t:,,,,l E3 procedure amendment form, 1. Indication of the case 1986 Patent Office No. 094427 2. Title of the invention Maximum Image processing device 3 using processing clock according to magnification
, Relationship with the case of the person making the amendment Patent applicant address: 1-26-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo
Name (127) Konishiroku Photo Industry Co., Ltd. 4, Agent address 4-12-1, Ginza, Chuo-ku, Tokyo 8104
No. Mizuho Daiichi Building 3rd floor 203-545-81506
, Number of inventions increased by amendment None 7. Subject of amendment Description

Claims (1)

[Claims] (1) In an image processing device that performs scaling processing at a predetermined magnification on document image information obtained using a photoelectric conversion element, the processing clock at the maximum magnification N times is set to a frequency N times or more of the synchronization clock of the image signal. An image processing device characterized by: