JPS62252264A - Picture reader whose part to obtain timing signal is improved - Google Patents

Abstract

PURPOSE:To simplify the whole of circuit constitution, and to easily attain synchronization between a picture signal and a magnifying and reducing circuit, by making into common use a timing generating means which generates the operation timing signal of a photoelectric transducer, and the timing generating means which generates a timing signal for an enlarging and reducing process. CONSTITUTION:In a picture reader 1 equipped with an enlarging and reducing function, a counter which generates the operation timing of a CCD300, and the counter which generates various kinds of timing in a magnifying and reducing circuit 4, are used in common. At the timing generation circuit, various kinds of timing signals are generated, and those timing signals are sent to a circuit in the inside of a document reader 3, or a timing generation circuit 400 other than the enlarging and reducing circuit 4. The signal is outputted to the data selection ROM405 of the enlarging and reducing circuit 4 through an address bus AB, but seven bits of low-order of the signal are inputted to address terminals A0-A6 of the data selection ROM405. Since the timing of the CCD300, and that of the enlarging and reducing circuit 4, are related organically, a control signal for them is generated from the output of a common counter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device that has been improved in a portion for obtaining a timing signal.

[Background of the invention]

In a conventional image reading device of this kind, a counter provides a signal to the CCD to determine the operation (scanning) timing of the CCO as a photoelectric conversion element for image reading, and also provides a synchronization clock (image transfer lock) for the image signal. This operates a counter for the timing of enlargement/reduction processing. In other words, multiple counters are provided.

As a result, the circuit configuration becomes complicated, and it becomes necessary to synchronize each counter.Furthermore, when the synchronization of each counter is shifted due to noise or the like, there is a problem in that the processed image is likely to deteriorate.

[Purpose of the invention]

An object of the present invention is to simplify the overall circuit configuration, and
The purpose is to make it easier to synchronize the image signal and the enlargement/reduction circuit.

[Structure of the invention]

For this purpose, in the present invention, in an image reading device that performs enlargement/reduction processing on image information of a document obtained using a photoelectric conversion element according to a specified magnification and outputs the image information, a timing signal is generated to generate an operation timing signal of the photoelectric conversion element. The means and the timing generating means for generating the timing signal for the scaling process are made common.

〔Example〕

The present invention will be explained in detail below.

(1) Basic configuration of 0 image reading device FIG. 1 shows a block diagram of the image reading device.

1 is an image reading device that performs enlargement/reduction processing on document information according to a specified magnification and outputs the result; 2 is a laser printer and LED that performs recording using binary data obtained by the image reading device 1;
It is a recording device such as a printer.

The image reading device 1 includes a document reading section 3 and an enlargement/reduction circuit 4.
is built-in. The document reading unit 3 reads the document using a photoelectric conversion element such as a CCD, converts it into an electrical signal, and converts the document into an electrical signal.
/D conversion and shading correction, etc., and then output as original image data. The enlargement/reduction circuit 4 performs an enlargement/reduction process on the original image data from the document reading section 3 in accordance with a magnification set from an external operation key (not shown) in synchronization with a timing signal. and,
This enlarged or reduced converted image data is converted into binary data in accordance with the recording device 2 at the subsequent stage.

(2), Original reading section The configuration is shown in FIG. A document is read by a CCD 300, amplified to a predetermined level by an amplifier 301, and then input to an A/D converter 302. This A/D converter 3
At step 02, the input analog signal is converted into a digital signal using the voltage of the reference power supply 303 as a reference.

In this example, 6 bits convert from 0 to 63 levels. A shading correction circuit 304 corrects optical illuminance unevenness in the image signal read by the CCD 300, and corrects the image signal converted into a 6-bit digital signal by the A/D converter 302. Hereinafter, this shading-corrected image data will be referred to as original image data Roa, and this original image data Da is sent to the enlargement/reduction circuit 4. The above processing timing is performed by a signal from the synchronization control circuit 305. This synchronous control circuit 305 operates based on a signal from a crystal oscillator 306.

FIG. 3 is a timing chart showing part of the timing signals generated by this synchronization control circuit 305. CLKI
is an image transfer lock (synchronization clock), which serves as a clock for the A/D converter 302, the shading correction circuit 304, and others. Further, by counting this clock CLKI, a horizontal synchronizing signal H-5YNC is generated. This signal +1-5YNC is the CC readout start shift pulse Sl (also φl, φ2 is the image transfer lock CLKI 17
These are signals with twice the period and different phases, and each CCD
This is a clock for shifting the odd and even parts of the analog shift register. In the read image data signal VIDEO from the CCD 300, the first image data is read out from the output of the shift pulse S11, and then the second, third, and so on are sequentially read out.
..., 5000 bits are read out, but the first to fourth are CCD dummy pixels, and the fifth to 475 bits are read out.
The main scanning valid signal II-VALID becomes active only in the sixth section and is taken out. Signal R5 is CCD30
A pulse that resets the zero shift register after each shift, occurring at the trailing edge of image data. MWE is a shading start signal, which is generated in the section of the signal II-VALID of the first line that becomes active immediately after image reading starts.

Regarding the timing in the sub-scanning direction, the sub-scanning valid signal V-VALID becomes active during the document reading section.

(3) Shading correction The principle of shading correction is shown in FIG. In an apparatus that reads an image by irradiating a lamp onto a document and condensing the reflected light with a lens, an uneven optical image called shading is obtained due to optical problems with the lamp, lens, and the like. In FIG. 4, when the image data in the main scanning direction is Vl, V2, . . . Vn, the level is decreasing at both ends in the main scanning direction. Therefore,
In order to correct this, the shading correction circuit 304
The following processing is performed. In FIG. 4, VR is the maximum value of the image level, and vl is the 1st bit image level when reading the white color of a white board with uniform density as a reference (not shown). If the image level when the image is actually read is di, then the tone level of the corrected image dl'
becomes as follows.

di' = dlX Vl? /Vl Correction is performed for each bit so that this correction formula holds true.

FIG. 5 shows the internal configuration of the shading correction circuit 304. 3042 is a shading amount storage RAM for reading one line of a signal corresponding to a white board, and 3041 is a shading correction ROM that corrects an image signal based on the information stored in the shading amount storage RAM 3042 when reading an image.

When performing shading correction, first, the read image data for one line of the white plate is stored in the shading amount storage RAM 3.
042. At this time, the shading start signal MWE and address signal AD are sent from the synchronization control circuit 305.
R, image transfer terminal lock CLKI is input, and among them, the signal MWE and block lock CLKI are input to the Nant gate 30.
43 to the write enable terminal W of the shading amount storage RAM 3042, and the read image data is stored at the address specified by the address signal ADR.

Next, when reading the original, the A/D converted image data is transferred to the address terminal AO of the shading correction ROM 3041.
-Enter in A5. In addition, shading amount storage RAM
The shading data stored in 3042 is controlled by the address signal ADR, and the shading data stored in
Shading correction ROM3041 from 01 to l106
Output to the terminals 6 to All. Shading correction R
Pre-calculated data is written in the OM 3041 so that calculations using the above correction formula can be performed.

As a result of the above, using the read image data and shading data as address signals, the shading correction ROM 30
41 is accessed, and shading-corrected original image data Da is obtained from output terminals 01 to 06.

(4) Principle of Enlargement/Reduction The principle of enlargement/reduction is as shown in FIG. 6, for example, when enlarging (sampling at a magnification of 124/64). That is, although this FIG. 6 shows the sampling timing, the step width of the sampling timing is set to 64/124 (=0.51613), and by comparing the positions of adjacent pixel data of the original image data,
Selection data for selecting predetermined interpolation data is obtained, thereby obtaining interpolation data, which is used as converted image data. In this example, the original image data is DO, DI
, D2. D3. D4, and each gradation level is 0.
F, F, 0. It was set as O. The unit distance between each original image data is 1. Therefore, the selected data is normalized according to the sampling position and becomes 0.00000-0 (So) 0.51613-8 (Sl) 1.03226-0 (S2) 1.54839→8 (S3). The left side is the sampling position. The number in parentheses on the right side indicates the sampling order, and the symbol on the left side indicates the selected data. The interpolated data obtained by this selection data, that is, the converted image data is 0 (So) in the example of FIG.
, 8(St), F(S2), F(S3), and so on. The symbol to the left of the parentheses is the converted image data.

On the other hand, in reduction (sampling at a magnification of 33/64),
Proceed as shown in FIG. Step width is 64/33
(=1.93939). Each original image data is the same as in FIG. In this case, the original image data is thinned out, and the number of obtained converted image data is reduced. The selection data in this case is normalized and becomes o, ooooo → O (So) 1 , 93939 → F (Sl) 3.87879- E (S2), and the converted image data is 0 (SO), F (Sl) ,
O(52)...

(5) Enlarging/reducing circuit In the following explanation, it is assumed that the input original image data row a is 4 bits, the magnification is 0.5 to 2.0 in 165% increments, and ×764 is used as an approximation of 1.5%. .

In principle, the circuit is configured to perform the same operation as if the sampling period had changed; when enlarging, the converted image data increases more than the original image data, and when reducing, the original image data is thinned out. The number of converted image data decreases.

The enlargement/reduction of the original image in the main scanning direction is electrically performed using the enlargement/reduction circuit 4, and the enlargement/reduction in the sub-scanning direction is performed by changing the moving speed of the sub-scanning while keeping the exposure time of the CCD 300 constant. Let's do it.

In other words, if the sub-scanning speed is slowed down, the image will be enlarged, and if it is made faster, it will be reduced.

The timing generation circuit 400 generates a clock CL which is a timing signal from the synchronization control circuit 305 of the document reading section 3.
, horizontal synchronization signal ll-5YNC1 main scanning direction valid signal H
-VALID, a timing signal for the entire circuit is generated based on the sub-scanning direction valid signal V-VALID. Among them, a clock CL with a frequency twice 1 is added to the clock CL.
K2 is also included.

The input 4-bit original image data Da is shifted by latches 401 and 402 that receive the clock CLKI, resulting in Dal and Da2 shifted by one pixel.
The interpolation data between two points is obtained as an address signal of the interpolation ROM 403 in which the above-mentioned interpolation data between two points is stored in advance as a table. Attachment 1 shows a part of the table contents of interpolation data, and in reality it is as shown in Attachment 2.
03, and interpolation data ob obtained by linear interpolation between two points is stored. The addresses of this interpolation ROM 403 are terminals A4 to A7. Original image data Dal of each of the two points input to A8 to All.

Da2 and selection data SD (manually input to terminals AO to A3) as to which position interpolated by a straight line should be output are given. When the interpolation ROM 403 receives the addresses from these three sources, it outputs the 4-bit interpolation data Db stored in advance to the latch 404.

On the other hand, the data selection ROM 405 is addressed by an externally set magnification and an address signal AB from the synchronization control circuit 3.5 shown in FIG. outputs the processing timing signal TO at the time. This address signal AB corresponds to a repetition period (128). Processing timing signal TD
are synchronized with the clock CLK2 by latches 407 and 408, and then input to the gate circuit 409, which controls whether the clock CLK2 is passed or blocked. The clock controlled by the gate circuit 409 becomes a write clock CLK3, which will be described later.

124/64 (enlarged) in attached table-3, 33/ in attached table-4
64 (reduction), the contents of a part of the table of the data selection ROM 405 are shown. In these cases, among the 8 bits of output data, the upper 4 bits are the data that becomes the above-mentioned selection data S of the interpolation ROM 405, and the lower 4 bits (only 0.1 in this case) are "1" to output the write clock CLK3. , is processing timing data TD for controlling whether it is "0" or not. Figure 9(a), (
Timing charts for 124/64 (enlarged) and 33/64 (reduced) are shown in bl.

0 image data Db converted during enlargement (124/64)
is shown in Attached Table-5. When the converted image data So-59 is converted, the write clock CLK3 is outputted and sent to the binarization circuit 410 at the subsequent stage.

On the other hand, in the case of reduction (33/64), since some data is thinned out, the converted image data Db is output as shown in Table 6. Here, when the converted image data is invalid data or thinned-out data, the write clock CLK3 is not output. Invalid data is the circuit reference clock CLK2.
is set to twice the reference clock CLKI, so that data is output during reduction, and thinned data is data that is output at a timing when converted image data B is not created from original image data Da during reduction.

The converted image data Db obtained by the enlargement/reduction processing as described above is sent to the subsequent binarization circuit 410 in synchronization with the write clock, and is stored in the dither ROM 4.
11 and output to the recording device 2 as binary data. Dither ROM411 has horizontal synchronization signal H-5
It is addressed by the count values of the sub-scanning counter 412 that counts YNC and the main-scanning counter 413 that counts the write clock CLK3.

(6) 9 Main Parts of the Present Invention By the way, in the image reading device 1 having the enlargement/reduction function as described above, the counter that makes the operation timing of the CCD 300 and the counter that makes the various timings of the enlargement/reduction circuit 4 are common. It is desirable that there be one from the viewpoint of simplifying the overall circuit configuration and making it easier to synchronize the two.

Therefore, in this embodiment, the synchronous control circuit 30 shown in FIG.
As shown in FIG. The data is sent to the data selection ROM 405 in the enlargement/reduction circuit 4. The address of this counter is twice the ADH signal shown in FIG. 3+8).

In this timing generation circuit 3052, as shown in FIG. 3(a),
(It generates various timing signals shown in bl and sends the signals to the internal circuit of the document reading section 3 and another timing generation circuit 400 of the enlargement/reduction circuit 4. , are output via address bus AB, of which the lower seven bits are input to address terminals AO-A6 of data selection ROM 405.

Since the timing of the CCD 300 and the timing of the enlargement/reduction circuit 4 are organically related, generating these control signals from the output of the common counter 3051 is as follows.
Reasonable.

(7) Summary of the Embodiment As described above, in this embodiment, the enlargement/reduction circuit 4 is configured using a ROM, so the timing of the operation can be easily determined, and information on the magnification can be stored in the data selection ROM 405.
Since the magnification is contained within, it is possible to set even a specific magnification. In addition, in this embodiment, since the original image data is not interpolated and then sampled with a clock of a different cycle, even in an interpolation ROM etc., a particularly high-speed RO
There is no need to use M. Furthermore, since the scaling process is performed using data that is completely interpolated from the original image data, the image quality is good and high-speed processing is possible.

In addition, since the counter CCD which generates the timing and the counter used for scaling are made common, the overall circuit configuration is simplified and it is very easy to synchronize the timings of both.

〔Effect of the invention〕

As described above, according to the present invention, since the timing generation means for generating the operation timing signal of the photoelectric conversion element and the timing generation means for generating the timing signal for the scaling process are made common, the overall circuit configuration is simplified, and the image signal This makes it easier to synchronize with the enlargement/reduction circuit.

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[Brief explanation of drawings]

Figure 1 is a diagram showing the basic configuration of the image reading device, Figure 2 is an internal block diagram of the document reading device, Figures 3 (a) and (b) are timing charts for document reading, and Figure 4 is a shading correction diagram. An explanatory diagram of the principle, Fig. 5 is a detailed diagram of the shading correction circuit, Fig. 6 is an explanatory diagram of sampling in case of enlargement magnification, Fig. 7 is an explanatory diagram of sampling in case of reduction magnification,
Figure 8 is a circuit diagram of the enlargement/reduction circuit, Figure 9 (al, (bl)
10 is a timing chart for enlargement and reduction, and FIG. 10 is a circuit diagram of a timing generating means portion showing an embodiment of the present invention. Agent Patent Attorney Tsuneaki Nagao ADRαJ<IMWE Figure 9 (a) β% mini ±f ΣHowever, it stands Figure 10 1 Book Procedural Amendment (Form) 1. Indication of the case 1985 Patent Application No. 094421 2, Name of the invention Image reading device 3 improved with respect to the part for obtaining timing signals, Person making the amendment Relationship to the case Patent applicant Address 1-chome Nishi-Shinjuku, Shinjuku-ku, Tokyo 26 number 2 name
Name (127) Konishiroku Photo Industry Co., Ltd. 4, Agent

Claims (2)

[Claims] (1) In an image reading device that performs enlargement/reduction processing according to a specified magnification on image information of a document obtained using a photoelectric conversion element and outputs the image information, the timing generation means for generating an operation timing signal of the photoelectric conversion element; An image reading device characterized in that a timing generating means for generating a timing signal for enlargement/reduction processing is shared. (2) The image reading device according to claim 1, wherein the timing generating means comprises a counter.