JPS6123893Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to a binarization shaping device that converts a facsimile analog signal into a binary signal and then shapes the waveform by sampling. The structure is such that a good reproduced image can be obtained even if there is a minute positional displacement caused by such factors.

In a facsimile device used for photocopy transmission, etc., the facsimile analog signal obtained by photoelectrically converting the original image to be transmitted is converted into a binary signal consisting of a white level and a black level, and then the waveform is shaped by sampling using clock pulses. It is being done. However, if there is minute positional displacement due to jitter, level fluctuation, etc. in the facsimile analog signal, an undesirable quantization error will occur during sampling, resulting in distortion in the reproduced image.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology, and next, the facsimile analog signal binarization shaping device of this invention
A description will be given below along with embodiments shown in the drawings.

In FIG. 1, a first binarization circuit 2 and a second binarization circuit 3 are connected to a signal input terminal 1.
are both composed of comparators and have comparison reference voltage input terminals 4 and 5, respectively. A signal output terminal of the first binarization circuit 2 is connected to a first sampling circuit 6, and a signal output terminal of the first sampling circuit 6 is connected to one signal input of an OR circuit 7 consisting of an OR gate circuit. The signal output terminal of the OR circuit 7 is connected to one signal input terminal of an AND circuit 8 consisting of an AND gate circuit.

Further, the signal output terminal of the second binarization circuit 3 is connected to the second sampling circuit 9, and the signal output terminal of the second sampling circuit 9 is connected to the AND circuit 8.
is connected to the other signal input terminal of the AND circuit 8.
The signal output terminal of is connected to the binary signal output terminal 10 and the one-line memory circuit 11, and the signal output terminal of the one-line memory circuit 11 is connected to the other signal input terminal of the OR circuit 7. and,
Each synchronizing signal input terminal of the first and second sampling circuits 6 and 9 and the one-line memory circuit 11 is connected to the terminal 12.

The signal input terminal 1 is connected to A in FIG.
One line of facsimile analog signals as shown in B and C are sequentially applied. However, these analog signals are obtained by line-scanning the transmission original image with a light beam and photoelectrically converting it, and each contains some jitter. In addition,
A in FIG. 2 shows the analog signal obtained by the first line scan, B and C in FIG.
Analog signals obtained by the third line scan are shown respectively.

When such a facsimile analog signal is applied to the signal input terminal 1 as a time series, the first
The second binarization circuits 2 and 3 convert the analog signal into two types of binary signals consisting of a white level and a black level based on different comparison reference voltages applied to respective comparison reference voltage input terminals 4 and 5. Convert each to a value signal. Now, let P 1 be the first comparison reference voltage set in the first binarization circuit 2, and P ₂ be the second comparison reference voltage set in the second binarization circuit 3 (however, _{P 1} >P ₂ ), and the facsimile analog signals shown in A, B, and C in FIG. 2 are sequentially applied to the signal input terminal 1. From the first binarization circuit 2, , E, F, and the binary signals indicated by D ₁ , E ₁ , F ₁ are taken out and sent to the second binarization circuit 3.
From this, binary signals shown as D ₂ , E ₂ , and F ₂ at D, E, and F in FIG. 2 are taken out.

Furthermore, the first and second sampling circuits 6 and 9
Since the clock pulse shown at G in FIG. 2 is applied to each synchronizing signal input terminal of the 1-line memory circuit 11 through the terminal 12, the clock pulse shown at G in FIG. _H1 ,
Signals indicated by I ₁ and J ₁ are taken out, and these signals are applied to one signal input terminal of the AND circuit 8 through the OR circuit 7 . Further, from the second sampling 9, signals shown as H _, I, _and J in FIG. ₂ are taken out, and these signals are sent to the AND circuit 8.
is applied to the other signal input terminal of. Then, by the AND operation of the AND circuit 8, a binarized shaped signal is formed by shaping the analog signal, and the binarized shaped signal output from the AND circuit 8 is output as a binarized signal for each line. terminals 10 and 1
The input signal is applied to the line memory circuit 11, and the memory circuit 11 converts the input binary shaped signal of each line into 1
Output with line delay.

That is, when the first line scan is completed, the first line binary shaped signal shown at K in FIG. 2 is stored in the one line memory circuit 11, and this signal is delayed by one line period. Then, it is read out during the second line scan.

Therefore, one of the signal input terminals of the OR circuit 7 during the second line scan is connected to I in FIG.
The signal indicated by I ₁ is applied to the other signal input terminal, and the signal indicated by K in FIG. 2 is applied to the other signal input terminal, and the signal indicated by L in FIG. 2 is taken out from the OR circuit 7. . This signal is the AND circuit 8
Since the signal indicated by I2 in FIG. 2 is applied to the other signal input terminal of the AND circuit 8, the signal indicated by _I2 in FIG. The binarized shaped signal shown is extracted. Since the analog signal of each line is shaped based on the previous binary shaped signal of one line, the analog signal shown in B in FIG. 2 contains jitter, and I in _FIG. Even if the output signal of the sampling circuit 6 shown in is changed in high frequency, the high frequency change in the binary shaped signal at the output terminal 10 is prevented based on the binary shaped signal on the first line, and unnecessary changes due to jitter etc. The binarized shaped signal of the second line is formed while preventing high frequency changes.

Furthermore, when the second line scan is completed, the signal shown in M in FIG. 2 is stored in the 1-line memory circuit 11, so that the signal shown in A signal indicated by F ₁ and a signal indicated by M in FIG. 2 are added to F of . Then, the OR output signal and the signal shown as F2 in FIG. ₂ are applied to the AND circuit 8, and a shaped signal as shown in M in FIG. For the fourth and subsequent line scans, waveform-shaped binary signals are sequentially taken out to the terminal 10 by the same operation as described above.

By the way, the degree of waveform shaping is determined by the difference between the comparison reference voltages set in the first and second binarization circuits 2 and 3, and when this difference is zero, that is, when a single comparison reference voltage Therefore, in the conventional configuration that performs binarization and sampling, unnecessary quantization errors occur, resulting in distortion in the reproduced image.

However, as shown in FIG.
By binarizing the facsimile analog signal of each line by referring to the binarized shaped signal of the previous line output from 1, jitter and level fluctuation occur in the facsimile analog signal of each line and sampling is performed. Even if an unnecessary high frequency change occurs in the sampling results of the circuits 6 and 9 due to the quantization error, the output terminal 10 outputs the unnecessary high frequency change due to the quantization error based on the binarized shaped signal of one line before. A binarized shaped signal of each removed line is output, and a reproduced image without distortion can be obtained based on the binarized shaped signal.

As described above, according to the binarization and shaping device for facsimile analog signals of the present invention, the facsimile analog signal of each line is compared with the first comparison reference voltage to binarize the analog signal. a second binarization circuit that binarizes the analog signal by comparing the analog signal with a second comparison reference voltage; and an output signal of the first binarization circuit. a first sampling circuit that samples in synchronization with a clock pulse; a second sampling circuit that samples an output signal of the second binarization circuit in synchronization with the clock pulse;
a memory circuit that reads out the binary shaped signal of one line before in synchronization with the clock pulse; an OR circuit that calculates the OR of the output signals of the first sampling circuit and the memory circuit; and the OR circuit. and an AND circuit that calculates the logical product of the output signals of the second sampling circuit and outputs the binary shaped signal of each line to the binary signal output terminal and the memory circuit. The facsimile analog signal of each line can be binarized by referring to the binarized shaped signal of the previous line formed by processing, and the facsimile analog signal contains some jitter and level fluctuation. Even if high-frequency changes occur in the output signals of the first and second sampling circuits due to undesirable quantization errors, the quantization errors are output to the binary signal output terminals based on the binary shaped signals of one line before. A binarized shaped signal for each line from which unnecessary high-frequency changes have been removed is output, and a reproduced image with less distortion can be obtained based on this signal.

[Brief explanation of the drawing]

Figure 1 is a block diagram of one embodiment of the facsimile analog signal binarization and shaping device of this invention;
A to M in the figure are signal waveform diagrams at each part in FIG. 1. 1... Signal input terminal, 2... First binarization circuit, 3... Second binarization circuit, 6... First sampling circuit, 7... OR circuit, 8... AND AND Circuit, 9...Second sampling circuit, 10...
Binary signal output terminal, 11...1 line memory circuit.

Claims (1)

[Scope of utility model registration request] Each line of facsimile analog signal is
a first binarization circuit that binarizes the analog signal by comparing it with a comparison reference voltage; and a second binarization circuit that binarizes the analog signal by comparing the analog signal with a second comparison reference voltage. a binarization circuit; a first sampling circuit that samples the output signal of the first binarization circuit in synchronization with a clock pulse;
a second sampling circuit that samples the output signal of the second binarization circuit in synchronization with the clock pulse;
a memory circuit that reads out the binarized shaped signal before the line; an OR circuit that calculates the OR of the output signals of the first sampling circuit and the memory circuit; and the OR circuit and the second sampling circuit. A facsimile analog signal binarization shaping device, comprising an AND circuit that calculates a logical product of output signals and outputs the binarized shaped signal of each line to a binary signal output terminal and the memory circuit. .