JPH027669A - Binarization processing circuit - Google Patents

Abstract

PURPOSE:To attain binarization conversion processing with fidelity by input picture information by outputting a change picture as a black picture element and a white picture element based on edge detection information of a picture signal, binarizing unchanged picture element and selecting the element based on the edge detection information. CONSTITUTION:An edge signal EG is generated from a picture signal S at a differentiation circuit 12 and fed to a signal generating means 1B. The signal generating means 1B is provided with a binarizing means 1C binarizing the unchanged picture element of picture elements and selecting the elements based on the edge detection information. The binarizing means IC consists of the 3rd comparator 19 and a multiplexer 16, and a control signal CTL in response to the edge output formed based on the edge detection signal EG is fed to the multiplexer 16. In the case of a picture element whose level changes from a white to a black level, a black picture element is outputted and in the case of a picture element whose level changes from a black to a white level, a white picture element is outputted, and in the case of the unchanged picture element, a binary signal is outputted. Thus, even if the level of the picture information is of any value, the binarized output signal corresponding to the edge is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is suitable for application to cases where image signals are converted to 211i, such as in facsimile machines.
1i conversion processing circuit.

[Background of the Invention] A facsimile machine optically reads image information of a transported document and converts it into an electrical signal (image signal).
At the same time, a signal processing means is employed which converts this photoelectrically changed image signal into, for example, black and white binary information.

A black and white binary image signal that has undergone such signal processing is transmitted to the other party using a line.

By the way, since the degree of image information of a document to be read varies, there is a considerable difference in density level. If the difference in density of the character portion is large with respect to the background level, converting to a black and white binary signal based on the image signal allows conversion to a black and white binary signal that matches the human image information.

However, in normal cases, there are many originals that do not have much difference in density level, so if the human image signal is simply binarized, it may not be possible to obtain a black and white 21 direct signal that matches the human image information. many.

Therefore, in such a facsimile machine, by using a binarization processing circuit as shown in Fig. 3, the binarization processing is performed based on the edge-enhanced image signal. By converting to a binary signal based on an edge-enhanced image signal such as this, even if the 1 degree difference in human image information is small, it can be converted to a binary signal that matches the input image information. .

Now, FIG. 3 shows an example of the conventional 21Ii conversion processing circuit 1 mentioned above, in which the image signal S is supplied to the terminal 2, and this is the inverting input terminal of the comparator 3 composed of a black and white binary operational amplifier. is supplied to

Further, a predetermined reference voltage is applied to the terminal 4, and the image signal S and this reference voltage are divided by a resistor @5.6, and the resistor 5.6 and the capacitor 7 are configured. A predetermined reference signal REF is supplied to the integrating circuit 8.
is formed.

A reference signal R formed based on such an image signal S
EF is supplied to the non-inverting input terminal of comparator 3 and outputs terminal 2.
Binarization of the image signal S supplied to is executed. Therefore, a binary output corresponding to a black and white image is obtained at the terminal 9.

The level of the reference signal REF differs depending on the magnitude of the time constant of the integrating circuit 8. FIG. 4A is a waveform diagram showing the relationship between the image signal S and the reference signal REF when the time constant of the integrating circuit 8 is increased. Similarly, FIG. 4C shows the relationship between the image signal S and the reference signal REF when the time constant of the integrating circuit 8 is small.

With these, 2
Valued output is obtained.

[Problem to be Solved by the Invention] By the way, when the binarization processing circuit 1 as shown in FIG. 3 is used, since the level of the reference signal REF is lower than the image signal S, When compared, each edge portion of the image signal S is equivalent to an enhanced state. That is, if the reference signal REF is modulated according to the image signal in this way, it is equivalent to comparing it with the edge-enhanced input image signal.

Now, as shown in Figure 4, especially when image information such as a checkered pattern or a vertical stripe pattern is input, the waveform of the output binary signal is determined by the magnitude of the integration time constant. It will change drastically.

In particular, when the integration time constant is increased, a checkerboard-like M
For image information with low TF, signal collapse occurs,
This method has the disadvantage that it is not possible to reliably perform binarization processing according to image information (FIG. 4B).

Furthermore, if the integration time constant is made too small, there is a drawback that a binary output that is faithful to the image cannot be obtained, such as outputting a white signal even in areas that should be processed as black (see Figure 2). D).

Therefore, the present invention proposes a binarization processing circuit that can perform binarization conversion processing more faithfully to input image information.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention includes an image signal edge detection means, and a signal that outputs changed pixels as black pixels and white pixels based on the edge detection information. The generation means and two non-changing pixels
The present invention is characterized by comprising a binarization means for converting the information into values and selecting the values based on the edge detection information.

[Function] The image signal S is converted into an edge signal E in the differentiating circuit 12.
G (FIG. 2D) is formed.

The image signal S is further supplied to signal generating means IB.

This signal generating means IB includes first and second comparators 17
．． 18 and a multiplexer 16. Furthermore, a binarization means IC is provided which binarizes unchanged pixels and selects them based on edge detection information.

The binarization means IC is composed of a third comparator 19 and a multiplexer 16.

The multiplexer 16 has an edge detection signal EG, and a control signal CTL corresponding to the edge output formed based on the signal EG.
(Fig. 2E) is supplied. The control signal CTL is a signal corresponding to a rising edge, a falling edge, and an intermediate level thereof.

In addition to the image signal Sd, the first comparator 17 is supplied with a first reference signal Sa formed by this image signal Sd and a clamp potential, so that a white level signal is always formed. (Figure 2C).

Similarly, the second comparator 18 is supplied with a second reference signal Sc formed based on the image signal Sd and the shading signal in addition to the image signal Sd. , a black signal is always formed (FIG. 2C).

As the reference signal Sd of the third comparator 19 is supplied with a signal formed based on the clamp potential and the shading waveform, the third comparator 19 outputs a black and white binary value corresponding to the image signal Sd. signals are formed. These white, black, and monochrome binary signals are selected based on the edge detection information.

That is, when the edge signal EG is a rising edge, the comparison output of the first comparator 17 is selected, when it is a falling edge, the second comparison output is selected, and at other times, the comparison output of the first comparator 17 is selected. Comparison output No. 3 is selected.

By doing this, when a pixel changes from white to black, a black pixel is output, when a pixel changes from black to white, a white pixel is output, and when a pixel does not change, a binary signal is output. , when an image signal Sd as shown in FIG. 2C is manually generated, a binarized output signal as shown in FIG. 2G is obtained.

Thereby, no matter what the level of the image information is, it is possible to form a binarized output signal corresponding to the edge.

[Embodiment] Next, a case in which an example of the binarization processing circuit according to the present invention is applied to the signal processing system of the above-mentioned facsimile machine will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a connection diagram showing an example of a binarization processing circuit 1 according to the present invention.
edge detection means IA for forming edge detection information;
A signal generating means IB outputs a changed pixel as a black pixel and a white pixel based on this edge detection information, and a binarization means IC binarizes a non-changed pixel and selects it based on the edge detection information. It is composed of.

Here, the signal generating means IB is composed of at least first and second comparators 17 and 18 and a multiplexer 16, and the binarizing means IC is composed of a third comparator 19 and a multiplexer 16.

A specific example of the binarization processing circuit 1 will be explained in further detail.

First, the image signal S supplied to the terminal 2 is connected to the capacitor 10.
After the direct current component is cut off, the signal is supplied to the sampling and hold circuit 11, and is made into an image signal Sd as shown in FIG. 2C. This image signal Sd is supplied to the CR differentiation circuit 12 to form an edge signal EG corresponding to the image signal Sd (FIG. 2D).

The edge signal EG is supplied to the A/D converter 13, and the A/D converter 13 outputs a rising edge as an output "2", a falling edge as an output "0", and an intermediate level as "1". Conversion processing is performed. The A/D conversion output is used as a control signal CTL for a multiplexer 16, which will be described later (FIG. 2E).

Here, the A/D conversion base supplied to the A/D converter 13? Since the lK signal uses a signal formed based on the clamp potential applied to the terminals 14 and 15 and the shading signal, accurate edge information can be obtained without being affected by shading distortion. Obtainable.

The image signal Sd is further processed by first to third comparators 17 to 19.
is supplied to To explain from the first comparator 17, as the reference signal Sa for this, this image signal Sd,
A divided voltage output with the clamp potential supplied to the terminal 14 is used.

Therefore, the image signal Sd that has passed through the amplifier 21 is supplied to the non-inverting input terminal of the first comparator 17 in a state where the voltage is divided by the clamp potential and the resistors 22 and 23.

Therefore, the reference signal Sa always has a high level in relation to the image signal Sd, and is always obtained as a high-level comparison output. Therefore, the first comparison output corresponds to the white signal.

The image signal S [i is further supplied to the inverting input terminal of the second comparator 18, and the image signal S [i] is also supplied to the inverting input terminal of the second comparator 18, and
The divided voltage output with the shading signal supplied to the second
is supplied to the non-inverting input terminal as the reference signal Sc.

In this way, since the second reference signal Sc is a divided voltage output of the image signal Sd and the shading signal, as is clear from FIG. 2C, the second reference signal Sc is lower than the image signal Sd. It is always operated manually at a low level.

As a result, a second comparison output corresponding to the black level is obtained from the second comparator 18.

Note that 25 is an amplifier, and 26 and 27 are voltage dividing resistors. 30 is an analog switch which is normally used in the off state.

The image signal Sd is further supplied to the non-inverting input terminal of the third comparator 19, and the third comparator 19, which is formed based on the clamp potential and the shading signal, is supplied to the inverting input terminal of the third comparator 19.
The third reference signal S) is supplied with the reference signal sb, and the third reference signal S)) has a level as shown in FIG.
, rO'' binary third comparison output is obtained.

Note that 24 is a voltage dividing resistor.

The above-mentioned first to third comparison outputs are each supplied to the multiplexer 16, and the multiplexer 16 selects and outputs one of the comparison outputs based on the control signal CTL related to the edge detection information. The selection timing is synchronized with the clock pulse (:LK (see FIG. 2A)) supplied thereto.

In the embodiment, when the edge signal EG has a rising edge, the first comparison output is selected, when it has a falling edge, the second comparison output is selected, and at other times, the third comparison output is selected. It is configured as follows.

As a result, when the image signal Sd shown in FIG. 2C is generated manually, the control signal CTL becomes as shown in FIG. 2E, and the selected output is as shown in FIG. Become. As each reference signal at that time, the reference signal shown in F of the same figure is selected.

In this way, when a pixel changes from white to black, a comparison output corresponding to a black pixel is output, and when a pixel changes from black to white, a comparison output corresponding to a white pixel is output. Furthermore, unchanged pixels are binarized using another binarization threshold (equivalent to the third reference signal sb).

Therefore, when changing from white to black, the black level is always "0", and when changing from black to white, the white level is "0".
1'', so even if the human image signal Sd has a fine checkered pattern or vertical stripe pattern, as in the section α in Figure 2, the black and white binary output signal corresponding to the image information will be can get.

Furthermore, as shown in the section β in Fig. 2, even if the gray level of human image information fluctuates, this section β
The third comparator 19 outputs a comparison output "1" corresponding to white.
” is obtained, so white output is always selected for this section.

As a result, even if there is a slight variation in the image information, it can be converted into predetermined 2III information without following the variation.

[Effects of the Invention] As explained above, according to the present invention, when a pixel changes from white to black according to edge detection information of an image signal, a black pixel is output; In the range, the pixel is configured to be output as a white pixel, and in the section of the non-changed pixel, it is binarized based on another reference signal for binarization.

As a result, even for image signals related to minute image information, such as checkered patterns and vertical stripes, black and white 2III! It has the feature of significantly improving image quality.

Therefore, the binarization processing circuit according to the present invention is extremely suitable for application to the signal processing system of the above-mentioned facsimile machine.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an example of a binarization processing circuit according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a connection diagram showing an example of a conventional binarization processing circuit. FIG. 4 is a waveform diagram for explaining the operation. A B C 17 ~ l 9 Sa ~ Sc d

Claims (1)

[Claims] (1) An edge detection means for image signals, a signal generation means for outputting changed pixels as black pixels and white pixels based on this edge detection information, and a signal generation means for outputting changed pixels as black pixels and white pixels, and
A binarization processing circuit comprising a binarization means for converting into values and selecting the values based on the edge detection information.