JPS5948589B2 - Image signal binarization conversion circuit - Google Patents
Image signal binarization conversion circuitInfo
- Publication number
- JPS5948589B2 JPS5948589B2 JP50075565A JP7556575A JPS5948589B2 JP S5948589 B2 JPS5948589 B2 JP S5948589B2 JP 50075565 A JP50075565 A JP 50075565A JP 7556575 A JP7556575 A JP 7556575A JP S5948589 B2 JPS5948589 B2 JP S5948589B2
- Authority
- JP
- Japan
- Prior art keywords
- image
- signal
- image signal
- circuit
- black
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Facsimile Image Signal Circuits (AREA)
- Image Input (AREA)
Description
【発明の詳細な説明】
本発明は、ファクシミリ装置等の光電変換部でアナログ
画像信号を適度なスライスレベルでスライスし、白黒の
2値信号に変換する回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that slices an analog image signal at an appropriate slice level in a photoelectric conversion section of a facsimile machine or the like and converts it into a black and white binary signal.
ファクシミリ装置等の光電変換部に於いて、被読取原稿
面を走査し、該原稿面の濃淡を電気信号に変換し、これ
をそのまま、リニヤに変調し送信するか、又は、白黒の
2値に変換し、2値信号の形で送信するかのいづれかの
方法がとられている。The photoelectric conversion unit of a facsimile machine scans the surface of the document to be read, converts the shading of the document surface into an electrical signal, and either modulates it linearly and transmits it directly, or converts it into binary black and white. One of two methods is used: converting the signal and transmitting it in the form of a binary signal.
本発明は、後者の白黒の2値信号にする回路方式に関す
る。2値化する場合、原稿面の画像は濃淡を含み、かつ
バックグランドが真白の時や、例えば新聞紙のようなハ
ーフトーンを含むものがある。The present invention relates to the latter circuit system for converting black and white binary signals. In the case of binarization, the image on the document surface may include shading, and the background may be pure white or may include halftones such as, for example, newspaper.
このため、単純に一定の固定スライスレベルでスライス
すると、薄い文字は白に変換されたり、またハーフトー
ンは黒になつたりして画像の忠実性が失なわれる欠点が
ある。本発明は上記欠点を除去するため画像信号に応答
して動作する積分回路による基準電圧とバックグランド
の濃淡レベルに比例する基準電圧とを画像信号より作成
合成し、これによりスライスして、良好な画像を得る手
段を提供するものである。Therefore, if the image is simply sliced at a fixed slice level, thin characters will be converted to white, and halftones will become black, resulting in a loss of image fidelity. In order to eliminate the above-mentioned drawbacks, the present invention creates and synthesizes a reference voltage by an integrating circuit that operates in response to an image signal and a reference voltage that is proportional to the gray level of the background from the image signal, and slices the image signal to create a good image. It provides a means to obtain images.
第1図に本発明の一実施例のブロック図を示す。同図に
おいて1はアナログ画像信号の入力端子、2は画像信号
のアナログ増巾器、3は画像信号のレベルに応答して動
作する積分回路、4はバックグランドのレベルに応答し
て動作する積分回路、5、6は出力インピーダンスの低
い前記両積分回路3、4の出力を加算するために設けら
れたダイオード、7はアナログ増幅器2の出力の画像信
号と合成信号を比較して、スライスする比較回路、8は
白黒の2値化された出力信号端子である。第2図はこの
回路の動作説明図であつて、イの10は画像信号、11
は積分回路3の出力、12は積分回路4の出力信号波形
を図示したものであり、口は出力端子8の2値化された
出力信号波形を示す。以下詳述すると、入力端子1に印
加された画像信号はアナログ増巾器2、積分回路3,4
に加えられる。FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 1 is an analog image signal input terminal, 2 is an analog amplifier for the image signal, 3 is an integration circuit that operates in response to the level of the image signal, and 4 is an integration circuit that operates in response to the background level. diodes 5 and 6 are provided to add the outputs of the integration circuits 3 and 4 with low output impedance; 7 is a comparison circuit for comparing and slicing the image signal output from the analog amplifier 2 and the composite signal; The circuit 8 is a black and white binary output signal terminal. FIG. 2 is an explanatory diagram of the operation of this circuit, in which 10 in A is an image signal, 11
12 shows the output signal waveform of the integrating circuit 3, 12 shows the output signal waveform of the integrating circuit 4, and the numeral 12 shows the binarized output signal waveform of the output terminal 8. To explain in detail below, the image signal applied to the input terminal 1 is input to the analog amplifier 2, the integrating circuits 3 and 4.
added to.
積分回路3は、この画像信号に応答し、積分時定数とし
て、黒レベルから白レベルへの変化に対しては画像信号
に応答して、早い時定数でチヤージアツプし、かつ、白
レベルから黒レベルへの変化に対しては、適度な時定数
で(最高画周波数程度)放電する特性を有する。この結
果積分回路3の出力は、第2図イの波形11の如くにな
る。積分回路4は画像信号に応答し、積分時定数として
、黒レベルから白レベルへの変化に対しては、画像信号
に応答して、早い時定数でチヤージアツプし、白レベル
から黒レベルへの変化に対しては、画像信号の最も低い
周波数に比して充分長い時定数で放電する特性を有する
。この結果積分回路4の出力は、第2図イの波形12の
如くになる。すなわち、積分回路3は画像信号の高い周
波数部分のスライス基準電圧を得ており、積分回路4は
、画像信号の白いレベル(バツクグランド)応じた大き
さの電圧が得られている。The integration circuit 3 responds to this image signal and charges up as an integration time constant with a fast time constant in response to a change from the black level to the white level, and charges up with a fast time constant when changing from the white level to the black level. It has a characteristic of discharging with an appropriate time constant (approximately the highest image frequency) in response to a change in . As a result, the output of the integrating circuit 3 becomes a waveform 11 shown in FIG. 2A. The integrating circuit 4 responds to the image signal and charges up as an integration time constant with a fast time constant in response to the change from the black level to the white level, and charges up with a fast time constant when changing from the white level to the black level. has a characteristic of discharging with a sufficiently long time constant compared to the lowest frequency of the image signal. As a result, the output of the integrating circuit 4 becomes a waveform 12 in FIG. 2A. That is, the integrating circuit 3 obtains a slice reference voltage for the high frequency portion of the image signal, and the integrating circuit 4 obtains a voltage corresponding to the white level (background) of the image signal.
以上の説明の積分回路3,4の出力信号は加算用ダイオ
ード5,6で加算され、比較回路7に加えられ、アナロ
グ増巾器2の出力の画像信号(第2図イの波形10)と
比較される。The output signals of the integrating circuits 3 and 4 explained above are added by the adding diodes 5 and 6, and then added to the comparator circuit 7, where they are combined with the image signal of the output of the analog amplifier 2 (waveform 10 in Figure 2 A). be compared.
この結果第2図イで波形10が波形11又は12より下
まわつた部分は第2図口の2値化信号出力波形で表わさ
れている様に黒と判定される。すなわち、例えば画像が
薄い文字の場合は画像信号の振巾は、小さく且つ、その
絶対出力は真白レベルに近い出力となるが、積分回路3
の機能により自動的に波形11のスライス基準電圧が真
白レベル側に動き白、黒、の判定が行われる。As a result, the portion where waveform 10 is lower than waveform 11 or 12 in FIG. 2A is determined to be black, as represented by the binarized signal output waveform at the beginning of FIG. That is, for example, if the image is a thin character, the amplitude of the image signal will be small and its absolute output will be close to the pure white level, but the integration circuit 3
By this function, the slice reference voltage of the waveform 11 automatically moves toward the true white level side, and the determination of white and black is performed.
又、バツクグランドが新聞紙の如くハーフトーンの場合
、画像信号の白レベルは真黒レベルよりになるが、この
場合は積分回路4の機能により自動的に12のスライス
基準電圧が真黒レベル側に動き、白.黒の判定が行われ
る。以上説明のごとく、本発明によれば被読取原稿画像
の濃淡およびバツクグラウンドの濃淡の広い範囲につい
て、忠実な白.黒2値の判定を行うことができる。In addition, when the background is a halftone like a newspaper, the white level of the image signal is lower than the pure black level, but in this case, the function of the integrating circuit 4 automatically moves the 12 slice reference voltages toward the pure black level. White. A black judgment is made. As explained above, according to the present invention, faithful whiteness can be achieved over a wide range of shading of the original image to be read and the shading of the background. Black binary values can be determined.
第1図は、本発明にか\るブロツクダイヤを示し、第2
図は、本発明の動作説明図である。
1は画像信号入力端子、2は増巾器、3は積分回路、4
は積分回路、5,6は合成用ダイオード、7は比較器、
8は出分端子である。
10はアナログ画像信号、11は積分回路3の出力波形
、12は積分回路4の出力波形である。FIG. 1 shows a block diagram according to the present invention, and the second
The figure is an explanatory diagram of the operation of the present invention. 1 is an image signal input terminal, 2 is an amplifier, 3 is an integration circuit, 4
is an integrating circuit, 5 and 6 are synthesis diodes, 7 is a comparator,
8 is an output terminal. 10 is an analog image signal, 11 is an output waveform of the integrating circuit 3, and 12 is an output waveform of the integrating circuit 4.
Claims (1)
の濃淡信号を走査して得られたアナログ信号を白黒の2
値信号に変換する場合において、前記画像の濃淡信号に
応答し、早い時定数で充電し、放電時には前記画像信号
の最高画周波数程度に対応する時定数を有する第1の積
分回路と、早い時定数で充電し、放電時には前記画像信
号の最低画周波数に対応する十分長い時定数を有する第
2の積分回路とを有し、両積分回路の出力を加算しこれ
をスライス基準電圧として前記画像濃淡信号と共に比較
回路に加え、前記画像濃淡信号の白黒2値を判定するよ
うにしたことを特徴とする画像信号の2値化変換回路。1 The analog signal obtained by scanning the grayscale signal of the original image to be read by the photoelectric conversion unit of a facsimile machine, etc. is converted into two black and white signals.
When converting into a value signal, a first integrating circuit responds to the gray level signal of the image, charges with a fast time constant, and has a time constant corresponding to approximately the highest image frequency of the image signal when discharging; It has a second integrating circuit that charges at a constant rate and has a time constant long enough to correspond to the lowest image frequency of the image signal during discharging, and adds the outputs of both integrating circuits and uses this as a slice reference voltage to determine the image density. 1. A binarization conversion circuit for an image signal, characterized in that the circuit is added to a comparison circuit together with the signal and determines whether the image gradation signal has black or white binary values.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50075565A JPS5948589B2 (en) | 1975-06-23 | 1975-06-23 | Image signal binarization conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50075565A JPS5948589B2 (en) | 1975-06-23 | 1975-06-23 | Image signal binarization conversion circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5210613A JPS5210613A (en) | 1977-01-27 |
JPS5948589B2 true JPS5948589B2 (en) | 1984-11-27 |
Family
ID=13579820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50075565A Expired JPS5948589B2 (en) | 1975-06-23 | 1975-06-23 | Image signal binarization conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5948589B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5926690Y2 (en) * | 1978-07-20 | 1984-08-02 | 三洋電機株式会社 | Image signal binarization circuit |
JPS58146179A (en) * | 1982-02-24 | 1983-08-31 | Nec Corp | Binarizing circuit of facsimile signal |
JPS6094577A (en) * | 1983-10-28 | 1985-05-27 | Tokyo Keiki Co Ltd | Digitizing device of picture signal |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5065163A (en) * | 1973-09-12 | 1975-06-02 |
-
1975
- 1975-06-23 JP JP50075565A patent/JPS5948589B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5065163A (en) * | 1973-09-12 | 1975-06-02 |
Also Published As
Publication number | Publication date |
---|---|
JPS5210613A (en) | 1977-01-27 |
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