JPS60239042A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten the surface of an interlayer insulating film and to eliminate the disconnection of wirings to be provided thereon by a method wherein an inorganic film is applied on an insulating film with a stepping, and when a dry etching is going to be performed on these films, the shortest distance ratio from the height of the stepping and lower end of the stepping to the surface of the inorganic film is prescribed as 1:1-3:1. CONSTITUTION:An SiO2 film 2 is coated on an Si substrate 1, Al wirings 3 and 4 of prescribed shape are formed thereon, and a PSG film 5 is coated on the substrate 1 having the stepping which is formed as above-mentioned. Then, a silica film 6 of the SiO2 concentration of 5.9wt% is coated on the film 5 whereon a stepping is generated between the top part 5a and the bottom face part 5b by the presence of the wirings 3 and 4, and the film 6 is sintered by performing a heat treatment at 90 deg.C for one minute, then at 200 deg.C for thirty minutes, and lastly, at 400 deg.C for 30min. Subsequently, the film 6 is completely removed by performing an anisotropic etching, and the film 5 having small surface stepping 5c is left. In order to have the avobe result, the height of the stepping which is generated first and the shortest distance between the lower end and the surface of the film 6 are specified in advance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that is most suitable for forming wiring on an interlayer insulating film in a MOS LSI or a bipolar LSI.

Background technology and its problems When performing multilayer wiring in MOS LSI or bipolar LSI, it is necessary to reduce the level difference on the surface of the interlayer insulating film, that is, to flatten it, in order to prevent disconnections and short circuits in the wiring. be. The following methods are conventionally known as methods for this purpose. The first method is to
First, resist or PIQ (polyimide resin) is applied, and then the interlayer insulating film and the interlayer insulating film are etched while adjusting the flow rate of oxygen in the etching gas to make the etching rate of the resist or PIQ and the interlayer insulating film substantially the same. This method flattens the interlayer insulating film by dry etching the resist or PIQ. In this first method, when etching progresses and the upper surface of the glabellar insulating film made of 5i02, PSG, etc. is exposed, oxygen gas is generated from SiO□ or PSG, and therefore oxygen gas is locally generated in this area. The drawback is that it is difficult to obtain a flat surface because the partial pressure increases and the etching rate of the resist or PTQ increases. The second method is to apply a thick inorganic film such as silica film on the glabellar insulating film so that the level difference is completely filled, and then perform reactive ion etching (RI).
In this method, the inorganic film and the interlayer insulating film are etched using E) to planarize the interlayer insulating film. In this second method, since the inorganic film must be applied thickly, there is a drawback that cranking is likely to occur during annealing to solidify the inorganic film. Furthermore, since the surface is almost completely flattened, the thickness of the glabellar insulating film varies greatly depending on the location, making it difficult to perform etching to form contact balls in the next step.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that corrects the above-mentioned drawbacks of the conventional method for manufacturing a semiconductor device, which does not planarize the interlayer insulating film. shall be.

Summary of the Invention A method for manufacturing a semiconductor device according to the present invention includes coating an inorganic film on an insulating film having a step, and then etching the inorganic film and the insulating film using a dry etching method. In this step, the inorganic film is coated on the insulating film so that the ratio between the height of the step and the shortest distance from the bottom end of the step to the surface of the inorganic film is 1:1 to 3:1. ing. By doing this, it is possible to reduce the level difference on the surface of the insulating film after etching, and to make the surface of the insulating film have a smooth curved shape with a gentle slope that corresponds to the surface shape when the inorganic film was applied. Therefore, when an i-wire or the like is formed on this insulating film, disconnection or short-circuiting of the wire near the step can be prevented, and the step coverage and step image of the wire can be improved. Furthermore, even after etching, the surface of the insulating film has a curved shape that corresponds to some extent to the surface shape of the underlying Aj2 wiring, etc., which causes the step difference, so the thickness of the insulating film is almost constant regardless of the location, so A7! Etching for forming contact holes such as wiring is easy.

EXAMPLE Hereinafter, an example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

As shown in FIG. 1A, first, a film having a thickness of, for example, 5,000 mm is coated on a SiO□ film 2 previously formed on, for example, a silicon substrate 1.
A first layer of ^p wiring 3.4 having a width of 1.5 μm (wiring pitch is, for example, 4 μm) is formed manually. Next, the entire surface is coated with P with a thickness of 1 μm and a phosphorus concentration of 5.2% by weight using the CVD method.
SGSbO2 deposit is formed.

In this case, ^l arrangement 513. Top surface portion 5a corresponding to 4
There is a step 5C between the bottom part 5b corresponding to the 5i02 film 2.
is formed. Although predetermined diffusion layers (for example, source and drain regions in the case of a MOS LSI) are actually formed in the silicon substrate 1, their illustration is omitted in FIG. 1A (the same applies hereinafter).

Next, as shown in FIG. 1B, a silica film 6 (for example, SiO□
A thin film (with a concentration of 5.9% by weight) (for example, an average film thickness of 0.311 m) is applied over the entire surface.As is clear from FIG. 1B, the thickness of the silica film 6 after application is not uniform; The PSGSbO2 surface portion 5b has a large film thickness (for example, a film thickness of 2,500 layers), and the top surface portion 5a has a small film thickness (for example, a film thickness of 500 layers).
The shortest distance d from the lower end 5d of the step 5C formed by the edge b to the surface of the silica film 6 is about 4000 people. After this, for example, first at 90°C for 15 minutes, then at 20°C.
Annealing is performed by increasing the temperature stepwise at 0°C for 30 minutes and finally at 400°C for 30 minutes to solidify the silica film 6 without producing any cranking, and also to improve the silica film 6 during etching by RTE, which will be described later. The etching speed of the silica film 6 and PSGSbO2 are made to be substantially the same.

In addition, in FIG. 1B, P after etching described below is shown.
The SGSbO2 surface is indicated by a dashed line.

Next, anisotropic etching is performed in the direction perpendicular to the silicon substrate 1 to a predetermined thickness, for example, about 4,500 wafers, using the aforementioned RIB using CHF 3 gas as an etching gas. As a result of this etching, the silica film 6 is completely removed, and the PSGSbO2 surface portion 5a on which the thin silica film 6 was formed is removed from the silica film 6.
It is etched by a thickness approximately equal to the difference between the maximum film thickness (for example, about 4500 people) and the minimum film thickness (for example, about 500 people). As a result, the step 5 on the PSGSbO2 surface
As C becomes smaller, the PSGSbO2 surface becomes a smooth curved shape with a gentle slope similar to the surface shape of the silica film 6 shown in FIG. 1B. After this, a contact hole is formed by etching away the PSGSbO2 constant part,
Next, a second layer of ^p wiring is formed to complete the desired semiconductor device.

According to the above embodiment, since the silica film 6 and PSGSbO2 are bonded by the RIB method in the state shown in FIG. 1B, the PSGSbO2 difference 5C is made sufficiently small as shown in FIG. 1C compared to FIG. 1A. It is possible to obtain a smooth surface shape with a gentle slope. Therefore, when the second-layer wiring is formed on the PSG film 5, disconnection or short circuit of the wiring near the step 5C can be prevented. In addition, the step coverage and step image (planar shape of the β wiring in the vicinity of the step 5C) of the β wiring are also good.

In addition, in the above-mentioned example, since the silica film 6 and PSGSbO2 are deposited by the RIB method, there is extremely little dust generation compared to the case where the ion beam sputtering method is used, and therefore the yield decreases due to dust. rarely occurs. Furthermore, since the silica film 6 is completely removed by RTB, the problem of reaction between the organic resist formed in the next contact hole formation process and the silica film 6 is solved, and therefore the reliability of the semiconductor device due to this reaction is solved. It is possible to prevent a decline in sexual performance.

Further, according to the above embodiment, by selecting the annealing conditions for the silica film 6 as described above, the etching rate of the silica film 6 during RIB etching is made to be substantially the same as the PSGSbO2 etching rate. Therefore, as shown in Figure 1C, PSGSbO
The two surfaces can have a smooth curved surface shape with a gentle slope that approximates the surface shape of the silica film 6 shown in FIG. 1B.

Furthermore, in the above-mentioned example, since the highest temperature used in the series of steps required to make PSGSbO2 surface is 400°C (that is, it is a low-temperature process), impurities in the diffusion layer formed in the silicon substrate 1 are There will be no rediffusion or melting of the AN wiring.

Furthermore, in the above embodiment, even after RIB etching, the PSGSbO2 surface has a curved shape that corresponds to some extent to the surface shape of the wiring 3.4, so the PSGS
Since the bO2 thickness is approximately constant regardless of location, there is also the advantage that etching for forming contact holes is easy.

Also, like PSGSbO2, silica film 6 is an inorganic film.
is used as the coating material, so as described in the conventional method (first method), resist or PIQ is used as the coating material.
When using PSGS, there is no change in the etching rate of the coating material due to oxygen gas generated from the PSG film, etc.
The bO2 surface can be easily formed into a smooth curved shape with a gentle slope.

Furthermore, it is generally known that if the shortest distance d from the lower end 5d of the PSGSbO2 difference 5C to the surface of the silica film 6 exceeds 6,000 people, the crank tends to enter near the step 5c when performing the 7 knee J of the silica film 6. In the above embodiment, the silica film 6 is coated so that d is sufficiently smaller than this limit value, that is, d = 4000 people, so there is an advantage that the occurrence of cracks can be prevented. be.

The present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention. For example, in the above-described embodiments, PSGSbO2 with a phosphorus concentration of 5.2% by weight was used as the glabellar insulating film, but it is of course possible to use a PSG film with a phosphorus concentration different from the above, if necessary. For example, an As5G film may be used. Alternatively, other types of insulating films such as PSG films may be used. In addition, in the above embodiment, as shown in FIG. 1A, when the height h of the PSGSbO2 difference 5C is 5000 people, the shortest distance d from the bottom end 5d of the step to the surface of the silica film 6 (see FIG. 1B) Although the silica film 06 was applied so that the thickness of the film was approximately 4,000, it may be made thicker or thinner than this if necessary. However, if h is smaller than d, the surface of the inorganic film such as silica film 6 will be flattened.
For the reasons mentioned above, etching for forming contact holes becomes difficult, and if h is more than three times d, it becomes difficult to form the surface of the insulating film into a smooth curved shape with a gentle slope. d must be 1:1 to 3:1. Further, as described above, if d>6000, cranks are likely to enter the inorganic film, so it is preferable to apply the inorganic film so that d≦6000. Although it varies depending on the height of the step, the height of the step after etching is preferably, for example, 115 to 415, more preferably 115 to ⅔ of the height of the step before etching.

Furthermore, in the above embodiment, the etching rate of the silica film 6 can be increased by selecting the annealing conditions (especially temperature) of the silica film 6 as described above.
PSGSbO
The etching rate of the glabella insulating film 6 may be made substantially the same as the etching rate of the silica film 6 by appropriately selecting the concentration of the silica film 6.
Generally, by appropriately selecting the impurity concentration of the interlayer insulating film and the annealing conditions for the inorganic film, the etching rates of the interlayer insulating film and the inorganic film may be made substantially the same. Furthermore, it is not always necessary to make the etching rate of the interlayer insulating film and the inorganic film substantially the same; for example, if the etching rate of the inorganic film is made lower than the etching rate of the interlayer insulating film, the surface of the interlayer insulating film can be etched more sloped. It is possible to have a gently curved surface shape. Note that the annealing temperature of the inorganic film is preferably 450° C. or lower in order to prevent the occurrence of cracks. Further, the impurity concentration of the interlayer insulating film such as the PSG film or the As5G film is preferably 4 to 8% by weight in order to have a higher etching rate than an inorganic film.

Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention, the ratio between the height of the step of the insulating film and the shortest distance from the bottom end of the step to the surface of the inorganic 2 film is 1:1 to 3:1. Since the inorganic film is coated on the insulating film, it is possible to reduce the level difference on the surface of the insulating film after etching, and the surface of the insulating film can be sloped to approximate the surface shape when the inorganic film is applied. It can be made into a gentle and smooth curved shape. Therefore, A7! When forming wiring etc.
It is possible to prevent disconnections and short circuits in the wiring near the step, and to improve the step coverage and step image of the wiring. In addition, even after etching, the surface of the insulating film has a curved shape that corresponds to some extent to the surface shape of the underlying wiring, etc., which causes the step difference, so the thickness of the insulating film remains almost constant regardless of the location. β
Etching for forming contact holes such as wiring is easy.

Furthermore, since it is possible to reduce the thickness of the inorganic film,
Cracks do not occur in the inorganic film during annealing to solidify the inorganic film.

[Brief explanation of drawings]

FIGS. 1A to 1C are cross-sectional views showing one embodiment of a method for manufacturing a semiconductor device 3 according to the present invention in the order of steps. In addition, in the symbols used in the drawings, 1 -------------------Silicon substrate 3, 4----------1 to efki line 5 - −−−−−−−−−−−−−−−−−−−PSGS
bO2---------------One step difference 6
------------------------ It is a silica film. Agent Ueya Katsutsunekane Yoshio 4

Claims (1)

[Claims] In a method for manufacturing a semiconductor device, in which an inorganic film is coated on an insulating film having a step, and then the inorganic film and the insulating film are etched by a dry etching method, the height of the step and the distance from the lower end of the step to the A method for manufacturing a semiconductor device, characterized in that the inorganic film is coated on the insulating film so that the ratio to the shortest distance to the surface of the inorganic film is 1:1 to 3:1.