JPS60236266A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60236266A JPS60236266A JP59093401A JP9340184A JPS60236266A JP S60236266 A JPS60236266 A JP S60236266A JP 59093401 A JP59093401 A JP 59093401A JP 9340184 A JP9340184 A JP 9340184A JP S60236266 A JPS60236266 A JP S60236266A
- Authority
- JP
- Japan
- Prior art keywords
- lower layer
- thin film
- film transistor
- layer
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 2
- 239000010409 thin film Substances 0.000 abstract description 14
- 239000010408 film Substances 0.000 abstract description 9
- 239000011248 coating agent Substances 0.000 abstract 3
- 238000000576 coating method Methods 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、例えば液晶駆動用薄膜トランジス
タアレイに対して用いることのできる半近年、液晶表示
パネル用薄膜トランジスタ（ＴＰＴ）の高集積化、均一
性、信頼性がめられている中で、電極配線の断線が大き
な問題となっている。このため、断線防止に対して種々
の対応がなされている。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention can be used for semiconductor devices, for example, thin film transistor arrays for driving liquid crystals. As reliability becomes more important, disconnections in electrode wiring have become a major problem. For this reason, various measures have been taken to prevent wire breakage.
以下、図面を参照しながら従来の薄膜ｌ・ランジスタの
配線方法について説明する。第１図は従来の薄膜トラン
ジスタを上から見た図であり、第２図はその断面図であ
る。第１図、第２図で１はゲート、２は絶縁膜、３は半
導体膜、４は絶縁膜、６はコンタクトホール、６ｆ′ｉ
配線電極である。Hereinafter, a conventional method of wiring a thin film transistor will be explained with reference to the drawings. FIG. 1 is a top view of a conventional thin film transistor, and FIG. 2 is a cross-sectional view thereof. In Figures 1 and 2, 1 is a gate, 2 is an insulating film, 3 is a semiconductor film, 4 is an insulating film, 6 is a contact hole, 6f'i
It is a wiring electrode.
以上のように構成された薄膜トランジスタにおいては各
層の段差部分でパターニング時にエツチング液による回
り込みＫよる断線が発生するという問題点を有し−（い
た。The thin film transistor constructed as described above has a problem in that disconnection occurs due to the etching solution running around during patterning at the stepped portions of each layer.
発明の目的
本発明の目的は段差を有する薄膜トランジスタにおいて
、段差部分での断線防止を簡易に可能とする構造をした
薄膜トランジスタを捉供することにある。OBJECTS OF THE INVENTION An object of the present invention is to provide a thin film transistor having a structure in which disconnection at the step portion can be easily prevented in a thin film transistor having a step difference.
発明の構成
本発明の薄膜トランジスタは、平面基板−トに形成され
、平面内で構造を有する少なくとも１つの下部層と、そ
の下部層の上に積層さねた１一部層を含み、前記上部層
の構造端部における段差のうち前記上部層により被覆さ
れる重な怜部分の実効的な段差被覆長を大きくするよう
構成したものであり、これにより段差部での断線防止を
実現するものである。Structure of the Invention The thin film transistor of the present invention is formed on a planar substrate and includes at least one lower layer having a structure in the plane, and one layer stacked on the lower layer, and the upper layer Among the steps at the ends of the structure, the effective step covering length of the overlapping edge portion covered by the upper layer is increased, thereby preventing wire breakage at the step. .
実施例の説明
以下、本発明の実施例について、図面を参照しながら説
明する。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第３図は下部層７の上に電極配線８をほどこした最も簡
単な例である。この場合、点線で囲んだ部分は断線しや
すい。第４図、第６図、第６図は本発明の一実施例に係
る下部層、ｌ一部層の構造の例である。第４図、第５図
は下部層を屈曲させて被覆面積を大きくしている。第６
図は上部層の幅を一部大きくすることで被覆面積を大き
くしている。特に第４図、第６図の例では、下部層が１
１角に曲っている。もし、上部層がサイドエッチされた
場合でも角で阻止することが可能である。FIG. 3 shows the simplest example in which electrode wiring 8 is provided on the lower layer 7. In this case, the portion surrounded by the dotted line is likely to be disconnected. FIG. 4, FIG. 6, and FIG. 6 are examples of the structure of the lower layer and the first layer according to an embodiment of the present invention. In FIGS. 4 and 5, the lower layer is bent to increase the coverage area. 6th
In the figure, the coverage area is increased by partially increasing the width of the upper layer. In particular, in the examples shown in Figures 4 and 6, the lower layer is 1
It is curved in one corner. Even if the upper layer is side-etched, it can be stopped at the corners.
第７図は第４図の構造を用いた薄膜トランジスタの例で
ある。第７図において、１１はゲ−１・、１２は絶縁膜
、１３は半導体、１４は絶縁膜、１６はコンタクトホー
ル、１６は配線電極である。FIG. 7 is an example of a thin film transistor using the structure shown in FIG. 4. In FIG. 7, 11 is a gate, 12 is an insulating film, 13 is a semiconductor, 14 is an insulating film, 16 is a contact hole, and 16 is a wiring electrode.
以上のように構成された本実施例の薄膜トランジスタで
は、第４図と同様に各層の形状を形成すのものに限定さ
れるものではなく、第５図、第６図等もあり、段差被覆
長が大きくなるものであれば何でもよい。In the thin film transistor of this embodiment configured as described above, the shape of each layer is not limited to that shown in FIG. 4, and there are also shapes such as those shown in FIGS. Anything that increases is fine.
発明の効果
以上の説明から明らかなように、本発明は複数の層から
成る薄膜トランジスタの段差部分の形状を、下部層を被
う配線との段差被覆長が大きくなるように形成すること
で断線を簡易に防止できる効果がある。Effects of the Invention As is clear from the above description, the present invention prevents disconnection by forming the step portion of a thin film transistor consisting of multiple layers so that the step coverage length with the wiring covering the lower layer is large. It has the effect of being easily preventable.
第１図は従来の薄膜トランジスタの図、第２図は第１図
の点線での断面図、第３図は２層の場合の断線の最も発
生しやすい構造図、第４図、第６図、第６図は本発明の
一実施例に係る断線防止構造の図、第７図は本発明の一
実施例である薄膜トランジスタの図である。
１・・・・・ゲート、２・・−・・絶縁膜、３・・・・
・半導体、４・・・・絶縁膜、６・・ コンタクトホー
ル、６・・・・・配線金属、７・・・・下部層、８・・
・・・・上部層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第３図 ′″′４図Figure 1 is a diagram of a conventional thin film transistor, Figure 2 is a cross-sectional view taken along the dotted line in Figure 1, Figure 3 is a diagram of the structure where disconnection is most likely to occur in the case of two layers, Figures 4 and 6, FIG. 6 is a diagram of a disconnection prevention structure according to an embodiment of the present invention, and FIG. 7 is a diagram of a thin film transistor according to an embodiment of the present invention. 1...Gate, 2...Insulating film, 3...
・Semiconductor, 4... Insulating film, 6... Contact hole, 6... Wiring metal, 7... Lower layer, 8...
...upper layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 4 ``'''
Claims (1)
積層された上部層とを含み、前記下部層の端部における
段差部のうち前記上部層により被覆される領域の長さを
前記上部層の幅より大きくしたことを％徴とする半導体
装置。 （２）下部層の構造端部における段差と上部層の重なり
部分において、前記下部層の構造端部の形を屈曲させた
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。 （３） 重なり部分における上部層の幅を前記型なり部
分以外の幅よりも大きくしたことを特徴とする特許請求
の範囲第１項記載の半導体装置。 （４）上部層が電極配線であることを特徴とする特許請
求の範囲第１項記載の半導体装置。 （６）下部層が半導体層であることを特徴とする特許請
求の範囲第１項記載の半導体装置。Scope of Claims: (1) A lower layer formed on a substrate and an upper layer laminated on the lower layer, wherein a stepped portion at an end of the lower layer is covered by the upper layer. A semiconductor device characterized in that the length of the region to be covered is larger than the width of the upper layer. (2) The semiconductor device according to claim 1, characterized in that the shape of the structural end of the lower layer is bent at a portion where the step at the structural end of the lower layer and the upper layer overlap. (3) The semiconductor device according to claim 1, wherein the width of the upper layer at the overlapping portion is larger than the width at the portion other than the molded portion. (4) The semiconductor device according to claim 1, wherein the upper layer is an electrode wiring. (6) The semiconductor device according to claim 1, wherein the lower layer is a semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59093401A JPS60236266A (en) | 1984-05-10 | 1984-05-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59093401A JPS60236266A (en) | 1984-05-10 | 1984-05-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60236266A true JPS60236266A (en) | 1985-11-25 |
Family
ID=14081273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59093401A Pending JPS60236266A (en) | 1984-05-10 | 1984-05-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60236266A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS625658U (en) * | 1985-06-25 | 1987-01-14 | ||
| JPS62280890A (en) * | 1986-05-30 | 1987-12-05 | 松下電器産業株式会社 | Active matrix array |
| EP0488802A2 (en) * | 1990-11-30 | 1992-06-03 | Sharp Kabushiki Kaisha | An active matrix display device |
| US5276540A (en) * | 1990-11-30 | 1994-01-04 | Sharp Kabushiki Kaisha | Active matrix substrate with conductive film covering transparent conductive film portion connecting additional and non-additional capacitance portions of pixel electrode |
| EP0597641A2 (en) * | 1992-11-12 | 1994-05-18 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor and method of fabricating the same |
| US7511301B2 (en) | 2003-12-01 | 2009-03-31 | Nec Lcd Technologies, Ltd. | Liquid crystal display unit |
| WO2012070498A1 (en) * | 2010-11-25 | 2012-05-31 | シャープ株式会社 | Display device and television receiver |
| CN104460150A (en) * | 2014-12-09 | 2015-03-25 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal display panel and manufacturing method of array substrate |
| JP2015173296A (en) * | 2015-06-24 | 2015-10-01 | 株式会社ジャパンディスプレイ | display device |
| CN109545799A (en) * | 2018-11-09 | 2019-03-29 | 惠科股份有限公司 | Display panel, manufacturing method and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940365B1 (en) * | 1970-07-13 | 1974-11-01 | ||
| JPS5982769A (en) * | 1982-11-04 | 1984-05-12 | Seiko Epson Corp | Thin film silicon transistor |
-
1984
- 1984-05-10 JP JP59093401A patent/JPS60236266A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940365B1 (en) * | 1970-07-13 | 1974-11-01 | ||
| JPS5982769A (en) * | 1982-11-04 | 1984-05-12 | Seiko Epson Corp | Thin film silicon transistor |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS625658U (en) * | 1985-06-25 | 1987-01-14 | ||
| JPS62280890A (en) * | 1986-05-30 | 1987-12-05 | 松下電器産業株式会社 | Active matrix array |
| EP0488802A2 (en) * | 1990-11-30 | 1992-06-03 | Sharp Kabushiki Kaisha | An active matrix display device |
| US5276540A (en) * | 1990-11-30 | 1994-01-04 | Sharp Kabushiki Kaisha | Active matrix substrate with conductive film covering transparent conductive film portion connecting additional and non-additional capacitance portions of pixel electrode |
| US5287206A (en) * | 1990-11-30 | 1994-02-15 | Sharp Kabushiki Kaisha | Active matrix display device |
| EP0597641A3 (en) * | 1992-11-12 | 1994-10-19 | Matsushita Electric Ind Co Ltd | Thin-film transistor and method of fabricating the same. |
| EP0597641A2 (en) * | 1992-11-12 | 1994-05-18 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor and method of fabricating the same |
| US5528055A (en) * | 1992-11-12 | 1996-06-18 | Matsushita Industrial Electric Co., Ltd. | Thin-film transistor |
| US7511301B2 (en) | 2003-12-01 | 2009-03-31 | Nec Lcd Technologies, Ltd. | Liquid crystal display unit |
| WO2012070498A1 (en) * | 2010-11-25 | 2012-05-31 | シャープ株式会社 | Display device and television receiver |
| US8994886B2 (en) | 2010-11-25 | 2015-03-31 | Sharp Kabushiki Kaisha | Display device and television device |
| CN104460150A (en) * | 2014-12-09 | 2015-03-25 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal display panel and manufacturing method of array substrate |
| JP2015173296A (en) * | 2015-06-24 | 2015-10-01 | 株式会社ジャパンディスプレイ | display device |
| CN109545799A (en) * | 2018-11-09 | 2019-03-29 | 惠科股份有限公司 | Display panel, manufacturing method and display device |
| US11495622B2 (en) | 2018-11-09 | 2022-11-08 | HKC Corporation Limited | Display panel, manufacture method and display apparatus |
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