KR950025876A - How to form self-aligned contacts - Google Patents
How to form self-aligned contacts Download PDFInfo
- Publication number
- KR950025876A KR950025876A KR1019940003890A KR19940003890A KR950025876A KR 950025876 A KR950025876 A KR 950025876A KR 1019940003890 A KR1019940003890 A KR 1019940003890A KR 19940003890 A KR19940003890 A KR 19940003890A KR 950025876 A KR950025876 A KR 950025876A
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- South Korea
- Prior art keywords
- forming
- layer
- film
- insulating
- insulating layer
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자 제조 공정중 자기 정렬 콘택 형성 방법에 있어서, 하부전도층(21)이 형성된 웨이퍼 전체구조상부에 제1절연막(22)을 형성하는 단계, 상기 제1절연막(22)상에 제1절연막(22)과 식각선택비가 우수한 물질막(23)을 형성하는 단계, 하부전도층(21) 상에 오버랩되어 상기 물질막(23)이 남도록 물질막(23)의 소정부위를 식각하는 단계, 전체구조 상부에 제2절연막(25)을 형성하는 단계, 전체구조 상부에 자기 정렬 콘택 식각장벽 물질막(26)을 형성하고 상기 제2 및 제1절연막절연막(25,22)을 식각하는 단계, 및 상기 식각장벽물질막(26)을 제거하고 상부전도층물질(27)을 증착하는 단계를 포함하여 이루어지는 것을 특징으로 하는 자기 정렬 콘택 형성방법에 관한 것으로, 자기 정렬 콘택시 층간의 브리지을 방지하고 소자의 액티브 영역을 확보하며 산화막을 이용한 스페이서 공정에 스페이서 식각 손상을 감소시키는 효과가 있다. 그리고 마스크용 산화막을 사용하지 않아도 됨으로 웨이퍼의 토포로지를 낮출 수 있다.The present invention provides a method of forming a self-aligned contact in a semiconductor device manufacturing process, the method comprising: forming a first insulating layer 22 on an entire structure of a wafer on which a lower conductive layer 21 is formed, and forming a first insulating layer 22 on the first insulating layer 22. (1) forming a material film (23) having an excellent etching selectivity with respect to the insulating film (22), and etching a predetermined portion of the material film (23) so that the material film (23) remains on the lower conductive layer (21). Forming a second insulating layer 25 on the entire structure, forming a self-aligned contact etch barrier material layer 26 on the entire structure, and etching the second and first insulating layer insulating layers 25 and 22. And removing the etch barrier material layer 26 and depositing an upper conductive layer material 27, wherein the self-aligned contact forming layer is prevented. Acid to secure the active area of the device A process using a spacer film has the effect of reducing the spacer etching damage. In addition, the topology of the wafer can be reduced by eliminating the need for a mask oxide film.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2A도 내지 제2E도는 본 발명의 일실시예에 따른 자기 정렬 콘택 형성 공정도.2A through 2E illustrate a process diagram for forming a self-aligned contact according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003890A KR950025876A (en) | 1994-02-28 | 1994-02-28 | How to form self-aligned contacts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003890A KR950025876A (en) | 1994-02-28 | 1994-02-28 | How to form self-aligned contacts |
Publications (1)
Publication Number | Publication Date |
---|---|
KR950025876A true KR950025876A (en) | 1995-09-18 |
Family
ID=66689607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940003890A KR950025876A (en) | 1994-02-28 | 1994-02-28 | How to form self-aligned contacts |
Country Status (1)
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KR (1) | KR950025876A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100443345B1 (en) * | 1997-12-30 | 2004-09-18 | 주식회사 하이닉스반도체 | Method for forming self-aligned contact of semiconductor device to remove stress and reduce contact resistance |
-
1994
- 1994-02-28 KR KR1019940003890A patent/KR950025876A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100443345B1 (en) * | 1997-12-30 | 2004-09-18 | 주식회사 하이닉스반도체 | Method for forming self-aligned contact of semiconductor device to remove stress and reduce contact resistance |
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