KR950021790A - MOSFET having self-aligned contact and manufacturing method thereof - Google Patents

MOSFET having self-aligned contact and manufacturing method thereof Download PDF

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Publication number
KR950021790A
KR950021790A KR1019930031834A KR930031834A KR950021790A KR 950021790 A KR950021790 A KR 950021790A KR 1019930031834 A KR1019930031834 A KR 1019930031834A KR 930031834 A KR930031834 A KR 930031834A KR 950021790 A KR950021790 A KR 950021790A
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South Korea
Prior art keywords
gate electrode
self
mosfet structure
source
forming
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KR1019930031834A
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Korean (ko)
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KR0138732B1 (en
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김재갑
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김주용
현대전자산업 주식회사
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Priority to KR1019930031834A priority Critical patent/KR0138732B1/en
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Publication of KR0138732B1 publication Critical patent/KR0138732B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 자기정렬형 콘택을 갖는 모스펫 구조 및 그 제조방법에 관한 것으로, 특히 하부의 소오스/드레인전극에 상부의 소오스/드레인 전극 연결선을 접속하면서 게이트 전극과는 절연시킬 때 상기 소오스/드레인전극에 형성되는 콘택과 게이트전극과의 간격을 최소화함으로써 모스펫 구조의 면적을 줄일수 있으며, 또한 게이트 전극이 활성영역과 필드영역의 경계선을 완전히 덮도록 하여 소오스/드레인 전극이 활성영역과 필드영역의 경계선에 형성되지 않도록 하는 방법에 관한 것이다.The present invention relates to a MOSFET structure having a self-aligned contact and a method of manufacturing the same, and in particular, when the upper source / drain electrode is connected to the lower source / drain electrode and insulated from the gate electrode, The area of the MOSFET structure can be reduced by minimizing the gap between the formed contact and the gate electrode, and the source / drain electrodes are formed on the boundary between the active and field regions so that the gate electrode completely covers the boundary between the active and field regions. It relates to a method of preventing the formation.

Description

자기정렬형 콘택을 갖는 모스펫(MOSFET)및 그 제조방법MOSFET with self-aligned contacts and method of manufacturing the same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 모스펫 구조를 나타낸 평면도.3 is a plan view showing a MOSFET structure according to the present invention.

제4A도 내지 제4C도는 본 발명에 따라 자기정렬형 콘택을 갖는 모스펫 구조의 단면도.4A-4C are cross-sectional views of a MOSFET structure with self-aligned contacts in accordance with the present invention.

Claims (3)

자기정렬형 콘택을 갖는 모스펫 구조에 있어서, 게이트 전극의 식각면이 상부의 층간절연막의 식각면과 같은 일직선상에 있으며 상기 게이트 전극과 층간절연막의 측벽에 절연막 스페이서가 있으며, 게이트전극이 활성영역과 필드영역의 경계선을 완전히 덮고 있어 소오스/드레인 전극이 활성영역과 필드영역의 경계선에 형성되지 않는 것을 특징으로 하는 자기정렬형 콘택을 갖는 모스펫 구조.In a MOSFET structure having a self-aligned contact, the etching surface of the gate electrode is in the same line as the etching surface of the upper interlayer insulating layer, and an insulating layer spacer is formed on the sidewalls of the gate electrode and the interlayer insulating layer, and the gate electrode is formed on the active region. A MOSFET structure having a self-aligned contact, wherein the source / drain electrodes are not completely formed at the boundary between the active region and the field region because the boundary of the field region is completely covered. 자기정렬형 콘택을 갖는 모스펫 구조 및 그 제조방에 있어서, 게이트 전극과는 절연되면서 소오스/드레인전극에 자기정렬형 콘택을 형성하여 모스펫 구조의 면적을 최소화하기 위해서 반도체기판 상부에 소자분리 산화막을 형성하는 게이트 산화막, 게이트 전극용 폴리실리콘 및 층간절연막을 형성한후, 콘택 감광용 패턴을 형성하는 공정과, 콘택 감광용 패턴을 이용하여 노출된 부분의 층간 절연막과 게이트 전극용 폴리실리콘을 식각한 후 소오스/드레인 전극을 형성하는 공정과, 폴리실리콘막과 가상 필드산화막을 제거하여 트렌치를 형성하는 공정과, 상기 식각된 층간절연막과 게이트 전극측벽에 절연막 스페이서를 형성하고 소오스/드레인 전극 연결선을 형성하는 공정을 포함하는 것을 특징으로 하는 자기정렬형 콘택을 갖는 모스펫 구조 및 제조방법.In a MOSFET structure having a self-aligned contact and a method of manufacturing the same, a device isolation oxide layer is formed on a semiconductor substrate to minimize the area of the MOSFET structure by forming a self-aligned contact on a source / drain electrode while being insulated from the gate electrode. Forming a gate oxide film, a polysilicon for a gate electrode, and an interlayer insulating film, forming a contact photosensitive pattern, and etching the exposed interlayer insulating film and the polysilicon for a gate electrode using the contact photosensitive pattern. Forming a source / drain electrode, removing a polysilicon layer and a virtual field oxide layer to form a trench, forming an insulating layer spacer on the etched interlayer insulating layer and the gate electrode side wall, and forming a source / drain electrode connection line And a MOSFET structure having a self-aligned contact comprising a process; Article methods. 제2항에 있어서, 게이트 전극이 호로성영역과 필드영역의 경계선을 완전히 덮고 있어서 소오스/드레인 전극이 활성영역과 필드영역의 경계선에 형성되지 않는 것을 특징으로 하는 자기정렬형 콘택을 갖는 모스펫 구조 및 그 제조방법.3. The MOSFET structure according to claim 2, wherein the gate electrode completely covers the boundary line between the femoral region and the field region so that the source / drain electrode is not formed at the boundary line between the active region and the field region. The manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031834A 1993-12-31 1993-12-31 Mosfet & mosfet manufacturing method KR0138732B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930031834A KR0138732B1 (en) 1993-12-31 1993-12-31 Mosfet & mosfet manufacturing method

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Application Number Priority Date Filing Date Title
KR1019930031834A KR0138732B1 (en) 1993-12-31 1993-12-31 Mosfet & mosfet manufacturing method

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KR950021790A true KR950021790A (en) 1995-07-26
KR0138732B1 KR0138732B1 (en) 1998-04-28

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