JPS60234352A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60234352A
JPS60234352A JP59089425A JP8942584A JPS60234352A JP S60234352 A JPS60234352 A JP S60234352A JP 59089425 A JP59089425 A JP 59089425A JP 8942584 A JP8942584 A JP 8942584A JP S60234352 A JPS60234352 A JP S60234352A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor chip
semiconductor device
terminal
corrosion resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59089425A
Other languages
English (en)
Inventor
Tatsuo Itagaki
板垣 達夫
Akira Suzuki
明 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59089425A priority Critical patent/JPS60234352A/ja
Publication of JPS60234352A publication Critical patent/JPS60234352A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05073Single internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05649Manganese [Mn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01025Manganese [Mn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 [技術分野] 本発明は、半導体装置に係り、特に、半導体装置の腐蝕
防止技術に適用して有効な技術に関するものである。
[背景技術] 半導体チップの外部端子とインナーリードとをボンディ
ングワイヤで接続した後に、それらを封止部(樹脂部)
で封止してなる半導体装置は、熱膨張率の違いでインナ
ーリードと封止部とに生じる微小な間隙から、外部端子
に不要な水滴が搬送されるという現象がある。
半導体チップの外部端子は、その内部集積回路の配線と
同一の金属材料、例えば、アルミニウムにより形成され
ており、前記不要な水滴によって断線等の電気的特性を
劣化させる腐蝕が生じる。
そこで、アルミニウムと耐腐蝕性の金属材料例えばニッ
ケルとの合金で外部端子を形成することが考えられる。
しかしながら、かかる技術における検討の結果、本発明
者は、半導体チップの形成工程では、外部端子と内部集
積回路の配線とが同一工程で形成されるので、耐腐蝕性
の金属材料の導入による配線抵抗の増加等、半導体装置
の電気的特性を劣化させるという問題点を見い出した。
また1本発明者は、外部端子を耐腐蝕性の良好な金で覆
うことについて考え検討したが、アルミニウムと金との
合金化は好ましくなく、それらの介在部に他の金属を介
在させ積層化する必要がある(たとえば、特開昭54−
128280号公報など)ので、製造工程の増加、材料
費の増加、設備の改善等、著しくコスト高になるとして
いる。
さらに、積層化した場合は、水滴の浸入を防止するため
に、それぞれの金属層の被着性を良好にする必要が生じ
る。
〔発明の目的] 本発明の目的は、耐腐蝕性を向上することが可能な技術
手段を提供することにある。
本発明の他の目的は、半導体装置において、半導体チッ
プの集積回路の配線抵抗値に著しい影響を及ぼすことな
く、耐腐蝕性を向上することが可能な技術手段を提供す
ることにある。
本発明の他の目的は、半導体装置において、著しいコス
トの増加をすることがなく、耐腐蝕性を向上することが
可能な技術手段を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。
[発明の概要コ 本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。
すなわち、半導体チップの少なくとも外部端子の表面部
に、耐腐蝕性の金属材料で合金化された領域を設けるこ
とにより、半導体チップの集積回路の配M抵抗値に著し
い影響を及ぼすことなく、半導体装置の耐腐蝕性を向上
することができる。
以下、本発明の構成について、実施例とともに説明する
本実施例は、本発明をフラットパッケージ型半導体装置
に適用したものである。
[実施例] 第1図は、本発明の詳細な説明するための半導体装置の
概略斜視図、第2図は、第1図のn −■切断線におけ
る断面図である。
なお、実施例の全回において、同一機能を有するものは
同一符号を付け、そのくり返しの説明は省略する。
第1図及び第2図において、1はタブ部であり、半導体
チップを搭載するためのものである。
2はリードであり、半導体チップと外部装置とを電気的
に接続するためのものである。2Aはインナーリードで
あり、2Bはアウターリードである。
3はタブ部1に搭載されて設けられた半導体チップであ
り、論理機能、メモリ機能等を有するものである。
4はその一端が半導体チップ3の外部端子(図示してい
ない)に接続されその他端がインナーリード2Aに接続
されて設けられたボンディングワイヤであり、それらを
電気的に接続するためのものである。
5はタブ部工、インナーリード2A、半導体チップ3及
びボンディングワイヤ4を封止して設けられた樹脂から
なる封止部であり、主として半導体チップ3を外部雰囲
気及び外部応力から保護するためのものである。
次に、半導体チップに設けられた外部端子について、具
体的に説明する。
第3図は、外部端子部分における半導体装置の要部断面
図である。
第3図において、6は半導体基板、7は半導体素子(図
示していない)間を電気的に分離するフィールド絶縁膜
、8は半導体素子とその上部に設けられる導電層とを電
気的に分離する絶縁膜である。
9は半導体チップ3の製造工程における第1層目の配線
形成工程により絶縁膜8上部に設けられた導電層であり
、内部集積回路の配線9Aと、内部集積回路と外部機器
との電気信号を入出力するための外部端子9Bとを構成
するためのものである。この導電層9は、低抵抗値を有
し電気信号の伝播速度を向上するために、例えば、アル
ミニウム又はエレクトロマイグレーションを防止するア
ルミニウムシリコンの金属材料により形成すればよい。
10は導電層9を覆うように設けられた絶縁膜であり、
主として外部雰囲気から導電層9を保護するためのもの
である。
10Aは外部端子9B上部の絶縁膜10を選択的に除去
して設けられた開口部であり、外部端子9Aとボンディ
ングワイヤ4とを電気的に接続するためのものである。
11は開口部10Aから露出する外部端子9B上部に被
着して設けられた金属層であり、外部端子9Bの耐腐蝕
性を向上するためのものである。
この金属層11は、耐腐蝕性を向上するように、パラジ
ウム、金、ニッケル、マンガン等を用いればよい。
11Aは外部端子9Bの表面部にその他の金属材料によ
り合金化されて設けられた合金化領域であり、耐腐蝕性
を向上するためのものである。合金化領域11Aは、前
記金属層11を形成し、例えば、400[°C]程度の
熱処理を施して金属層11の一部を外部端子9Aの表面
部に拡散して形成されたものであり、前記金属層11の
あるないにかかわらず、例えば、0.05 [μm]程
度の深さで形成すれは、充分に耐腐蝕性を向上すること
ができる。
また、第4図及び第5図に示すように、前記金属層11
を完全に合金化領域11B、IIGに可変させてもよい
第4図は、外部端子9Bの表面部に合金化領域11Bを
形成した例、第5図は、外部端子9Bの略全部に合金化
領域11Cを形成した例であり、どちらも前記第3図に
示す例に比べ、ボンディングワイヤ4を接続する際のボ
ンダビリティが良好である。
また、第4図に示す例は、第5図に示す例に比べ、合金
化による抵抗値の増加は小さくなっている。
[効果] 以上説明したように、本願において開示された新規な技
術手段によれば、以下に述るような効果を得ることがで
きる。
(1)、半導体チップの少なくとも外部端子の表面部に
、耐腐蝕性の金属材料で合金化された領域を設けること
により、その内部集積回路の配線抵抗値に著しい影響を
及ぼすことなく、半導体装置の耐腐蝕性を向上すること
ができる。
(2)、半導体チップの少なくとも外部端子の表面部に
、耐腐蝕性の金属材料で合金化された領域を設けること
により、積層化する場合に比べ、製造工程の増加、材料
費の増加、設備の改善等、著しくコスト高をすることな
く、半導体装置の耐腐蝕性を向上することができる。
(3)、半導体チップの少なくとも外部端子の表面部に
、耐腐蝕性の金属材料で合金化された領域を設けること
により、積層化することによって生じるそれぞれの金属
層の被着性を考慮する必要がなく水滴の浸入がないので
、半導体装置の耐腐蝕性を向上することができる。
以上、本発明者によってなされた発明を前記実施例にも
とづき具体的に説明したが、本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて、種々変形し得ることは勿論である。
【図面の簡単な説明】
第1図は、本発明の詳細な説明するための半導体装置の
概略斜視図、 第2図は、第1図の■−■切断線における断面図、 第3図乃至第5図は、外部端子部分における半導体装置
の要部断面図である。 図中、1・・・タブ部、2 ・リード、2A・インナー
リード、2B・・アウターリード、3・・半導体チップ
、4・・・ボンディングワイヤ、5 封止部、6・・半
導体基板、7・・フィールド絶縁膜、8.lO・・・絶
縁膜、9・・・導電層、9A・・・配線、9B・・・外
部端子、IOA・・・開口部、11・・・金属層、II
A。 11B、IIC・・・合金化領域である。 第 1 図 第 2 図 第 3 図 第 4 図 ○ 第 D 図

Claims (1)

  1. 【特許請求の範囲】 1、その内部集積回路に使用される配線と同一の第1の
    金属材料で形成された外部端子を有する半導体チップが
    、封止部により封止されてなる半導体装置であって、少
    なくとも前記外部端子の表面部に、その他の第2の金属
    材料により合金化された領域を具備してなることを特徴
    とする半導体装置。 2、前記合金化された領域は、耐腐蝕性を向上するため
    のものであることを特徴とする特許請求の範囲第1項記
    載の半導体装置。  3、前記第1の金属材料は、アルミニウム又はその合金
    からなり、前記第2の金属材料は、パラジウム、金、ニ
    ッケル、マンガン等からなることを特徴とする特許請求
    の範囲第1項又は第2項記載の半導体装置。
JP59089425A 1984-05-07 1984-05-07 半導体装置 Pending JPS60234352A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59089425A JPS60234352A (ja) 1984-05-07 1984-05-07 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59089425A JPS60234352A (ja) 1984-05-07 1984-05-07 半導体装置

Publications (1)

Publication Number Publication Date
JPS60234352A true JPS60234352A (ja) 1985-11-21

Family

ID=13970302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59089425A Pending JPS60234352A (ja) 1984-05-07 1984-05-07 半導体装置

Country Status (1)

Country Link
JP (1) JPS60234352A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235212A (en) * 1988-03-18 1993-08-10 Kabushiki Kaisha Toshiba Semiconductor device having a mechanical buffer
EP2273542A3 (en) * 2001-12-14 2011-10-26 STMicroelectronics S.r.l. Semiconductor electronic device and method of manufacturing thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235212A (en) * 1988-03-18 1993-08-10 Kabushiki Kaisha Toshiba Semiconductor device having a mechanical buffer
EP2273542A3 (en) * 2001-12-14 2011-10-26 STMicroelectronics S.r.l. Semiconductor electronic device and method of manufacturing thereof

Similar Documents

Publication Publication Date Title
JP4676640B2 (ja) インテリジェントパワーモジュールパッケージ
US5300461A (en) Process for fabricating sealed semiconductor chip using silicon nitride passivation film
KR970010678B1 (ko) 리드 프레임 및 이를 이용한 반도체 패키지
US7473584B1 (en) Method for fabricating a fan-in leadframe semiconductor package
KR870000350B1 (ko) 다측 배선(多重配線)구조를 가진 전자장치(電子裝置)
US4394678A (en) Elevated edge-protected bonding pedestals for semiconductor devices
JPH05226339A (ja) 樹脂封止半導体装置
US20230238317A1 (en) Semiconductor device, method of manufacturing semiconductor device, and module
JPS60234352A (ja) 半導体装置
JP2674567B2 (ja) 半導体装置
JPH01261850A (ja) 樹脂封止型半導体装置
JP3200488B2 (ja) 樹脂封止型半導体装置及びその製造方法
JPH04283950A (ja) 樹脂封止型半導体装置
US20080251907A1 (en) Electronic Device With Stress Relief Element
JPS604248A (ja) 半導体装置
JP2972679B2 (ja) リードフレーム並びに樹脂封止型半導体装置及びその製造方法
JPH07135203A (ja) 半導体装置
JPH07249727A (ja) 半導体装置
JPH04306837A (ja) 樹脂封止型半導体装置
JPH0621061A (ja) 半導体装置
JP2745887B2 (ja) 樹脂封止型半導体装置
JPH08288447A (ja) リードフレーム
JPH0290637A (ja) 半導体集積回路装置
JP2720863B2 (ja) 半導体集積回路装置
JP2845002B2 (ja) 半導体装置用複合リードフレーム