JPS60224356A - Bus circuit - Google Patents

Abstract

PURPOSE:To enhance the data transmission speed of a large scale integrated circuit by providing a small quantity of additional circuit in a bus circuit and reducing the delay of data. CONSTITUTION:When a precharging signal 9 goes to the high level, the output point of a bus line rises after a delay due to the output impedance of a P- channel transistor TR4 itself. When the precharging signal 9 goes to the low level, either of output buffers 1 and 12 outputs data to the bus line. If data outputted at this time is in the high level, the level of the bus line is not changed from the high level. If output data from the output buffer 1 or 12 is in the low level, the fall is slow; but the level of an output point 15 reaches a threshold A of an inverter 6 of an additional circuit 10, the inverter 6 outputs the high level, and it falls quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a bus circuit, and particularly to a bus circuit used in an integrated circuit or the like.

(Prior art) (hereinafter referred to as L19I) has a high integration rate and its functions are also becoming higher. Also, along with this, the data bus inside the LSI,
Internal path lines such as address buses are becoming larger in distributed resistance 1 distribution volume and load capacity jitI#. Especially when the pass line intersects with the power line, ground line, or other wiring, the pass line is changed from aluminum wiring to polysilicon or diffusion layer wiring, but the resistance and capacitance of this polysilicon and diffusion layer are compared to aluminum wiring. and grow bigger. As the capacitance and resistance increase as described above, the data delay of the pass line increases, resulting in a problem that the data transmission speed of the LSI decreases.

Conventionally, methods to improve this have been considered to reduce the data delay by lowering the resistance and capacitance of the pass line, increasing the drive capacity of the output buffer, and the like. However, in order to lower the resistance of the pass line, it is possible to change the wiring material from aluminum, which has a medium resistance, to gold, which has a lower resistance, but this will increase the cost, and also increase the wiring width and capacitance. , LSI with multilayer wiring in the nest
There were drawbacks such as an increase in the number of manufacturing steps. On the other hand, in order to reduce the capacitance of the pass line, there is a drawback that if the interlayer film is made thicker to increase the spacing between the healds, manufacturing problems will occur such as increasing the level difference between layers and through holes. Ta. Furthermore, increasing the drive capacity of each output buffer on the pass line will not only increase the area of the chip, but also increase the output capacity of the output buffer itself. The disadvantage is that it is not effective in reducing data delay.

(Object of the Invention) The object of the present invention is to solve the above-mentioned drawbacks by adding a small number of circuits to the conventional bus circuit, and to provide a bus circuit that can reduce the delay of the line C>data. It's in particular.

(Structure of the Invention) According to the present invention, photoelectric means for precharging the pass line to a first level in synchronization with the M l (Di bus);
The pass line reset in the first 1J is the second
The bus circuit is characterized by comprising a temporary memory device that is set when the level is reached, and an output device that outputs a third level to the pass line when the temporary memory device is set to the level δ. Ru.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the bus circuit of the present invention, and FIG. 2 is a waveform diagram showing a simplified example of the operating waveforms in FIG. 1. It should be noted that a pass line such as a data bus is usually composed of a plurality of lines, and FIG. 1 only shows a portion of one of them.

In FIG. 1, the bus circuit includes output buffers 1 and 12 that output data to the pass lines, input buffers 2 and 13 that input data on the pass lines, and a P channel MO8).
transistor (hereinafter referred to as PTr) 4, N-channel MO8) transistor (hereinafter referred to as NTr) 8, inverters 5 and 6,
Consisting of R-87 lip 70 tube (hereinafter referred to as R-8FF) 7, the circuit curved with diagonal lines, that is, inverter 6, R-8FF
7 and N-'rrs is an additional circuit 10 added to the conventional bus circuit according to the present invention. Reference numerals 3 and 11 are equivalent distributed capacitance resistances that isometrically represent the distributed capacitance and distributed resistance of the pass line, reference numeral 9 is a precharge signal of the pass line, and reference numeral 14 is
, 15 and 16 are the output buffers 7 and 1 on the pass line, respectively.
output point, output point of the additional circuit 10, input buffer 130
Indicates the input point.

Next, the operation of this embodiment will be explained in detail using FIGS. 1 and 2.

When the precharge signal 9 becomes high level (hereinafter referred to as H level), the R-8FF7 is reset and the NTr8 is turned off. At the same time, the P-Tr4 is turned on, precharging the pass line to the power supply potential VCC level, that is, the H level.

As shown in Fig. 2, the rise of the pass line is delayed by the output impedance (on-resistance) of the P-Tr4 itself at the output point 15 on the pass line.
, - At the output point 14 and input point 16 of the bus line, the rise 9 is delayed because the delay caused by the equivalent distributed capacitance resistors 3 and 11 is added to the delay at the output point 15, respectively. The pass line only needs to reach the power supply potential VCC level before the precharge signal 9 becomes low level (hereinafter referred to as L level).

Next, when the precharge signal 9 reaches the L level, the output buffer 1, 120 outputs data to the furnace cover line. If the data to be output at this time is at H level, it is the same as the precharge level, so the level of the pass line remains at H level and does not change. Therefore, there appears to be no delay in the pass line when the output buffer outputs H level data.

Next, a case where the output data from the output buffer is at L level will be explained. The operating waveforms in FIG. 2 show a case where the output buffer 1 outputs L level data and the input buffer 13 inputs data. When output buffer 7 outputs L level data, output point 14 on bus line
Then, the signal falls with a delay due to the output impedance of the output buffer 1 itself. Also, output point 15 on the pass line
Then, the delay caused by the equivalent distributed capacitance grinding resistor 3 is added to the delay at the output point 14. Furthermore, at the input point 16 on the pass line, the fall is delayed due to the delay caused by the equivalent distributed capacitance resistor 11 added to the delay at the output point 15.

If the threshold value of the inverter 6 of the additional circuit 10 is level A (shown in FIG. 2), the output point 150
When the level reaches level A, inverter 6 outputs H level and R-8)'F7 is set. This R-8F
When F7 is set, N-Tr8 is turned on and outputs the earth level, that is, L level, to the output point 15. As a result, the number output point 15 is not only discharged in the output buffer l as before reaching the level A, but also N T
Since r8 is also discharged, it falls rapidly with only a delay determined by the output impedance of NTr8. In FIG. 2, the broken line of the output point 150 waveform is 1! when there is no additional circuit 10! The case of a conventional bus circuit is shown below.

In addition, before the level of the output point 15 reaches the level A, the input point 16 receives the L level output from the output buffer 1 with a delay equal to the sum of the equivalent distributed capacitance resistors 3 and 11, and falls. However, the output point 15
After reaching the level AK, the output point 15 becomes NTr8.
But since it is discharged, it is simply the equivalent distribution capacity fish resistance 1
It falls only with a delay due to 1. In FIG. 2, the broken line of the waveform at the input point 16 shows the case without the additional circuit 10.

Assuming that the threshold of the input buffer 13 is at the same level as the threshold of the inverter 6, the fall will be faster by the time t (shown in FIG. 2) than in the case where the additional circuit 10 is provided. .

In this embodiment, the threshold value of the input of the inverter 6 and the threshold value of the input of the input buffer 130 have been explained as being at the same level. By doing so, the fall of the pass line can be made even faster.

(Effects of the Invention) As explained above, according to the bus circuit of the present invention, by providing a slight biasing path in the conventional bus circuit, the fall of output data due to the distributed capacitance 1 distributed resistance of the bus line, etc. In other words, since data delays can be reduced, an effect will be produced as LSI data transmission devices become faster.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the bus circuit of the present invention, and FIG. 2 is a waveform diagram showing a simplified example of the operating waveforms in FIG. 1. In the figure, 1.12・old...output buffer, 2゜13
°°°°°° Input voltage, 3, 11...Equivalent distributed capacitance resistance, 4...P channel ML) 8) Ransistor, 5.6......r patterner ,7・old・
・R-87 lip flop, δ...rJ Nail MOS transistor, 9...Precharge 1
One side, 1o...Additional circuit, 14.15...
...Output point, 16...Input point. Figure 2

Claims (1)

[Claims] charging means for precharging the pass line to a first level in synchronization with a first signal; temporary storage means that is reset by the first signal and set when the bus line reaches a second level; and output means for outputting a 30th level to the pass line when the means is set.