AU593382B2 - Bandwidth expanding arrangement - Google Patents

Description

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St it 0.000 00 to 0 00(1 o 0 4044- 040044 4 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED "BANDWIDTPH EXPANDING AR~RANGEMIENT" The following statement is a full description of this invention, including the best method or performing it known to us:- This invention relates to a circuit arrangement comprising two successive stages interconnected by a signal line in which the bandwidth is limited between the two stages by finite internal resistances and unavoidable capacitances.

Nearly every electric circuit arrangement is subject to the aforementioned limitations. Exceptions are mainly filters in which the bandwidth is limited by selective measures. In principle, however, the bandwidth of every electric circuit arrangement is limited by the upper cutoff frequency. The problem of limited bandwidth is of such fundamental importance that a multitude of solutions has been provided. In the field of digital S logic circuits, for example, there are several circuit families which pertit 4, 1, form the same logic functions but differ in their bandwidths, among other tt 0 things. In threshold regions, however, this problem always plays a major role. In an integrated circuit, for example, the longitudinal resistance of a line, and thus also of a channel in a transistor, can be reduced by increasing the cross section of the line. The capacitance is increased in the same measure, however, so that the product of resistance and capacitance will remain unchanged. However, since the longitudinal resistance of a line and a shunt capacitance form a low-pass filter whose cutoff

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frequency depends on the product of resistance and capacitance, the bandwidth cannot be increased by such geometric measures. This problem becomes Seven more critical in a bus circuit, where a plurality of driver circuits is connected to a cormion signal line. To ensure proper operation, all I driver circuits but one must be disabled. The capacitances of the disabled driver circuits thus constitute an additional load for the non-disabled driver circuit. The capacitances of the signal line itself and of the sig- I nal inputs connected thereto are of secondary importance. A broadband switching module in which a connection between one of several inlets and one of several outlets car'_be established via each of a plurality of crosspoints has one such bus circuit per outlet and one driver circuit per inlet

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and bus circuit. The bandwidth of such a broadband switching module thus depends directly on the number of inlets. With a given technology and for a given bandwidth, the size of the switching network is thus fixed if no steps can be taken in the respective technology to increase the bandwidth.

The present invent ion remedies this. Acco2J-."ingly there is provided a circuit arrangement comprising two successive stages interconnected by a signal line, wherein the bandwidth is limited between the two stages by finite internal resistances and unavoidable capacitances, wherein to increase the bandwidth, a resistor is inserted between the signal line and a point of fixed potential.

By inserting a resistor between the signal line and a point of fixed :potential, the internal resistance is shunted by a resistance to provide a ',:path for alternating current, so that the resistance of the low-pass filter is effectively reduced, thereby increasing the bandwidth. To allow for (-nonlinearities, the fixed potential is preferably chosen tos lie in the middle of the supply voltage, in the case of analog circuits at the operating point. If a second resistor connected to a second point of a different pot.4 r t t tential is added, a voltage divider is obtained with which both the effective resistance and a potential which does not, as far as possible, affect the operation of the circuit can be adjusted. Especially in integrated circuits, the resistors will preferably be implemented with transistors.

SThe measure in accordance with the invention does not only have advantageous effects, of course. On the one hand, it results in additional power consumption; on the other hand, it reduces the signal swing, since the gain-bandwidth product Is constant. The use of transistors has the advantage that they can be turned off if thi's portion of the circuit is not needed, and that adaptation to the actually needed bandwidth is possible by changing the biasing. Because of the reduction of the signal swing and the possible additional interference associated therewith, however, such a measure should be taken only where absolutely necessary, between those two stages in a signal path between which the bandwidth is limited most. In a broadband switching module in which a signal travelling from an inlet to an outlet, besides passing through the switching network proper, goes through a number of signal-conditioning and monitoring circuits, such as input and output isolation amplifiers and synchronizers, the greatest bandwidth limitation occurs in the bus circuits connected to a common outlet, as described above.

Embodiments of the invention will now be described with reference tr.

the accompanying drawings, in which: Fig. 1 is an equivalent circuit diagram serving to explain the operation of the circuit arrangement in accordance with the invention; Figs. 2 to 5 show embodiments of circuit arrangements in accordance :with the invention; V I6 Fig. 6 is a block diagram of a broadband switching module designed in te accordance with the invention, and Fig. 7 shows the switching network of the broadband switching module of Fig. 6. It comprises a number of bus circuits in accordance with the invention.

First, the fundamental idea of the invention will be explained with the aid of Fig. 1. A transmit section S is connected to a receive section E by a signal line L. The transmit section S and the receive section E are to 9two arbitrary successive stages in a signal path. The transmit section S is characterized by an internal resistance Ri and a voltage generator uo.

The voltage generator uo is illustrated in the drawing as a digital-signal source. The receive section E is characterised by an input resistance Re.

It will be assumed that the signal line L is so short that it need not be terminated in a resistance equal to the characteristic impedance of the line. In such cases, the input resistance Re Is greater than the internal resistance Ri by orders of magnitude. The output of the transmit section S, the input of the receive section E, and the signal line L have unavoidable capacitances, which are drawn in Fig. 1 as a grounded capacitance C.

It is obvious that the internal resistance Ri and the capacitance C form a low-pass filter. The input resistance Re is connected in parallel with the internal resistance Ri to allow the flow of alternating current and, in principle, does not alter the fact that a low-pass filter is present.

According to the invention, the internal resistance Hi is shunted by an additional resistance Ha to provide a path for alternating current. In principle, that does not change the low-pass response; however, -the upper cutoff frequency and, consequently, the bandwidth can thus be increased significantly. This basic circuit also shows, however, *that the signal swing is reduced by this measure. The internal resistance Hi, the iresist- 0 0 ance Ha, and the practically negligibly high input resistance Re form a p44 voltage divider. A considerable portion of the signal voltage drops across 0000* the internal resistance Hi and has no effect in the receiving section E.

It is thus apparent that this measure is a makeshift and should not be used without reflection.

Between the resistance Ha and ground, an auxiliary voltage source UB 4 is inserted. This auxiliary voltage source UII, a DC voltage source, has no .44influence on the frequency response of the circuit arrangement. The resistance Ha may be connected to any point of fixed potential. Especially suited are the existing ground and supply-voltage potentials. In order not to influence the DC voltage conditions or to set an operating point, the fixed potential may also lie in the middle of the supply voltage. This is of importance particularly if the circuit arrangement is nonlinear.

Fig. 2 shows a practical embodiment of the basic circuit of Fig. 1.

The transmit section contains a driver circuit which coneists of two transistors TS1 and Wd2 and is connected between the supply voltage VDD and ground. The two transistors TS1 and TS2 are biased together, one of them being on and the other off. The receive section S contains a similar input circuit connected between the supply voltage VDD and ground and consisting r- of two transistors TE1 and TE2 which are biased by the output from the transmit section S via the signal line L. The resistor Ra is connected in this example to half the supply voltage VDD/2.

How this half supply voltage VDD/2 is generated is not shown in this example. An auxiliary voltage of VDD/2 generated for several like circuit arrangements in common is sometimes undesirable because of the necessary wiring and of possible cross-coupling via the internal resistance of the auxiliary voltage source.

Fig. 3 shows a slight modification of the example of Fig. 2. The resistor Ra has been divided into two resistors Rl and R2, one of which is grounded, while the other is connected to the supply voltage VDD. In this manner, the auxiliary voltage can be influenced via the res3tance ratio of the resistors R1 and R2, and the bandwidth via the absolute value of the two resistors.

Fig. 4 shows a modification of the circuit of Fig. 3 for the case where the circuit arrangement is part of an integrated circuit, which is of S great practical importance. In that case, the resistors RI and R2 are implemented with transistors, too, which are designated Tal and Ta2. The two transistors are biased by a DC voltage Usl and a DC voltage Us2, respectively; the two voltages may be fixed or adjustable from outside, so that the reduction of the signal swing and the dissipation in the transistors Tal and Ta2 can be kept to a minimum depending on the application.

Fig. 5 shows another embodiment which combines features of the embod- Siment of Fig. 2 and features of the embodiment of Fig. 4. The resistor Ra of Fig. 2 has been replaced by two transistors Tal and Ta2 in parallel.

These transistors are biased by voltages of opposite polarity with the aid of an inverter (not shown), so that both are simultaneously on or off.

With this circuit arrangement, only a changeover can be effected, which is sufficient for many practical cases.

9 9 Fig. 6 shows a block diagram of a broadband switching module with 16 inlets El to E16, 16 extensions inlets EXi to EXl6, a clock input TE, a clock output TA, 16 outlets Al to A16, and a control bus BUS. The signal paths run through input isolation amplifiers 3 into the Interior of the broadband switching module, and through output isolation amplifiers 4 outwards. The signals received through the inlets El to E16 are synchronized in an input synchronizer 1, and before leaving the broadband switching module, they are synchronized again in an output synchronizer 2. The extension inlets EXl to EX16 are connected to outlets Al to A16 of a spatially immiediately preceding switching module. Therefore, their signals need not be synchronized. Th heart of thq broadband switching module is a switching matrix K. The output of the switching matrix K is followed by a monitoring device 5, which permits 16 output signals to be monitored. A decode and control logic 6 ie provided for controlling the switching matrix K and for 9 performing the monitoring function with the aid of the monitoring device The switching matrix K will now be explained in more detail with the aid of Fig. 7.

ii The switching matrix K consists of rows and columns, with each row associated with one of the outlets Al to A1l6, and each column with one of the inlets El to E16 or one of the extension inlets EXl to EX16. At each intersection of a column and a row, a crosspoint K0l01 to K1616 is provided. Each crosspoint includes two pairs of -transistors, one of which is biased by a signal St, wnile the other is biased by the signal coming from the associated inlet. The bias signal is inverted in each crosspoint, so that both transistors of the associated transistor pair are either simultaneously on or simultaneously off. Thie bias signal St comes from the decode and control logic 6. It determines which of the inlet signals is switched to a given outlet. The second transistor pair is biased with signals of equal polarity, so that, because of the opposite polarities of 30 the two transistors, one of them is on and the other off. Similar cross- 0 points KX1 to KX16 are located where a column coming from the extension inlets EX1 to EX16 intersects the row going to the associated outlet. Paths can thus be established from the extension inlet EX1 to the outlet Al, from the extension inlet EX2 to the outlet A2, etc. Each row running to an outlet thus forms a bus circuit consisting of a number of crosspoints, a signal line LI to L16, and the input of the following device. Each crossing forms a driver circuit. One driver circuit at the most is active, while all others are disabled and represent a capacitive load for the active driver circuit. Via the associated extension inlet, which may be connected to the associated outlet of a preceding broadband switching module, a plurality of further inlets may be indirectly connected to this circuit without appreciably loading the latter. This represents one possibility of increasing the number of inlets at a given bandwidth. The invention pro- 4 4a vides a further possibility of increasing the number of inlets at a given bandwidth. This is equivalent to the possibility of increasing the bandwidth if the number of inlets is fixed. To do this, an additional resistor 'I is inserted, as shown in the previous embodiments. This is illustrated in Fig. 7 by the circuits designated as resistances R1 to R16. The bias i, signals St can be used here primarily to make this circuit high impedance when the outlets are inactive.

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Claims (9)

1. A circuit arrangement for increasing the transmission speed limit over a signal line, the arrangement comprising a first stage including a plural- ity of driver circuits connected to the signal line, in which no more than one if the driver circuits is active at any one time, the inactive driver circuits acting as capacitive loads on the signal line, wherein a select- able resistance means selected according to the 'transmission speed connects the signal line to a selected potential at least for the duration of the 'transmission.

2. An arrangement as claimed in claim 1 wherein the selectable resistance ~'means comprises a pair or series connected resistances connected across a voltage source, the signal line being connected to the junction of the pair ~of resistances.

3. An arrangement as claimed in claim. or claim 2 wherein each driver circuit Is a crosspoint comprising a first pair of series connected tran- sistor switches in series with a second pair of transistor switches, the r transistors of the first and second pair being arranged to have one tran- sistor per pair on either side of a mid-point, the mid-points of each t t crosspoint being connected to the signal line.

4. An arrangement as claimed in claim 3 wherein the first pair of tran- *sistors are controllable by a respective line control signal so that no *more than one said first pair is active at any one time, and wherein each second pair of transistors is controllable by an input signal from a re- spective input.

An arrangement as claimed In any one of claims I to 4 wherein the se- lectable resistance means comprise one or more transistors.

6. An arrangement as claimed in olaim 5 wherein the value of the resist- ance is selected by changing the biassing of the transistors.

7. A signal line arrangemwent as herein described with reference to the accompanying drawings. 104 -N, C)

8. A broadband switching module coiprising a plurality of inputs and a plurality of outputs, a matrix of rows of crosspoints each row comprising an arrangement as claimed in claim 4, claim 7, or claim 5 as appended to claim 4.

9. A switching module as claimed in claim 8 wherein each input controls the crosspoints of a respective column of the matrix, and wherein the sig- nal lines comprise the plurality of outputs. A switching module as herein described with reference to the accompa- 4 nying drawings. DATED THIS SIXTEENTH DAY OF NOVEMVBER 1989 ALJCATEL N.V. t (t~ t f t t I I 44'