JPS59108430A - Binary-ternary value converting circuit - Google Patents

Abstract

PURPOSE:To make an intermediate level generating section stable against load fluctuation and to use the section in common to other circuits by regulating the intermediate level potential to a constant voltage by an operational amplifier and connecting the operational amplifier to an upper and a lower level generating circuit via a gate. CONSTITUTION:An output of FETs 9, 10 is at ''L'' when inputs I1, I2 are (phi, phi), at ''H'' when (11) and at a high impedance state when at intermediate levels (01), (10). On the other hand, a potential, VCC (H) is split by resistors 15, 16, and an intermediate level potential regulated into a constant voltage and extracted by the operational amplifier 11 whose output voltage is fed back to an inverting input is outputted to an output terminal OUT via transfer gate 12, since an NAND gate 13 goes to ''L'' when the inputs I1, I2 go to (01). Further, when the input is at (10), since the transfer gate 12 is also closed, the high impedance state is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a binary-to-ternary conversion circuit that converts a binary data signal into a ternary data signal.

Configuration of conventional example and its problems Figure 1 shows a conventional binary-to-ternary conversion circuit.
1 is inverter, 2 is input NOR gate, 3 is PMO3
) transistor (hereinafter referred to as PMOSTr), 4 is NMO8) transistor (hereinafter referred to as NMOSTr)
, 6.6 is resistance, ■1. I2 is the first . second 2
Value data input and OUT are ternary data outputs.

Inverter 1 inputs the first binary data 1, applies the output to the gate of P MOS T r 3, and
OR gate 2 receives first and second binary data input ■1°I2
is input, and the output is applied to the gate of NMO8Tr4. In addition, the source of PMO3Tr3 is connected to the power supply 3 S - Vcc, and the drain is connected to the drain of NMOS Tr 4, from which output is obtained, the source of NMOS Tr 4 is grounded, and the resistor 5 is connected to the power supply Vcc and the output terminal OU.
Between T.

A resistor 6 is connected between the output terminal OUT and ground.

In FIG. 1, 1. Second binary data input ■1. ■
When both inverters 1 and 2 are at low level °'L''', inverters 1 and U
The outputs of OR gate 2 are both at high level ``H''.

Therefore, PMO8Tr3 is non-conductive, and NMOS Tr3 is non-conductive.
4 is conductive. At this time, the output 0UTid, "L
”.Data human power 11.I2 is °゛L”“,“
When °H°゛, inverter 1.

The outputs of NOR gate 2 are respectively...H", "L"
・So both NMOS T r 4 become non-conductive.

At this time, the output UT becomes the intermediate potential "M"' divided by the resistors 5 and 6. When the first binary data input 11 is H'' and the second binary data input is H' or L, the outputs of the inverter 1 and NOR gate 2 are both L,
PMO8Tr3. NMO8Tr4 becomes conductive and non-conductive, respectively. At this time, the output OUT reaches ``H''.

In this way, binary data input 11. Data of 2-3 values can be output according to I2.

However, the conventional binary-to-ternary conversion circuit has the following problems. That is, PMO3Tr.

When both NMOS T r are in a non-conducting state and output the level of the intermediate potential 11M'' which is divided by the resistance, this "M'" level varies depending on the value of the load resistance connected to the output terminal 0UTK. .In order to reduce this drawback, the values of the resistors 5 and 6 can be reduced, but in this case, the current consumed by the resistors 5 and 6 increases.Moreover, multiple binary-to-ternary conversion circuits are required. If , °“Ml+
Since each circuit requires a resistor to generate a level, current consumption also increases by the number of circuits.

purpose of invention In view of the above-mentioned problems, the present invention provides M'' depending on the load.

The object of the present invention is to provide a binary-to-ternary conversion circuit that has little level fluctuation and can share an "M" level generation section when a plurality of binary-to-ternary conversion circuits are used. .

Structure of the Invention Page 6 The present invention consists of a PMO8Tr, NMOS Tr that outputs "H", ", L" level, an operational amplifier that outputs "M" level, and a PMOS Tr, NMOS Tr that outputs "M" level.
This is a binary-to-ternary conversion circuit consisting of a first logic circuit that controls ON/OFF of MOS TR, a second logic circuit that controls the "M" level output, and a transfer gate. By using an operational amplifier and a transfer gate, This suppresses fluctuations in the "1M+" level due to load, and also allows the 11h7[1 level generating circuit to be used in common when a plurality of binary-to-ternary conversion circuits are used.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a binary-to-ternary conversion circuit according to a first embodiment of the present invention. In Figure 2, 7 is an inverter, 8 is 2
Manual NOR gate, 9 is PMO3Tr110 is NMOT
r, 11 is an operational amplifier, 12 is a transfer gate, 13 is a two-person NAND data 1, 14 is an inverter,
15.16 is the resistance.

11112 Ha No. 11 No. 2 (7) Binary Chi 1-manpower fO
UTll-11, ternary output.

The operation of the binary-to-ternary conversion circuit configured as described above is 1.
The work is explained below.

Data human power 11. Both I2 are “L”, output OUT is II L H, data input I, I2 is “H”, H”
' or "H".

The operation when the output is "H" at "L" is the same as the conventional example. Data input ■11■2 is par L''', °“
When H''', PMOS T 瓜NMO8 as in the conventional example
Both T r 10 are non-conductive. At this time, NAND
Gate 13 is II L II, inverter 14 is °°H
'', the transfer gate 12 becomes conductive and the output OUT becomes the intermediate potential divided by the resistors 15 and 16 at the level ``M''.

As described above, according to this embodiment, since the "M" level is generated by the operational amplifier, the variation in the "Ml+ level due to the load is small, and the current consumption by the resistors 15 and 16 can also be reduced.Furthermore, The transfer gate connects and disconnects the output terminal and the "Ml+ level generation circuit," so when multiple ternary output circuits are required, the "M" and "M" generation circuits can be shared, reducing the number of elements. , current consumption can be reduced.

FIG. 3 shows a binary-to-ternary conversion circuit showing a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 2 is that the inverter 7 is replaced by a data input 11. The point is that a two-man powered NOR gate 1 is provided to input I2.

In the second embodiment configured as described above, the difference from the first embodiment is that the data input I, I2 is "°L",
, IIHI+, the NAND gate 17 is “'H”
″′.

NOR gate 8 outputs °゛L''', PMO8Tr9
゜NMO3Tr10 are both non-conductive, the NAND gate 13 outputs "H'', the inverter 14 outputs °'L"', the transfer gate 12 is also non-conductive, and the output OU
The point is that T can be placed in a high impedance state.

As described above, in this embodiment, by providing the NAND gate 17, it is possible to create an impedance state in addition to the three-value output.

Effects of the Invention By newly providing an operational amplifier and a transfer gate, the binary-to-three-value conversion circuit of the present invention can suppress fluctuations due to load in "°M" level, making it possible to easily convert binary to three-value conversion circuits.
When a plurality of three-value conversion circuits are used, the "M" level generation circuit can be shared, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is an electrical connection diagram of a conventional binary-to-ternary conversion circuit, FIG. 2 is an electrical connection diagram of a binary-to-ternary conversion circuit according to the first embodiment of the present invention, and FIG. 3 is an electrical connection diagram of a conventional binary-to-ternary conversion circuit. FIG. 7 is an electrical wiring diagram of a binary-to-ternary conversion circuit in a second embodiment of the invention. 7...Inverter, 8...NOR gate, 9...---PMO8Tr, ICL...
・-NMO8Tr, 11-・-Op Amp, 12
...Transfer Gate, 13...
NAND gate, 14... Inverter, 15.
...Resistance, 16...Resistance, 17...
・NAND gate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
3M

Claims (1)

[Claims] A PMOS transistor whose source is connected to a power supply, a drain connected to the drain of the PMOS transistor,
An NM○S transistor whose source is grounded, an inverting input terminal, and an output terminal are connected to each other, an operational amplifier whose non-inverting input is an intermediate potential between the power supply and the ground, and the output of the operational amplifier is the input, and its output terminal is connected to the A transfer gate connected to the drains of the NMOS transistor and the PMO transistor, and a first state in which one of the PMO transistor and the NMOS transistor is conductive, as well as a non-conductive state and a second state in response to two binary data inputs. a first logic circuit that switches to a state of 2, and a second logic circuit that makes the transfer gate conductive when the PMO transistor 8) and the NMO transistor 8) are non-conductive according to the binary data input;
comprising a logic circuit, the PMOS transistor, NMO8
) A binary-to-ternary conversion circuit, characterized in that the binary data input is converted into a ternary data output by obtaining an output from the drain of a second-level transistor.