JPH0315854B2 - - Google Patents

Description

Detailed Description of the Invention The present invention relates to a P-channel type insulated gate field effect transistor (hereinafter referred to as P-MOS) and an N-channel type insulated gate field effect transistor (hereinafter referred to as N-MOS).
The present invention relates to a reference voltage generation circuit that uses complementary insulated gate field effect transistors (hereinafter referred to as C-MOS) and is driven with low power consumption.

FIG. 1 is a circuit diagram showing a conventional reference voltage generating circuit. In the figure, 1 is a first P _{-MOS whose source is grounded to V DD} and whose drain and gate are connected to the first node 2; 3 is a first P-MOS whose drain is connected to the first node 2;
A second N-MOS, 5, has one end connected to the _ground V DD and the other end connected to the second node 2, with its source connected to the negative power supply V _SS and its gate connected to the third node 4. a resistor 7 connected to the node 6, a third P-MOS whose source is connected to the second node 6, whose drain is connected to the third node 4, and whose gate is connected to the first node 2; 8 is a fourth N-MOS whose drain and gate are connected to the third node 4, and whose source is connected to the negative power supply V _SS .

Note that the first P-MOS 1 and the second N-MOS
- constitute a first series circuit from MOS 3, the resistor 5, third P-MOS 7 and fourth N-MOS;
8 constitutes a second series circuit, and the first series circuit and the second series circuit are connected in parallel. In addition, the first P-MOS1 and the third P-MOS
MOS7 has the same shape (length: L, width: W), but the absolute value of the threshold pressure value is the same as that of the first P-MOS.
1 is larger than the third P-MOS7. Also,
The second N-MOS 3 and the fourth N-MOS 8 have the same shape and the same threshold voltage value.

Next, the operation of the reference voltage generation circuit having the above configuration will be explained. First, since the second N-MOS 3 and the fourth N-MOS 8 constitute a current mirror circuit, the first P-MOS 1 and the third P-MOS
The current values flowing through MOS7 are equal. Furthermore, the first
Since the shapes of the P-MOS1 and the third P-MOS7 are the same and the gate is common, this current value I ₀ is the absolute value of each threshold voltage value of the first P-MOS1 and the third P-MOS7 | It is the value obtained by dividing the difference between V _THP1 | and |V _THP2 | by the resistance value R ₀ of resistor 5. That is, I ₀ =(|V _THP1 |−|V _THP2 |)/R ₀ (a) From equation (a), the current value I ₀ is constant regardless of the negative power supply voltage. Then, a reference voltage V ₆ is generated at the second node 6 that does not depend on the negative power supply voltage.

That is, V ₆ =-(|V _THP1 |-|V _THP2 |) (b) Voltage generated at node 2 and third node 4
FIG. 2 shows the relationship between V ₂ and V ₄ and the negative power supply voltage. The consumption current I _0LD flowing through this entire circuit is I _0LD =2I ₀ (c).

However, the conventional reference voltage generation circuit
As can be seen from equations (a) and (b), the only way to reduce power consumption without changing the reference voltage value is to increase the resistance value R ₀ of the resistor 5 in inverse proportion to it. Moreover, in the case of an LSI that requires low power consumption, the resistance value R ₀ of resistor 5 must be several MΩ or more, and it is not easy to realize such a large resistance on a chip due to pattern size constraints. There were flaws.

Therefore, an object of the present invention is to provide a reference voltage generation circuit that can reduce power consumption without increasing the resistance value of the resistor.

In order to achieve this purpose, this invention
a first transistor of a first conductivity type connected between a first potential and a first node; and a second transistor of a second conductivity type connected between a first node and a second potential. a resistor connected between the first potential and the second node; and a resistor connected between the second node and the third node, the gate of which is connected between the first potential and the second node; a first transistor connected to the gate of the first transistor and connected to either the first node or the third node, the absolute value of which has a threshold voltage smaller than the absolute value of the threshold voltage of the first transistor; a third transistor of conductivity type, connected between the third node and the second potential, the gate of which is connected to the gate of the second transistor, and the first node or the third node; a second series circuit comprising a fourth transistor of a second conductivity type connected to the other of the transistors; This device includes a connected fifth transistor, and will be described in detail below using examples.

FIG. 3 is a circuit diagram showing one embodiment of the reference voltage generating circuit according to the present invention. In the figure, 9 is a fifth N-MOS whose drain is connected to the second node 6, whose gate is connected to the third node 4, and whose source is connected to the negative power supply (V _SS ).

The threshold voltage value of this fifth N-MOS 9 is the same as that of the second N-MOS 3 and the fourth N-MOS 8, and the shape is the same as that of the second N-MOS 9.
With respect to the shapes of the third and fourth N-MOS 8, the length L is the same and the width W is N times larger.

Next, the operation of the reference voltage generation circuit having the above configuration will be explained. First, the second N-MOS3,
The width/length (W/L) of the shapes of the fourth N-MOS 8 and the fifth N-MOS 9 are W ₃ /L ₃ and W ₈ /
Assuming L ₈ , W ₉ /L ₉ , the ratio is W ₃ /L ₃ :W ₈ /
L ₈ :W ₉ /L ₉ =1:1:N. In addition, the second N-MOS3, the fourth N-MOS8, and the fifth N-MOS
Since the threshold voltage values of MOS9 are the same and the gate is common, if the currents flowing through each transistor are I ₃ , I ₈ , and I ₉ , then I ₃ :I ₈ :I ₉ =1:1:N
It is. First P-MOS1, third P-MOS7
Since the absolute value of the threshold voltage value and the resistance value R ₀ of the resistor 5 are the same as in Fig. 1, the current flowing through the resistor 5 I ₀
is also as described above. That is, I ₀ = (|V _THP1 | − | V _THP2 |)/R ₀ (a) Here, I ₀ = I ₈ + I ₉ (d), so considering the ratio of I ₈ and I ₉ , I ₃ , _I8 , and _I9 are respectively _I3 = _I8 = _I0 /(N+1) _I9 =N× _I0 /(N+1) (e). Therefore, the current consumption in the entire circuit I _NEW
I _NEW = I ₃ + I ₈ + I ₉ = I ₀ × (N+2)/(N+1) (f).

When compared with the current consumption I _OLD of the entire circuit shown in Figure 1, from equations (c) and (f), _{I NEW} is (N+
2)/2(N+1) times. For example, N=
In the case of 10, I _NEW will be reduced to 12/22≈0.55 times I _OLD . Further, the reference voltage generated from the second node 6 has the same value as in FIG. That is, V ₆ =−(|V _THP1 |−|V _THP2 |) (b).

Note that in this embodiment, the current flowing through the fifth N-MOS 9 flows through the second N-MOS 3 and the fourth N-MOS.
Although we changed the shape to increase the current flowing through MOS8 by N times, it is of course possible to achieve this by changing the threshold voltage value.

FIG. 4 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. In this case, the first potential is the ground V _SS and the second potential is the positive power supply V _DD ,
The first conductivity type transistor is N-MOS, and the second conductivity type transistor is P- _{MOS .}
Of course, it is possible to generate a reference voltage independent of

As described above in detail, according to the reference voltage generation circuit according to the present invention, current consumption can be reduced with a simple configuration. Further, in the case of the same current consumption as in the conventional example, the value of the resistance can be reduced, so the pattern size can be reduced, which is effective in terms of pattern size.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional reference voltage generation circuit, FIG. 2 is a diagram showing the negative power supply voltage-reference voltage characteristics of FIG. 1, and FIG. 3 is an embodiment of the reference voltage generation circuit according to the present invention. FIG. 4 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. 1...First P-MOS, 2...First node,
3...Second N-MOS, 4...Third node,
5...Resistor, 6...Second node, 7...Third P-MOS, 8...Fourth N-MOS, 9...Fifth
N-MOS, 10...6th N-MOS, 11...
...7th P-MOS, 12...8th N-MOS,
13... 9th P-MOS, 14... 10th P-
M.O.S.

Claims (1)

[Claims] 1. A first transistor of a first conductivity type connected between a first potential and a first node, and a first transistor connected between the first node and a second potential. a first series circuit comprising a second transistor of a second conductivity type; a resistor connected between the first potential and the second node; and a resistor connected between the second node and the third node. The absolute value of the threshold voltage is the threshold voltage of the first transistor, and the gate is connected to the gate of the first transistor, and the absolute value of the threshold voltage is the threshold voltage of the first transistor. A third transistor of a first conductivity type smaller than the absolute value of a second series circuit comprising a fourth transistor of a second conductivity type connected to the other of the node or the third node, connected between the second node and the second potential, the gate of which is A reference voltage generation circuit including a fifth transistor connected to a gate of the second transistor.