JPS59211329A - Reference voltage generating circuit - Google Patents

Reference voltage generating circuit

Info

Publication number
JPS59211329A
JPS59211329A JP58086855A JP8685583A JPS59211329A JP S59211329 A JPS59211329 A JP S59211329A JP 58086855 A JP58086855 A JP 58086855A JP 8685583 A JP8685583 A JP 8685583A JP S59211329 A JPS59211329 A JP S59211329A
Authority
JP
Japan
Prior art keywords
transistor
gate
node
drain
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58086855A
Other languages
Japanese (ja)
Other versions
JPH0315854B2 (en
Inventor
Hiroyuki Sugino
杉野　博之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58086855A priority Critical patent/JPS59211329A/en
Publication of JPS59211329A publication Critical patent/JPS59211329A/en
Publication of JPH0315854B2 publication Critical patent/JPH0315854B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

Abstract

PURPOSE:To decrease current consumption without increasing a resistance value of a resistor by providing the 5th MOSFET to a reference voltage generating circuit comprising two C-MOSFETs. CONSTITUTION:The source of a P-MOSFET1 is grounded and the drain and gate are connected to a node 2. The drain of an N-MOSFET3 is connected to the node 2, the source is connected to a negative power and the gate is connected to a node 4. The source of a P-MOSFET7 is connected to a node 6, the drain is connected to the node 4 and the gate is connected to the node 2. A resistor 5 is connected between ground and the node 6. The drain and gate of an N- MOSFET8 are connected to the node 4 and the source is connected to a negative power supply. The drain of an N-MOSFET9 is connected to the node 6, the gate is connected to the node 4 and the source is connected to the negative power supply.

Description

【発明の詳細な説明】 この発明はＰチャネル形絶縁ゲート電界効果トランジス
タ（以下Ｐ−ＭＯ８と言う）とＮチャネル形絶縁ゲート
電界効果トランジスタ（以下Ｎ−ＭＯ８と言う）とから
なる相補形絶縁ゲート電界効果トランジスタ（以下Ｃ−
ＭＯ８と言う）を用いた低消費電力で駆動する基準電圧
発生回路に関するものである。Detailed Description of the Invention The present invention provides a complementary insulated gate field effect transistor consisting of a P-channel type insulated gate field effect transistor (hereinafter referred to as P-MO8) and an N-channel type insulated gate field effect transistor (hereinafter referred to as N-MO8). Field effect transistor (hereinafter referred to as C-
The present invention relates to a reference voltage generation circuit that uses a low power consumption drive circuit (referred to as MO8).

第１図は従来の基準電圧発生回路を示す回路図である。FIG. 1 is a circuit diagram showing a conventional reference voltage generating circuit.

同図において、（１ンはソースが接地（ＶＤｎ　）され
、ドレインおよびゲートがノード（乃に接続された第１
のＰ−ＭＯＳ、（３）はドレインが／　−）”（２）に
接続され、ソースが負電源（Ｖｇｓ　）に接続され、ゲ
ートがノード（４）に接続された第２のＮ−ＭＯＳ、（
５）は一端が接地（ＶＤＤ　）され、他端はノード（６
）に接続された抵抗、（７）ｉ−１，ソースがノード（
６）に接続され、ドレインがノード（４）に接続され、
ゲートがノード（２）に接続された第３のＰ−ＭＯ８，
（８）はドレインおよびゲートがノード（４）に接続さ
れ、ソースが負電源（Ｖｓｓ　）に接続された第４のＮ
−ＭＯ８である。In the same figure, (1) is connected to the first node whose source is grounded (VDn) and whose drain and gate are connected to a node.
P-MOS, (3) is a second N-MOS whose drain is connected to /-)'' (2), source is connected to the negative power supply (Vgs), and gate is connected to node (4), (
5) has one end grounded (VDD) and the other end connected to the node (6
), (7)i-1, source connected to node (
6), the drain is connected to node (4),
a third P-MO8, whose gate is connected to node (2);
(8) is the fourth N whose drain and gate are connected to node (4) and whose source is connected to the negative power supply (Vss).
-MO8.

なお、前記第１のＰ−ＭＯ８（１）および第２のＮ−Ｍ
ＯＳ　（３）から第１の直列回路を構成し、前記抵抗（
５）。Note that the first P-MO8(1) and the second N-M
A first series circuit is constructed from OS (3), and the resistor (
5).

第３のｐ　−ｈｑｏ　ｓ　（７）および第４ＯＮ−ＭＯ
８（８）から第２の直列回路を構成し、そして、この第
１の直列回路と第２の直列回路とは並列に接続される。3rd p-hqos (7) and 4th ON-MO
8 (8) constitutes a second series circuit, and the first series circuit and the second series circuit are connected in parallel.

また、第１のＰ−ＭＯ８（１）と第３のＰ−ＭＯ８（７
）は形状（長さ：Ｌ１幅：Ｗ）が同じであるが、しきい
電圧値の絶対値は第１のＰ−ＭＯ８（１）のほうが第３
０Ｐ−ＭＯ８（７）よシ太きい。また、第２のＮ−ＭＯ
８（３）と第４のＮ−ＭＯ８（８）は形状もしきい電圧
値も共に同じである。In addition, the first P-MO8 (1) and the third P-MO8 (7
) have the same shape (length: L1 width: W), but the absolute value of the threshold voltage value is higher for the first P-MO8 (1) than for the third P-MO8 (1).
0P-MO8 (7) It's thick. Also, the second N-MO
8 (3) and the fourth N-MO 8 (8) have the same shape and threshold voltage value.

次に、上記構成による基準電圧発生回路の動作について
説明する。まず、第２のＮ−ＭＯ８（３）と第４ＯＮ−
ＭＯ８（８）がカレントミラー回路を構成しているので
、第１０Ｐ−ＭＯ８（１）と第３０Ｐ−ＭＯ８（７）を
流れる電流値は等しい。さらに、第１のＰ−ＭＯＳ　（
１）と第３のＰ−ＭＯ８（７）の形状が等しく、ゲート
が共通なので、この電流値ＩＯは第１のＰ　−ＭＯ８（
１）と第３のＰ−ＭＯ３（７）の各しきい電圧値の絶対
値１■丁ＨＰＩ　ｌ　＋　ｌ　ＶＴＨＰ２１の差を抵抗
（５）の抵抗値ＲＯで割った値になる。すなわち、 Ｉｏ＝（ＩＶｔｎｐＨ１ＶＴＨＰ２１）／ＲＯ（ａ）（
、）式から、電流値ＩＯは負電源電圧に依存せず一定で
ある。そして、ノード（６）には負電源電圧に依存しな
い基準電圧■６が発生する。Next, the operation of the reference voltage generation circuit having the above configuration will be explained. First, the second N-MO8 (3) and the fourth ON-
Since the MO8(8) constitutes a current mirror circuit, the current values flowing through the 10th P-MO8(1) and the 30th P-MO8(7) are equal. Furthermore, the first P-MOS (
1) and the third P-MO8 (7) have the same shape and have a common gate, this current value IO is equal to that of the first P-MO8 (7).
1) and the absolute value of each threshold voltage value of the third P-MO3 (7) 1 d HPI l + l VTHP21 divided by the resistance value RO of the resistor (5). That is, Io=(IVtnpH1VTHP21)/RO(a)(
, ), the current value IO is constant regardless of the negative power supply voltage. Then, a reference voltage (6) independent of the negative power supply voltage is generated at the node (6).

すなわち、 Ｖａ＝　　（１ＶＴｕｐ１１　１ＶＴ１１Ｐ２１　）　
　　　　（ｂ）メート（２）およびメート（４）に発生
する電圧■２およびｖ４と負電源電圧との関係を含めて
、第２図に示す。そして、この回路全体を流れる消費電
流ｌ０ＬＤはｌ０ＬＤ　＝　２　Ｉｏ　　　　　　　　
　　　　　（ｃ）である。That is, Va= (1VTup11 1VT11P21)
(b) FIG. 2 shows the relationship between the voltages 2 and v4 generated in mate (2) and mate (4) and the negative power supply voltage. The current consumption l0LD flowing through this entire circuit is l0LD = 2 Io
(c).

しかしながら、従来の基準電圧発生回路は前記（、）式
および（ｂ）式かられかるように、基準電圧値を変えず
に、消費電流を下げるにはそれ（反比例して、抵抗（５
）の抵抗値Ｒｏを大きくする以外に方法がない。しかも
、低消費電力を要求される工、ＳＩの場合、抵抗（５）
の抵抗値ＲＯは数ＭΩ以上必要であり、このような大き
な抵抗をチップ上で実現する際にはパターンサイズ上の
制約から容易でない欠点があった。However, as can be seen from equations (,) and (b) above, in the conventional reference voltage generation circuit, in order to reduce the current consumption without changing the reference voltage value, it is necessary to
) There is no other way than to increase the resistance value Ro. Moreover, in the case of engineering and SI that require low power consumption, the resistor (5)
The resistance value RO is required to be several MΩ or more, and it is difficult to realize such a large resistance on a chip due to pattern size constraints.

したがって、この発明の目的は抵抗の抵抗値を大きくせ
ずに、しかも消費電流を低減することができる基準電圧
発生回路を提供するものである。Therefore, an object of the present invention is to provide a reference voltage generation circuit that can reduce current consumption without increasing the resistance value of the resistor.

このような目的を達成するため、この発明は第１導電形
の第１のトランジスタと第２導電形の第２のトランジス
タとが直列に接続されたのち、第１の電位と第２の電位
との間に接続された第１の直列回路と、抵抗体、第１導
電形の第３のトランジスタおよび第２導電形の第４のト
ランジスタとが直列に接続されたのち、第１の電位と第
２の電位との間に接続された第２の直列回路と、ドレイ
ンが前記抵抗体と第３のトランジスタのソースとの接続
点に接続され、ゲートが第３のトランジスタのドレイン
と第４のトランジスタのドレインとの接続点に接続され
、ソースが第２の電位に接続された第５のトランジスタ
とを備え、前記第１のトランジスタのゲートが第３のト
ランシスタノケートに接続されると共に第１のトランジ
スタ（もしくは第３のトランジスタ）のドレインに接続
され、前記第２のトランジスタのゲートが第４のトラン
ジスタのゲートに接続されると共に第４のトランジスタ
（もしくは第２のトランジスタ）のドレインに接続され
、第１のトランジスタのしきい電圧値の絶対値を第３の
トランジスタのしきい電圧値よシ太きくしたものであシ
、以下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention connects a first transistor of a first conductivity type and a second transistor of a second conductivity type in series, and then connects the first potential to the second potential. After the resistor, the third transistor of the first conductivity type, and the fourth transistor of the second conductivity type are connected in series, the first series circuit is connected between the first potential and the fourth transistor of the second conductivity type. a second series circuit whose drain is connected to the connection point between the resistor and the source of the third transistor, and whose gate is connected between the drain of the third transistor and the fourth transistor; a fifth transistor connected to a connection point with the drain of the first transistor and having a source connected to a second potential, a gate of the first transistor being connected to a third transistor node and a fifth transistor having a source connected to a second potential; connected to the drain of the transistor (or the third transistor), the gate of the second transistor is connected to the gate of the fourth transistor, and the drain of the fourth transistor (or the second transistor); The absolute value of the threshold voltage value of the first transistor is made larger than the threshold voltage value of the third transistor, and will be explained in detail below using an example.

第３図はこの発明に係る基準電圧発生回路の一実施例を
示す回路図である。同図において、（９）はドレインが
ノード（６）に接続され、ゲートがノード（４）に接続
され、ソースが負電源（ＶＳＳ）に接続された第５ＯＮ
−ＭＯ８である。FIG. 3 is a circuit diagram showing one embodiment of the reference voltage generating circuit according to the present invention. In the same figure, (9) is the fifth ON whose drain is connected to the node (6), whose gate is connected to the node (4), and whose source is connected to the negative power supply (VSS).
-MO8.

なお、この第５ＯＮ−ＭＯ８（９）のしきい電圧値は第
２のＮ−ＭＯ８（３）および第４のＮ−ＭＯ８（８）の
しきい電圧値と同じで、形状は第２のＮ−ＭＯＳ（３）
および第４のＮ−ＭＯＳ（８）の形状に対して、長さく
Ｌ）が同じで、幅（Ｗ）がＮ倍である。The threshold voltage value of this fifth ON-MO8 (9) is the same as that of the second N-MO8 (3) and the fourth N-MO8 (8), and the shape is similar to that of the second N-MO8 (8). -MOS(3)
The length L) is the same as that of the fourth N-MOS (8), and the width (W) is N times larger.

次に、上記構成による基準電圧発生回路の動作について
説明する。まず、第２のＮ−ＭＯＳ（３）、第４のＮ−
ＭＯＳ（８）、第５のＮ−ＭＯＳ（９）の形状の幅／長
す（ＶＬ　）　ｆ　’Ｃレソレ”／Ｌ３１ｗ８／Ｌｓ　
、　ｗ９／Ｌ９とすると、その比はＷ３／Ｉ、３：Ｗ８
／Ｌ８：Ｗ９／Ｌ９−１＝にＮである。また、第２のＮ
−ＭＯＳ（３）、第４のＮ−ＭＯＳ（８）、第５のＮ−
ＭＯＳ（９）のしきい電圧値が等しく、ゲートが共通で
あるから、それぞれのトランジスタを流れる電流をＩ３
＋Ｉ８＋Ｉｇとすると、Ｉ３：　Ｉｓ：　ｌ９＝１　：
　１　：　Ｎである。第１のＰ−ＭＯＳ（１）、第３０
Ｐ−ＭＯＳ（７）のしきい電圧値の絶対値や抵抗（５）
の抵抗値ＲＯは第１図と同じであるから、抵抗（５）を
流れる電流１．も前述したようになる。すなわち、 ｌ０＝（ＩＶＴＨＰＩＩ　　ＩＶＴＨＰ２１）／ＲＯ（
ａ）ここで Ｉｏ＝　Ｉｓ　＋　ＩＯ（ｄ） であるから、Ｉｓと工９の比を考えると、Ｉ３＋　Ｉｓ
　＋Ｎａはそれぞれ、 Ｉ３．＝　Ｉｓ　＝　Ｉｏ／（Ｎ＋１）ＩＱ　＝　Ｎ　
Ｘ　ＩＯ／（Ｎ＋１）　　　　　　　（ｅ）である。し
たがって、回路全体での消費′電流ＩＮｍは　　　ＩＮ
ＥＷ＝　Ｉ３＋　Ｉｓ　＋　ＩＱ＝　ＩＯＸ　（Ｎ＋２
）／（Ｎ＋１）　　　（ｆ）となる。Next, the operation of the reference voltage generation circuit having the above configuration will be explained. First, the second N-MOS (3), the fourth N-MOS
Width/length (VL) of shape of MOS (8), fifth N-MOS (9) f'Cresole''/L31w8/Ls
, w9/L9, the ratio is W3/I, 3:W8
/L8:W9/L9-1=N. Also, the second N
-MOS (3), 4th N-MOS (8), 5th N-
Since the threshold voltage values of MOS (9) are the same and the gate is common, the current flowing through each transistor is I3.
+I8+Ig, I3: Is: l9=1:
1: N. 1st P-MOS (1), 30th
Absolute value of threshold voltage value and resistance (5) of P-MOS (7)
Since the resistance value RO is the same as in FIG. 1, the current 1. flowing through the resistor (5) is 1. is also as described above. That is, l0=(IVTHPII IVTHP21)/RO(
a) Here, Io = Is + IO(d), so considering the ratio of Is and 9, I3 + Is
+Na are respectively I3. = Is = Io/(N+1)IQ = N
X IO/(N+1) (e). Therefore, the current consumption INm in the entire circuit is IN
EW= I3+ Is + IQ= IOX (N+2
)/(N+1) (f).

第１図に示す回路全体の消費電流ｌ０ＬＤと比較すると
、（Ｃ）式および（ｆ）式から、ＩＮ謀はＩｏｔ、ｎの
（Ｎ＋２）／２（Ｎ＋１）倍になっている。例えばＮ−
１０の場合、ＩＮｇｗはｌ０ＬＤの１２７２２舞０．５
５倍に低減されることになる。また、ノード（６）から
発生される基準電圧は第１図と同じ値になる。すなわち
、Ｖ６＝　　（ＩＶＴＨＰＩＩ　　ＩＶＴｉｐｚｌ）　
　　　　（ｂ）である。When compared with the current consumption l0LD of the entire circuit shown in FIG. 1, from equations (C) and (f), the IN ratio is (N+2)/2(N+1) times Iot,n. For example, N-
In the case of 10, INgw is 12722 times 0.5 of l0LD.
It will be reduced by 5 times. Further, the reference voltage generated from node (6) has the same value as in FIG. That is, V6= (IVTHPII IVTipzl)
(b).

なお、この実施例では第５のＮ−ＭＯＳ（９）を流れる
電流が第２ＯＮ−１１ｉｉＯ８（３）および第４のＮ−
ＭＯＳ（８）　を流れる電流のＮ倍にさせるために形状
を変えたが、しきい電圧値を変えても実現できることは
もちろんである。Note that in this embodiment, the current flowing through the fifth N-MOS (9) flows through the second ON-11iiO8 (3) and the fourth N-MOS (3).
The shape was changed to increase the current flowing through the MOS (8) by N times, but this can of course be achieved by changing the threshold voltage value.

第４図はこの発明に係る基準電圧発生回路の他の実施例
を示す回路図である。この場合、第１の電位を接地（Ｖ
ｓｓ　）とし、第２の電位を正電源（ＶＤＤ）！第１導
電形のトランジスタをＮ−ＭＯＳ、第２導電形のトラン
ジスタをＰ−ＭＯＳとして構成したものであシ、接地（
Ｖｓｓ）を基準として、正電源（ＶＤＤ　）によらない
基準電圧を発生することができることはもちろんである
。FIG. 4 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. In this case, the first potential is grounded (V
ss ), and the second potential is the positive power supply (VDD)! The first conductivity type transistor is an N-MOS, and the second conductivity type transistor is a P-MOS.
Of course, it is possible to generate a reference voltage independent of the positive power supply (VDD) using Vss as a reference.

以上詳細に説明したように、この発明に係る基準電圧発
生回路によれば簡単な構成によシ、消費電流を低減する
ことができる。また、従来例と同じ消費電流の場合には
抵抗の値を小さくすることができるので、パターンサイ
ズを小さくでき、パターンサイズ上有効になるなどの効
果がある。As described above in detail, according to the reference voltage generation circuit according to the present invention, current consumption can be reduced with a simple configuration. Further, in the case of the same current consumption as the conventional example, the value of the resistance can be reduced, so the pattern size can be reduced, which is effective in terms of pattern size.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の基準電圧発生回路を示す回路図、第２図
は第１図の負電源電圧−基準電圧特性を示す図、第３図
はこの発明に係る基準電圧発生回路の一実施例を示す回
路図、第４図はこの発明に係る基準電圧発生回路の他の
実施例を示す回路図である０ （１）・・・・第１のＰ−ＭＯＳ、（２）・・・・ノー
ド、（３）・・・・第２ＯＮ−ＭＯＳ１（４）・・・・
ノート°、（５）・・・・抵抗、（６）・・・・ノー！
’、（７）・・・・第３のＰ−ＭＯＳ、（８）・・・・
第４のＮ−ＭＯＳ　、　（９）　’φ・・・第５のＮ−
ＭＯＳ０ なお、図中、同一符号は同一または相当部分を示す。 代理人　　大岩増雄 第１図 ｖ弱 第２図 第３図 第４図 手続補正前（自発） １、事件の表示　　　特願昭５８−０８６８５５号２、
発明の名称　　　基準電圧発生回路：３．補正をする者 事件との関係　特許出願人 住　所　　　　　東京都千代田区丸の内二丁目２番３乞
−名　称　　（６０１，）三菱電機株式会社代表者片由
仁八部 ４代理人 住　所　　　　東京都千代１］１区九の内二ｊ′目２番
３号（１）明細書の特許請求の範囲の− （２）明細書の発明の詳細な説明の欄 （３）明細書の図面の簡単な説明の欄 （４）図　面 ６、補正の内容 （１）　　８Ａ細書の特許請求の範囲を別紙の通り補正
する。 （２）同書第５頁第２０行〜第６頁第１行の「第３のト
ランジスタのドレイン」を［第２のトランジスタのゲー
ト」と補正する。 （３）同書第６頁第１行の［第４のトランジスタのドレ
イン」を「第４のトランジスタのゲート」と補正する。 （４）　　同書第１０頁第７行の［第５のＮ−ＭＯ８Ｊ
の後に［、ａａ−−−−第６　）Ｎ−ＭＯ３Ｘ（１１）
　−−−・第７のＰ−ＭＯＳ、住４・・・・第８のＮ　
−ＭＯＳ。 ａ３−−−−第９＋７）Ｐ−ＭＯ８ＸＱ４１−−−−第
１００Ｐ１００Ｐ−を加入する。 （５）第４図を別紙未配の通９補正する。 以上 別　　　　　　　　　　紙 ［第１導電形の第１のトランジスタと第２導電形の第２
のトランジスタとが直列に接続されたのち、第１の電位
と第２の電位との間に接続された第１の直列回路と、抵
抗体、第１導電形の第３のトランジスタおよび第２導電
形の第４のトランジスタとが直列に接続されたのち、第
１の電位と第２の電位との間に接続された第２の直列回
路と、ドレインが前記抵抗体と第３のトランジスタのソ
ースとの接続点に接続され、ゲートが第主のトランジス
タのゲートと第４のトランジスタのゲートとの接続点に
接続され、ソースが第２の電位に接続された第５のトラ
ンジスタとを備え、前記第１のトランジスタのゲートが
第３のトランジスタのゲートに接続されると共に第１の
トランジスタ（もしくは第３のトランジスタ）のドレイ
ンに接続され、前記第２のトランジスタのゲートが第４
のトランジスタのゲートに接続されると共に第４のトラ
：ジス：）（もしくは第２のトランジスタ）のドレイン
に接続され、第１のトランジスタのしきい電圧値の絶対
値を第３のトランジスタのしきい電圧値より大きくした
ことを％徴とする基準電圧発生回路。」 以上FIG. 1 is a circuit diagram showing a conventional reference voltage generation circuit, FIG. 2 is a diagram showing the negative power supply voltage-reference voltage characteristics of FIG. 1, and FIG. 3 is an embodiment of the reference voltage generation circuit according to the present invention. FIG. 4 is a circuit diagram showing another embodiment of the reference voltage generation circuit according to the present invention. (1)...First P-MOS, (2)... Node, (3)...Second ON-MOS1 (4)...
Note °, (5)...Resistance, (6)...No!
', (7)...Third P-MOS, (8)...
4th N-MOS, (9) 'φ...5th N-
MOS0 Note that in the drawings, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 v-low Figure 2 Figure 3 Figure 4 Before procedural amendment (voluntary) 1. Indication of the case Patent Application No. 1986-086855 2.
Title of the invention Reference voltage generation circuit: 3. Relationship with the case of the person making the amendment Patent applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo - Name (601,) Mitsubishi Electric Co., Ltd. Representative Katayuni Yabu 4 Agent Address Chiyo 1, Tokyo ] Section 1, Section 9, Item 2j', No. 2, No. 3 (1) Scope of claims in the specification - (2) Column for detailed explanation of the invention in the specification (3) Brief description of drawings in the specification Column (4) Drawing 6, Contents of amendment (1) The claims in the 8A specification are amended as shown in the attached sheet. (2) "Drain of the third transistor" in page 5, line 20 to page 6, line 1 of the same book is corrected to "gate of the second transistor". (3) "Drain of the fourth transistor" in the first line of page 6 of the same book is corrected to "gate of the fourth transistor." (4) [5th N-MO8J] on page 10, line 7 of the same book
After [,aa---6th)N-MO3X(11)
---・7th P-MOS, 4th...8th N
-MOS. a3---9th+7)P-MO8XQ41---100P100P- is added. (5) 9 corrections have been made to Figure 4 for which the attached sheet has not yet been distributed. Attachment above [First transistor of first conductivity type and second transistor of second conductivity type]
a first series circuit connected between the first potential and the second potential, a resistor, a third transistor of the first conductivity type, and a second conductivity type transistor; a second series circuit connected between the first potential and the second potential; and a drain connected to the resistor and the source of the third transistor. a fifth transistor whose gate is connected to a connection point between the gate of the first main transistor and the gate of the fourth transistor, and whose source is connected to the second potential; The gate of the first transistor is connected to the gate of the third transistor and the drain of the first transistor (or the third transistor), and the gate of the second transistor is connected to the gate of the fourth transistor.
is connected to the gate of the transistor and also connected to the drain of the fourth transistor (or the second transistor), and the absolute value of the threshold voltage value of the first transistor is set to the threshold voltage of the third transistor A reference voltage generation circuit that takes the percentage value as a percentage when it is greater than the voltage value. "that's all

Claims (1)

【特許請求の範囲】[Claims] 第１導電形の第１のトランジスタと第２導電形の第２の
トランジスタとが直列に接続されたのち、第１の電位と
第２の電位との間に接続された第１の直列回路と、抵抗
体、第１導電形の第３のトランジスタおよび第２導電形
の第４のトランジスタとが直列に接続されたのち、第１
の電位と第２の電位との間に接続された第２の直列回路
と、ドレインが前記抵抗体と第３のトランジスタのソー
スとの接続点に接続され、ゲートが第３のトランジスタ
のドレインと第４のトランジスタのドレインとの接続点
に接続され、ソースが第２の電位に接続された第５のト
ランジスタとを備え、前記第１のトランジスタのゲート
が第３のトランジスタのゲートに接続されると共に第１
のトランジスタ（もしくは第３のトランジスタ）のドレ
インに接続・　され、前記第２のトランジスタのゲート
が第４のトランジスタのゲートに接続されると共に第４
の）−ｊｙレジスタもしくは第２のトランジスタ）のド
レインに接続され、第１のトランジスタのシキい電圧値
の絶対値を第３のトランジスタのしきい電圧値よシ大き
くしたことを特徴とする基準電圧発生回路。After the first transistor of the first conductivity type and the second transistor of the second conductivity type are connected in series, a first series circuit is connected between the first potential and the second potential. , the resistor, the third transistor of the first conductivity type, and the fourth transistor of the second conductivity type are connected in series;
and a second series circuit, the drain of which is connected to the connection point between the resistor and the source of the third transistor, and the gate of which is connected to the drain of the third transistor. a fifth transistor connected to a connection point with the drain of the fourth transistor and having a source connected to the second potential, the gate of the first transistor being connected to the gate of the third transistor. with the first
(or a third transistor), the gate of the second transistor is connected to the gate of the fourth transistor, and the fourth
-jy register or the drain of the second transistor), the reference voltage is characterized in that the absolute value of the threshold voltage value of the first transistor is larger than the threshold voltage value of the third transistor. generation circuit.
JP58086855A 1983-05-16 1983-05-16 Reference voltage generating circuit Granted JPS59211329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58086855A JPS59211329A (en) 1983-05-16 1983-05-16 Reference voltage generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58086855A JPS59211329A (en) 1983-05-16 1983-05-16 Reference voltage generating circuit

Publications (2)

Publication Number Publication Date
JPS59211329A true JPS59211329A (en) 1984-11-30
JPH0315854B2 JPH0315854B2 (en) 1991-03-04

Family

ID=13898425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58086855A Granted JPS59211329A (en) 1983-05-16 1983-05-16 Reference voltage generating circuit

Country Status (1)

Country Link
JP (1) JPS59211329A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0497405A (en) * 1990-08-16 1992-03-30 Nec Ic Microcomput Syst Ltd Constant current circuit
JPH04170609A (en) * 1990-11-05 1992-06-18 Nec Ic Microcomput Syst Ltd Constant current circuit
JP2012070224A (en) * 2010-09-24 2012-04-05 Renesas Electronics Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0497405A (en) * 1990-08-16 1992-03-30 Nec Ic Microcomput Syst Ltd Constant current circuit
JPH04170609A (en) * 1990-11-05 1992-06-18 Nec Ic Microcomput Syst Ltd Constant current circuit
JP2012070224A (en) * 2010-09-24 2012-04-05 Renesas Electronics Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0315854B2 (en) 1991-03-04

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