JPH02123645U - - Google Patents

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Publication number
JPH02123645U
JPH02123645U JP3358889U JP3358889U JPH02123645U JP H02123645 U JPH02123645 U JP H02123645U JP 3358889 U JP3358889 U JP 3358889U JP 3358889 U JP3358889 U JP 3358889U JP H02123645 U JPH02123645 U JP H02123645U
Authority
JP
Japan
Prior art keywords
microcomputer
port
input
mode
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3358889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3358889U priority Critical patent/JPH02123645U/ja
Publication of JPH02123645U publication Critical patent/JPH02123645U/ja
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す図、第２図は
その具体回路を示す図、第３図は従来例を示す図
である。 １……第１のマイクロコンピユータ、１ａ……
ポート、２……チユーナ、３……第１キー入力部
、６……第２のマイクロコンピユータ、６ａ……
ポート、９……テープレコーダ、１０……第２キ
ー入力部、１１……設定回路、１２……ＮＡＮＤ
ゲート、１３……ＮＯＲゲート、１５，１６……
ＦＥＴ、１８……判定回路、２２……基準電圧発
生部、２３……第１比較器、２４……第２比較器
。 FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing its specific circuit, and FIG. 3 is a diagram showing a conventional example. 1...first microcomputer, 1a...
port, 2... tuner, 3... first key input section, 6... second microcomputer, 6a...
Port, 9...Tape recorder, 10...Second key input section, 11...Setting circuit, 12...NAND
Gate, 13...NOR gate, 15, 16...
FET, 18 ... Judgment circuit, 22... Reference voltage generation section, 23... First comparator, 24... Second comparator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力モード時にハイインピーダンスとなる入出
力兼用のポートを有する第１のマイクロコンピユ
ータと、この第１のマイクロコンピユータのポー
トが出力モードに設定されたとき、前記第１のマ
イクロコンピユータのポートからのデータを受け
る入力ポートを有する第２のマイクロコンピユー
タと、前記第１のマイクロコンピユータが入力モ
ードにあるとき、前記第２のマイクロコンピユー
タのポートを中間レベルに設定する設定手段を設
けたことを特徴とするマイクロコンピユータの接
続装置。 A first microcomputer has an input/output port that becomes high impedance in input mode, and when the port of this first microcomputer is set to output mode, data from the port of the first microcomputer is a second microcomputer having an input port for receiving input; and a setting means for setting the port of the second microcomputer to an intermediate level when the first microcomputer is in an input mode. Computer connection device.
JP3358889U 1989-03-24 1989-03-24 Pending JPH02123645U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3358889U JPH02123645U (en) 1989-03-24 1989-03-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3358889U JPH02123645U (en) 1989-03-24 1989-03-24

Publications (1)

Publication Number Publication Date
JPH02123645U true JPH02123645U (en) 1990-10-11

Family

ID=31260278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3358889U Pending JPH02123645U (en) 1989-03-24 1989-03-24

Country Status (1)

Country Link
JP (1) JPH02123645U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108430A (en) * 1982-12-13 1984-06-22 Matsushita Electric Ind Co Ltd Binary-ternary value converting circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108430A (en) * 1982-12-13 1984-06-22 Matsushita Electric Ind Co Ltd Binary-ternary value converting circuit

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