JPH01169823U - - Google Patents
Info
- Publication number
- JPH01169823U JPH01169823U JP6617488U JP6617488U JPH01169823U JP H01169823 U JPH01169823 U JP H01169823U JP 6617488 U JP6617488 U JP 6617488U JP 6617488 U JP6617488 U JP 6617488U JP H01169823 U JPH01169823 U JP H01169823U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- circuit
- mos transistor
- gate
- inverting amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims 4
- 239000003990 capacitor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図に示されたバイアス回路の他の実施例を
示す回路図、第３図は従来例を示す回路図である
。
９，１３……ＮＡＮＤ回路、１０……高抵抗、
１１……バイアス回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the bias circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional example. 9, 13...NAND circuit, 10...High resistance,
11...Bias circuit.
Claims (1)
加され、第１の制御信号で動作を行う反転増幅回
路と、前記第１の制御信号と検出動作を行う時に
出力される第２の制御信号で動作を開始し、前記
反転増幅回路に高抵抗を介してバイアス電圧を供
給するバイアス回路とを備えたゼロクロス検出回
路に於いて、前記バイアス回路は、バイアス電圧
の出力がゲートに印加されたＭＯＳトランジスタ
と、前記第１の制御信号がゲートに印加されたＭ
ＯＳトランジスタと、前記第２の制御信号に基い
て発生する信号がゲートに印加されたＭＯＳトラ
ンジスタとの直列回路を含むＮＡＮＤ回路である
ことを特徴とするゼロクロス検出回路。 (2) 外部からコンデンサを介して交流信号が印
加され、第１の制御信号で動作を行う反転増幅回
路と、前記第１の制御信号と検出動作を行う時に
出力される第２の制御信号で動作を開始し、前記
反転増幅回路に高抵抗を介してバイアス電圧を供
給するバイアス回路とを備えたゼロクロス検出回
路に於いて、前記バイアス回路は、バイアス電圧
の出力がゲートに印加されたＭＯＳトランジスタ
と、前記第１の制御信号及び第２の制御信号が共
に出力された状態に基いて発生する信号がゲート
に印加されたＭＯＳトランジスタとの直列回路を
含むＮＡＮＤ回路であることを特徴とするゼロク
ロス検出回路。[Claims for Utility Model Registration] (1) An inverting amplifier circuit to which an AC signal is applied from the outside via a capacitor and operates in response to a first control signal, and an output when performing a detection operation in conjunction with the first control signal. and a bias circuit that starts operation in response to a second control signal supplied to the inverting amplifier circuit and supplies a bias voltage to the inverting amplifier circuit through a high resistance, the bias circuit is configured to is applied to the gate of the MOS transistor, and the first control signal is applied to the gate of the MOS transistor.
A zero-cross detection circuit characterized in that it is a NAND circuit including a series circuit of an OS transistor and a MOS transistor whose gate is applied with a signal generated based on the second control signal. (2) An inverting amplifier circuit to which an AC signal is applied from the outside via a capacitor and operates based on the first control signal, and a second control signal output when performing a detection operation in conjunction with the first control signal. and a bias circuit that starts operation and supplies a bias voltage to the inverting amplifier circuit through a high resistance, wherein the bias circuit includes a MOS transistor to which a bias voltage output is applied to the gate. and a signal generated based on the state in which both the first control signal and the second control signal are output is a NAND circuit including a series circuit with a MOS transistor applied to the gate. detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988066174U JPH0727697Y2 (en) | 1988-05-19 | 1988-05-19 | Zero cross detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988066174U JPH0727697Y2 (en) | 1988-05-19 | 1988-05-19 | Zero cross detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01169823U true JPH01169823U (en) | 1989-11-30 |
| JPH0727697Y2 JPH0727697Y2 (en) | 1995-06-21 |
Family
ID=31291586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988066174U Expired - Lifetime JPH0727697Y2 (en) | 1988-05-19 | 1988-05-19 | Zero cross detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727697Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109991535A (en) * | 2019-04-19 | 2019-07-09 | 青岛亿联客信息技术有限公司 | A kind of flash on-off control system and its input flash detection circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5426650A (en) * | 1977-07-30 | 1979-02-28 | Toshiba Corp | Schmitt trigger circuit |
| JPS57147328A (en) * | 1981-03-05 | 1982-09-11 | Nec Corp | Input circuit |
-
1988
- 1988-05-19 JP JP1988066174U patent/JPH0727697Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5426650A (en) * | 1977-07-30 | 1979-02-28 | Toshiba Corp | Schmitt trigger circuit |
| JPS57147328A (en) * | 1981-03-05 | 1982-09-11 | Nec Corp | Input circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109991535A (en) * | 2019-04-19 | 2019-07-09 | 青岛亿联客信息技术有限公司 | A kind of flash on-off control system and its input flash detection circuit |
| CN109991535B (en) * | 2019-04-19 | 2024-04-30 | 青岛亿联客信息技术有限公司 | Flash switch control system and input flash detection circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0727697Y2 (en) | 1995-06-21 |
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