JPS5980763U - window comparator - Google Patents
window comparatorInfo
- Publication number
- JPS5980763U JPS5980763U JP17733382U JP17733382U JPS5980763U JP S5980763 U JPS5980763 U JP S5980763U JP 17733382 U JP17733382 U JP 17733382U JP 17733382 U JP17733382 U JP 17733382U JP S5980763 U JPS5980763 U JP S5980763U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- window comparator
- input signal
- setting
- voltage range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のウィンドコンパレータ、第２図は本考案
の一実施例を示す回路図である。
１．２・・・・・・コンパレータ、Ｒ，、Ｒ２，Ｒ３，
Ｒ１・・・・・・分圧用抵抗、Ｅｘ＝ＯＲ・・・・・・
排他的論理和ゲート。
補正 昭５８． ２．２５
図面の簡単な説明を次のように補正する。
明細書第６頁第１４行目「である。」に続いて次の説明
を加入する。
［第３図は本考案の他の実施例を示す回路図である。」FIG. 1 is a circuit diagram showing a conventional window comparator, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1.2...Comparator, R,, R2, R3,
R1...Resistance for voltage division, Ex=OR...
Exclusive OR gate. Revised 1984. 2.25 The brief description of the drawings is amended as follows. The following explanation is added following "is" on page 6, line 14 of the specification. [FIG. 3 is a circuit diagram showing another embodiment of the present invention. ”
Claims (1)
るウィンドコンパレータにおいて、入力信号電圧ＷＩＮ
と電圧範囲設定用基準電圧Ｖ、、、 Ｖ。 との間に夫々電圧範囲設定用分圧抵抗の直列回路を設け
、上記電圧Ｖ、、と電圧■８及び電圧ＶＬの夫々の分圧
電圧Ｖ）（ｌ、 Ｖｕを所定のスレッショールド電圧Ｖ
、８を持つゲート入力とするゲート回路を設け、上記ゲ
ート回路のオン−・オフ出力から検出出力を得ることを
特徴とするウィンドコンパレータ。[Claims for Utility Model Registration] In a window comparator that detects whether an input signal voltage is within a predetermined voltage range, the input signal voltage WIN
and the reference voltage for setting the voltage range, V. A series circuit of voltage dividing resistors for voltage range setting is provided between the voltage ranges V, , , and the voltages 8 and VL.
, 8 as a gate input, and a detection output is obtained from the on-off output of the gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17733382U JPS5980763U (en) | 1982-11-24 | 1982-11-24 | window comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17733382U JPS5980763U (en) | 1982-11-24 | 1982-11-24 | window comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5980763U true JPS5980763U (en) | 1984-05-31 |
Family
ID=30385288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17733382U Pending JPS5980763U (en) | 1982-11-24 | 1982-11-24 | window comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5980763U (en) |
-
1982
- 1982-11-24 JP JP17733382U patent/JPS5980763U/en active Pending
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