JPS6055115U - AGC circuit - Google Patents

AGC circuit

Info

Publication number
JPS6055115U
JPS6055115U JP14505083U JP14505083U JPS6055115U JP S6055115 U JPS6055115 U JP S6055115U JP 14505083 U JP14505083 U JP 14505083U JP 14505083 U JP14505083 U JP 14505083U JP S6055115 U JPS6055115 U JP S6055115U
Authority
JP
Japan
Prior art keywords
agc circuit
gate
input
signal
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14505083U
Other languages
Japanese (ja)
Inventor
二ノ瀬　修司
Original Assignee
クラリオン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クラリオン株式会社 filed Critical クラリオン株式会社
Priority to JP14505083U priority Critical patent/JPS6055115U/en
Publication of JPS6055115U publication Critical patent/JPS6055115U/en
Pending legal-status Critical Current

Links

Landscapes

  • Circuits Of Receivers In General (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図はこの考案の一実施例を示す回路図である。 １：アンテナ、２ニスイツチング回路、３：ＤＣＣバフ
フッ路、４：フロントエンドＩＣ，５：利得制御用ＦＥ
Ｔ、６：ピンダイオード、７：トランジスタ。The figure is a circuit diagram showing an embodiment of this invention. 1: Antenna, 2 Niswitching circuit, 3: DCC buffing circuit, 4: Front end IC, 5: Gain control FE
T, 6: Pin diode, 7: Transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アンテナ出力を利得制御用ＦＥＴの第１ゲートに入力し
て信号を得る一方、この信号に応じた制御信号を前記Ｆ
ＥＴの第２ゲートに入力するＡＧＣ回路において、アン
テナと前記第１ゲートとの間にビンタイオードを設け、
このピンダイオードを前記制御信号で制御するようにし
たことを特徴とするＡＧＣ回路。The antenna output is input to the first gate of the gain control FET to obtain a signal, while a control signal corresponding to this signal is input to the FET.
In the AGC circuit input to the second gate of the ET, a bin diode is provided between the antenna and the first gate,
An AGC circuit characterized in that the pin diode is controlled by the control signal.
JP14505083U 1983-09-21 1983-09-21 AGC circuit Pending JPS6055115U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14505083U JPS6055115U (en) 1983-09-21 1983-09-21 AGC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14505083U JPS6055115U (en) 1983-09-21 1983-09-21 AGC circuit

Publications (1)

Publication Number Publication Date
JPS6055115U true JPS6055115U (en) 1985-04-18

Family

ID=30323296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14505083U Pending JPS6055115U (en) 1983-09-21 1983-09-21 AGC circuit

Country Status (1)

Country Link
JP (1) JPS6055115U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS562416U (en) * 1979-06-20 1981-01-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS562416U (en) * 1979-06-20 1981-01-10

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