JP2734551B2 - Power supply voltage conversion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply voltage conversion circuit for converting a voltage supplied from an external power supply to obtain a predetermined voltage.

[Conventional technology]

As a power supply voltage conversion circuit using a conventionally known differential amplifier, there is a circuit shown in FIG. This power supply voltage conversion circuit is described in the magazine "IEEE, Journal of Solid State Circuits", published in October 1986, 21st edition.
Vol. 5, page 608. This circuit starts with FET
A desired reference voltage V _REF is generated by a reference voltage generation circuit 1 including Q _{11 to} Q ₁₅ . The voltage V _REF generated by the reference voltage generating circuit 1 is applied to a differential amplifier 2 composed of FETs Q ₂ , Q ₃ , Q _{6 to} Q _9.
, And the differential amplifier 2 amplifies the difference voltage between the output voltage V _OUT of the power supply voltage conversion circuit and the voltage V _REF . The output of the differential amplifier 2 is input to the load drive circuit 3. In the load driving circuit 3, the source is the power supply voltage V _CC
A P-channel MISFET having a drain connected to the output V _OUT and a gate connected to the output from the differential amplifier 2
) Q ₂₀ has been used as PMISFET.

The operation of the power supply voltage conversion circuit is performed as follows.
When the output voltage V _OUT is lower than the voltage value V _REF , the differential amplifier 2
Becomes low level, and the load driving circuit 3 PMIS
FETQ ₂₀ conducts and supplies current, increasing the voltage level of output voltage V _OUT . Conversely, when the level of the output voltage V _OUT is higher than the desired level, the output of the differential amplifier 2 goes high, the load drive circuit 3 becomes non-conductive, and the supply of current to the output voltage V _OUT stops. In this way, the output voltage is maintained at the level of the reference voltage _VREF .

Power supply voltage converting circuit of FIG. 10 converts the power supply voltage V _CC given from the outside making the output voltage V _OUT, is to supply the level of the output voltage V _OUT to any circuit.

The reference voltage generating circuit 1 of the power supply voltage converting circuit, the circuit and constituted by FETs Q ₁₁ to Q ₁₅ as Figure 10,
As shown in FIG. 11, there is a circuit for obtaining a reference voltage by dividing the resistances of R ₁ and R ₂ , and both circuits have a steady current path.

[Problems to be solved by the invention]

Thus, when trying to drive a load having a large capacity with the conventional power supply voltage conversion circuit, the load driving circuit 3 needs to have a large driving capability. As a result, the differential amplifier 2 also needs to have a driving capability in accordance with the load driving circuit 3, which causes an increase in power consumption. This means that the period during which the drive of the large load capacitance is required is one period of the entire operation of the memory, and the other period is, for example, when the power supply voltage conversion circuit is applied to the memory and used for driving the bit line. When applied to a case where only a relatively small capacitance needs to be kept at a constant voltage, power consumption is wasted.

Further, since the reference voltage generation circuit 1 used in the power supply voltage conversion circuit has a steady current path, if a large number of reference voltage generation circuits are used simultaneously according to the number of unit power supply voltage conversion circuits in the power supply voltage conversion circuit. Again, this leads to waste of current consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply voltage conversion circuit which solves such a problem and reduces power consumption when driving of a large load capacity is not required, and also reduces current consumption of a reference voltage generation circuit. It is in.

[Means for solving the problem]

The configuration of the power supply voltage conversion circuit according to the present invention includes a reference voltage generation circuit, a differential amplifier having an output of the reference voltage generation circuit connected to one of input terminals, and a load driven by inputting an output of the differential amplifier. And a plurality of unit power supply voltage conversion circuits connected in a feedback manner to the output voltage of the load drive circuit at the other input terminal of the differential amplifier. The output terminals of these unit power supply voltage conversion circuits A power supply voltage conversion circuit for selecting and outputting a required number of the plurality of unit power supply voltage conversion circuits according to the magnitude of a load capacitance to be driven, wherein the reference voltage generation circuit Describes that a switch circuit is provided in a constant current path formed in the reference voltage generation circuit, and a control signal is applied to the switch circuit to control activation / inactivation of the reference voltage generation circuit. And butterflies.

[Action]

According to the power supply voltage conversion circuit of the present invention, when a large load capacity drive is required, a desired output voltage is obtained by a unit power supply voltage conversion circuit having a load drive circuit having a large drive capacity, and the other relatively small load capacity is driven. To do this, switch the switch provided in the differential amplifier of the power supply voltage conversion circuit or in both the differential amplifier and the load drive circuit.
Since a desired output voltage is obtained by a unit power supply voltage conversion circuit having a load driving circuit having a small driving ability, a desired constant voltage can be output with power consumption when driving a large load capacity is not performed.

Also, when the unit power supply voltage conversion circuit is deactivated by a switch provided in the differential amplifier or in both the differential amplifier and the load drive circuit, the reference voltage generation circuit is simultaneously placed in the switch circuit provided therein. Inactivated by the control signal, the power consumption can be reduced.

〔Example〕

Next, embodiments of the power supply voltage conversion circuit and the reference voltage generation circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which reference voltage generating circuits 11 and 12, differential amplifiers 21 and 22, and PMISFETs Q ₃₁ and Q
₃₂ load driving circuits. Differential amplifier
The output signal V _REF from the reference voltage generation circuits 11 and 12 is input to one of the input terminals 21 and 22, the feedback signal of the output voltage V _OUT of the power supply voltage conversion circuit is input to the other input terminal. the output of 21 and 22 are inputted to the gate of the PMISFETQ _31, Q ₃₂ is a load driving circuit and constitute a unit power supply voltage conversion circuit. Two unit power supply voltage conversion circuits are connected in parallel at an output terminal 10 and output a voltage _VOUT . Note that the reference voltage generation circuits 11 and 12 may be any type of circuit as long as the circuit supplies a required reference voltage.

The differential amplifiers 21 and 22 used in this embodiment include, for example, a circuit shown in FIG. This circuit is a differential amplifier of a type generally called a current mirror type. Further, although a PMISFET is used as the load driving circuit 3, the present invention is not limited to this PMISFET, and may be an N-channel type MISFET.
FET (hereinafter referred to as NMISFET), bipolar transistor,
Alternatively, a circuit including a plurality of elements is used.

The description of the reference voltage generating circuit, the differential amplifier, and the load driving circuit applies to all of the following embodiments.

In the embodiment shown in FIG. 1, a load driving circuit having a large load driving capability, in other words, a PMISFETQ _{31 having} a large conductance is used.
And a second circuit having a PMISFETQ ₃₂ having a small conductance, that is, a first circuit having a small driving capability, that is, a second circuit having a PMISFETQ ₃₂ having a small conductance. Are _supplied with signals φ _A1 and φ _A2 for controlling the activation / deactivation of each circuit.

The method of using the circuit of FIG. 1 will be described with reference to an application to a memory. When it is necessary to drive a large load such as when charging a bit line, the signal φ _A1 is set to an appropriate level to set the reference voltage generation circuit 11 and the differential amplifier 21 of the first circuit.
And supply a constant voltage. This first circuit is effective for driving a large load because it has a load driving circuit having a large capacity. Next, when a large load drive is not required, as in the case of memory standby, the first circuit is deactivated by the signal φ _A1 and conversely, the second circuit is activated by the signal φ _A2 to maintain the constant voltage. Supply. The second circuit has a load driving circuit with a small capacity, so that the current consumption of the differential amplifier 22 for driving the load driving circuit can be reduced, which is effective in reducing power consumption.

An example of a method for introducing the control signal phi _A to the differential amplifier, illustrated by Figure 2. In the figure, the source is grounded, has a NMISFETQ ₁ with a drain connected to the source of the differential input section transistors Q _2, Q ₃ of the source-coupled, put a control signal phi _A to the gate of the NMISFETQ _1, circuit activation to conduct NMISFETQ ₁ by the phi _a high level at the time of, at the time of deactivation to nonconductive NMISFETQ ₁ by the phi _a low level. Although the activation / inactivation of the circuit can be controlled in this way, if the type of the differential amplifier changes, the control method using signals also changes.

As described above, since the power supply voltage conversion circuit of the present embodiment outputs the constant voltage _VOUT using the appropriate load drive circuit corresponding to the size of the load to be driven, the power supply voltage conversion circuit is controlled by one power supply voltage conversion circuit. The operation can be performed with lower power consumption than in the case of outputting a voltage.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.
Eliminating the signal phi _A2 for controlling the differential amplifier 22 towards circuit, but to be always activates the second circuit. In this case, since the load that must be driven during standby or the like is small, the load driving capability of the second circuit 2 can be small. As a result, when the current consumption is small, there is an advantage that the control signal is reduced. .

FIG. 4 is a circuit diagram of a third embodiment of the present invention.
This is an example in which unit power supply voltage conversion circuits of ≧ 2) are connected in parallel. Each reference voltage generation circuit 11-1n, differential amplifier 21
22n and PMISFETQ ₃₁ Q _3n , and when the load capacitance value to be driven is divided into several stages, etc., the unit power supply voltage conversion having a load drive circuit corresponding to each load capacitance value The circuit is switched and used.

FIG. 5 is a circuit diagram of a fourth embodiment of the present invention, in which a circuit for surely shutting off the load driving circuit 3 when inactive is provided. Specifically, the source was connected to the external power supply V _CC , and the drain was connected to the gates of the PMISFETs Q ₃₁ and Q ₃₂ as load drive circuits, and the control signal φ _Si (i: a positive integer) was input to the gate.
The PMISFETQ _41, Q ₄₂ are provided. This PMISFETQ _41, when the unit power supply voltage converting circuit including a Q ₄₂ is selected, the Q _41, Q ₄₂ and the control signal phi _Si to a high level keep the non-conductive.
Conversely, if the unit power supply voltage conversion circuit is not selected,
The signal φ _{Si is set} to low level to turn on the PMISFETs Q ₄₁ and Q ₄₂ , the gates of the PMISFETs Q ₃₁ and Q ₃₂ of the load drive circuit are set to high level, and the unit power supply voltage conversion circuit is completely deactivated. The signal φ _Si may be the same as the signal φ _Ai or another signal.

Figure 6 is a 5 in the circuit diagram of an embodiment of a bipolar transistor without a load driving circuit 3 is PMISFETQ _31, Q ₃₂ of the present invention
This is an example in which Q ₂₁ and Q ₂₂ are set.

FIG. 7 is a circuit diagram of a sixth embodiment of the present invention.
Applied to the reference voltage generation circuit by resistance division of R ₁ , R ₂ , PM circuit which is a switch circuit in the steady current path of the reference voltage generation circuit
The ISFETQ ₁₈ provided in the circuit by the control signal phi _R activity /
Inactivity can be controlled.

When using the power supply voltage conversion circuit of the present embodiment, for example, the first
The case where the reference voltage generation circuit of this embodiment is used for the reference voltage generation circuit shown in FIG. In FIG. 1, when the first circuit is deactivated by the signal φ _A1 , the signal φ _{R is set} to the high level to deactivate the reference voltage generation circuit, and the current is prevented from flowing by cutting off the steady current path. To When this first circuit is activated to activate the reference voltage generating circuit and a signal phi _R to the low level, to operate the power supply voltage conversion circuit. Thus, when the unit power supply voltage conversion circuit is not used, the reference voltage generation circuit is also inactivated, and the current consumption can be reduced. This is, for example, the fourth
This is particularly effective when a large number of unit power supply voltage conversion circuits are used simultaneously as shown in the figure. The switch circuit for controlling the activation / inactivation of the reference voltage generation circuit is not limited to the type shown in FIG.

In the circuit diagram of a seventh embodiment of FIG. 8 is the present invention, an example in which the switch circuit Q ₁₈ of Figure 7 to NMISFETQ _19. In this configuration change the manner of control, and the low level of phi _R is when the reference voltage generation circuit deactivated, may be a phi _R to the high level when activated.

Figure 9 is a circuit diagram of a reference voltage generating circuit of the eighth embodiment of the present invention, instead of the FETs Q _11, Q ₁₂ of FIG. 10, FETs Q _11, Q ₁₂ connected to the gate control signal phi _R is used It was done.
As can be seen by comparing FIGS. 9 and 10, the control signal φ is already applied to the gate of the transistor in the reference voltage generating circuit without adding a transistor as a switch circuit.
_The present invention can also be realized by inserting _R.

〔The invention's effect〕

As described above, by using the power supply voltage conversion circuit of the present invention, current consumption of the power supply voltage conversion circuit when a large load capacitance is not driven, such as during standby, can be significantly reduced.

According to a simulation result in which the power supply voltage conversion circuit of the present invention was applied to a memory, the current consumption of the differential amplifier portion was such that the source in the amplifier was grounded, and the drain was connected to the source of the source-coupled differential input transistor. MI
Since it is almost proportional to the gate width W of the SFET (Q ₁ ), the current consumption is reduced by the ratio that the size of the differential amplifier of the power supply voltage conversion circuit becomes smaller during standby compared to the conventional power supply voltage conversion circuit. The effect is obtained. Also, by using a reference voltage generation circuit switched by a switch circuit, even when a large number of reference voltage generation circuits need to be used, the steady current of the unused reference voltage generation circuits is eliminated to reduce power consumption. It has the effect of being able to peel off.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a differential amplifier used in FIG. 1, and FIGS. 3 to 6 are second to fifth embodiments of the present invention. Circuit block diagram of the embodiment,
7 to 9 are circuit diagrams showing three examples of the reference voltage generating circuit of FIG. 1, FIG. 10 is a circuit diagram of a conventional power supply voltage conversion circuit, and FIG. 11 is a conventional reference voltage by resistance division. It is a figure of a generation circuit. 1,11,12--1n ... Reference voltage generation circuit, 2,21,22-
2n ...... differential amplifier, 3 ...... load driving circuit, 10 ...... output _{terminal, Q 2, Q 4, Q} 5, Q 11 ~Q 18, Q 20, Q 31, Q 32 --- Q 3n, Q ₄₁ , Q ₄₂
…… PMISFET, Q ₁ , Q ₃ , Q ₁₉ … NMISFET, Q ₂₁ , Q ₂₂ … Bipolar transistor, R ₁ , R ₂ … Resistance.

Claims (1)

(57) [Claims] 1. A reference voltage generating circuit, a differential amplifier having an output of the reference voltage generating circuit connected to one of input terminals, and a load driving circuit for inputting an output of the differential amplifier and driving a load. The other input terminal of the differential amplifier is provided with a plurality of unit power supply voltage conversion circuits in which the output voltage of the load drive circuit is connected in a feedback manner, and the output terminals of the unit power supply voltage conversion circuits are connected in common and output. A power supply voltage conversion circuit for selecting and outputting a required number of the plurality of unit power supply voltage conversion circuits in accordance with the magnitude of the load capacitance to be driven. A power supply voltage converter, wherein a switch circuit is provided in a constant current path formed in the circuit, and a control signal is applied to the switch circuit to control activation / inactivation of the reference voltage generation circuit. Road.