JPH0612631B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a multi-bit output semiconductor memory.

[Conventional technology]

Conventionally, in this type of semiconductor memory, when a pulse having a short width is applied to an address terminal, an internal circuit operates in response to the pulse. On the other hand, when the read data output to the output terminal changes from the H level to the L level, the discharge current that discharges the charge accumulated in the output load capacitance, the bonding wire, and the inductance component of the lead frame cause the ground of the memory chip to be discharged. Although the potential of the pad fluctuates greatly, and thus the address signal applied to the address terminal does not change, the address signal appears to have changed when viewed from the chip. As a result, there is a problem that the internal circuit operates and the read data once output is erased. Hereinafter, description will be given with reference to the drawings.

FIG. 6 shows a metal oxide semiconductor transistor (hereinafter referred to as MOS
FIG. 8 is a circuit diagram of a conventional semiconductor memory using an abbreviated FET. In FIG. 6, A0, Ai, Ai + 1, A
j is an address terminal, DOUT is an output terminal, 601 to 60
4 is an address buffer and address transition detection circuit, 60
5 to 608 are NAND decoders, 609 to 612 are decoder buffers, 613 to 616 are digit line and data bus line equipotential signal generation circuits, and 617 to 618.
Is a sense amplifier circuit, 619 to 620 are inverters for driving output MOSFETs, Q1, Q2, Q4 and Q5 are digit line load MOSFETs, Q3 and Q6 are digit line equipotential MOSFETs, and Q7 to Q10 are digit line selections. Transfer gate, Q11 and Q12 are data bus line load MOSFETs, Q13 is a data bus line equipotential MOSFET, and Q14 and Q15 are output MOSFs.
ET, C ₀₀ , CK ₀ , C0 ₁ , and Ck ₁ are memory cells,
D ₀ , ▲ ▼, D ₁ , ▲ ▼ are digit lines, D
B, ▲ ▼ are data bus lines, X0, Xk are word lines,
Y0 and Y1 are Y address lines, EQ is an equipotential signal, A
0, ▲ ▼, Ai, ▲ ▼, Ai + 1, , Aj, ▲ are address buffer output lines, OS, OS
i, OSi + 1, and OSj are address transition detection signal lines.

Next, the operation of the circuit shown in FIG. 6 will be described with reference to FIG.
FIG. 7 is a waveform diagram showing operation waveforms of main nodes when the address input signal changes from L level to H level in the circuit of FIG. 6 and read data changes from H level to L level in response to this. Is. When the address input is at the L level, X0 is selected for the word line and Y0 is selected for the Y address line, and the data in the memory cell C00 is read. When the address input is at the H level, the word line is Xk and the Y address. The line is Y
It is assumed that 1 is selected and the data in the memory cell Ck1 is read. In FIG. 7, 701 is an address signal waveform, 7
Reference numeral 02 is an address transition detection signal waveform, 703 is a word line signal waveform, 704 is an equipotential signal waveform, 705 is a digit line signal waveform, 706 is a data bus line signal waveform, 707.
Is a gate signal waveform of the output MOSFET Q15, 708 is a signal waveform of the output terminal DOUT, and 709 is an output MOSFET.
Discharge current waveform flowing into the ground through TQ15, 7
Reference numeral 10 is a ground pad voltage waveform of the memory chip.

First, when the address signal changes from the L level to the H level at time t0, the address transition detection signal changes from the L level to the H level at time t1, and the equipotentialization signal EQ generated from this signal changes. At time t2, the L level changes to the H level. The address transition detection signal is time t
From time 1, the time Δt, which is determined by the delay time of the delay circuit in the address transition detection circuit, elapses, and at time t3, the signal changes from H level to L level again.
It returns to the level, and following this, the equipotentialization signal EQ also returns from the H level to the L level at time t4. Separately from this, the word line and the Y address line also move in response to the address change, and the word line X0 and the Y address line Y0 selected when the address is at the L level change from the H level to the L level at about time t3. On the other hand, the word line Xk and the Y address line Y1 which are selected when the address is at the H level are almost at time t.
At 4, it starts to rise from L level to H level. Now, when the equipotentialization signal EQ becomes H level, the equipotentialization MOSFET Q connected to the digit line and the data bus line is connected.
3, Q8 and Q13 are turned on to reduce the potential difference between the digit line and the data bus line. When the potential difference between the data bus lines disappears, the sense amplifier output signal becomes uncertain, and therefore the gate potentials of the output MOSFETs Q14 and Q15,
Also, the level of the output terminal DOUT becomes uncertain. Here, the output level being uncertain means that the output terminal voltage is at the H level or the L level, or at the H level and the L level.
You don't know if you're at an intermediate level, in other words, it could be any of these. At the time t4, the equipotentialization signal EQ becomes L level, and at the same time, the word line Xk and the Y address line Y1 become H level.
At the level, the data of the memory cell Ck1 appears on the data bus line DB, ▲ ▼ from the digit line through the transfer gates Q9, Q10. After this data is amplified by the sense amplifier, the gate terminal of the output MOSFET Q15 is set to the H level and the output terminal is set to the L level. Normally, the wiring capacity or the input capacity of the logic gate is used as a load at the output terminal. About several + PF to 100 PF are connected, and when the output changes from the H level to the L level, a discharge current for discharging the electric charge accumulated in this capacitance flows. The semiconductor memory is usually housed in a ceramic or plastic package, and a bonding wire and a lead frame are present between the ground pad of the chip and the system ground. Since each of these has a self-inductance component, the ground potential of the chip fluctuates greatly when the current flowing into the ground changes abruptly. If the ground current is i, the time is t, and the variation of the ground potential of the chip is ΔV, then ΔV
Is given by the following equation (1).

ΔV = −L x di / dt (1) Here, the rise time of the discharge current waveform is the output MOSF.
Since it is equal to the rise time of the gate signal of the ETQ15, the width W of the ground pad potential waveform of the chip caused by the change of the discharge current and the inductance of the bonding wire and the lead frame is smaller than the rise time of the gate signal of the output MOSFET Q15. When the ground potential of the chip fluctuates in this way, even if the address signal does not change, it appears to the memory circuit in the chip as if a narrow pulse signal was applied to the address terminal.

[Problems to be solved by the invention]

In the conventional semiconductor memory, the circuit moves in response to such a narrow pulse signal. Therefore, when the output changes from the H level to the L level, the address transition detection signal is output again.
In response to this, the equipotential signal is also generated again, and the potential difference between the digit line and the data bus line is reduced, so that the output level becomes temporarily uncertain. That is, since the address signal externally applied to the semiconductor memory has changed only once, the data read in response to this change is held until the next externally applied address signal changes. Although it has to be kept, the L-level data once output is temporarily erased, which causes a problem that the system using the memory malfunctions.

[Content of originality of prior art of invention]

In contrast to the conventional semiconductor memory described above, the present invention provides a pulse only when the pulse width of the address signal applied to the address input terminal is sufficiently longer than the rising and falling times of the gate signal of the output MOSFET in the output buffer circuit. Is provided with a pulse width discriminating circuit, and a gate circuit is provided between the output of the sense amplifier and the input of the output buffer circuit. The gate circuit is controlled by the output of the pulse width discriminating circuit and the address applied to the address input terminal. It has the ingenious content that the gate circuit is opened to carry the sense amplifier output to the output buffer input only when the pulse width of the signal is wide enough.

[Means for solving problems]

A semiconductor memory according to the present invention includes at least one address input terminal, at least one data output terminal, a memory cell array, a sense amplifier for amplifying read data, and a data output terminal that receives the output of the sense amplifier and reads the data output terminal. An output buffer circuit for outputting data, wherein the pulse width of the address signal applied to the address input terminal is determined from the rise and fall times of the gate signal of the output MOSFET in the output buffer circuit. A pulse width discriminating circuit that generates a pulse only when it is sufficiently long is provided, and a gate circuit is provided between the sense amplifier output and the output buffer circuit input, and the gate circuit is controlled by the output of the pulse width discriminating circuit. , The pulse width of the address signal applied to the address input terminal is sufficient It said gate circuit only when There are characterized in that to tell the output buffer input a sense amplifier output open.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory according to the first embodiment of the present invention. The biggest difference between the circuit of FIG. 1 and the circuit of FIG. 6 shown in the conventional example is that a transfer gate is provided between the sense amplifier and the output buffer circuit, and this is controlled by the output signal of the pulse width valve circuit. Especially. That is, in FIG. 1, the output of the sense amplifier 119 and the output MOS
N-channel MOSFET, Q14 and P-channel MOSF are provided between the FET drive inverters 121, 123.
A pulse width discrimination circuit 117 is provided which is provided with a transfer gate in which ET and Q15 are connected in parallel, and which receives the one-shot signal OS generated from the address transition detection signal as an input.
The problem of the conventional semiconductor memory is solved by being configured to be controlled by the output signal GP.

The operation of the circuit of FIG. 1 will be described below with reference to FIG.

FIG. 2 shows the circuit of FIG. 1, where the address input signal changes from the L level to the H level and the read data changes from the H level to the L level in response to this, as in the case of the conventional example. 5 is a waveform chart showing operation waveforms of main nodes of FIG. When the address input is L level, the word line is X0
However, when Y0 is selected as the Y address line and the data in the memory cell C00 is read out, and when the address input is at the H level, Xk is selected as the word line and Y1 is selected as the Y address line and the data in the memory cell Ck1 is selected. It is supposed to be read. Second
In the figure, 201 is an address signal waveform, 202 is an address transition detection signal waveform, 203 is a word line signal waveform, 20
4 is an equipotential signal waveform, 205 is a digit line signal waveform, 206 is a data bus line signal waveform, and 207 is an output MO.
The gate signal waveform of the SFET Q15, 208 is the waveform of the output signal GP of the pulse width discrimination circuit, and 209 is the output terminal DOU.
A signal waveform of T, 210 is a discharge current waveform flowing into the ground through the output MOSFET Q15, and 211 is a ground voltage waveform of the memory chip.

First, when the address signal changes from the L level to the H level at time t0, the address transition detection signal changes from the L level to the H level at time t1, and the equipotentialization signal EQ generated from this signal changes. At time t2, the L level changes to the H level, and at the time t5, the pulse width discrimination signal GP changes from the L level to the H level. The address transition detection signal returns from the H level to the L level again at the time t3 when the time Δt determined by the delay time of the delay circuit in the address transition detection circuit has elapsed from the time t1, and the equipotential signal EQ also follows the time. At t4, the H level is returned to the L level. Separately from this, the word line and the Y address line also move in response to the address change, and the word line X0 and the Y address line Y0 selected when the address is at the L level change from the H level to the L level at about time t3. On the other hand, the word line Xk and the Y address line Y1 selected when the address is at H level are
At about time t4, the L level starts to rise to the H level.
Now, when the equipotentialization signal EQ becomes H level, the equipotentialization MO connected to the digit line and the data bus line is set.
The SFETs Q3, Q6 and Q13 are turned on to reduce the potential difference between the digit line and the data bus line. When the potential difference between the data bus lines disappears, the sensor amplifier output signal becomes uncertain, and therefore the gate potentials of the output MOSFETs Q14 and Q15 and the level of the output terminal DOUT also become uncertain. When the equipotentialization signal Q becomes L level at the same time as the word line Xk and the Y address line Y1 become H level at the time t4, the data of the memory cell C _k1 is transferred from the digit line through the transfer gates Q9 and Q10. Appears on the bus line DB, DB. After this data is amplified by the sense amplifier, the gate terminal of the output MOSFET Q15 is set to H level and the output terminal is set to L level. After the read data is output, the pulse width discrimination signal GP becomes t
At 6, the H level is changed to the L level, and the transfer gates Q14 and Q15 are turned off. Output data is H
When the level changes from the L level to the L level, the potential of the chip ground pad fluctuates in the same manner as in the conventional example due to the discharge current that discharges the output load capacitance, so that the address transition detection signal and the equipotential signal EQ are also generated. , The output signal of the sense amplifier becomes indeterminate. However, the pulse width discrimination signal GP does not respond to such a narrow pulse, and when the sense amplifier output signal becomes uncertain, the transfer gate Q1
Since 4 and Q15 are in the off state, the problem that the data once output disappears unlike the conventional example does not occur. It should be noted that the inverter 12 shown in FIG.
The reason for attaching 2 is to prevent the inputs of the inverters 121 and 123 from floating after the transfer gate is turned off.

Next, the pulse width discrimination circuit will be described with a specific example.

FIG. 3 shows an embodiment of the pulse width discrimination circuit. Here, a circuit in the case where the input signal is a downward pulse will be described in accordance with the embodiment shown in FIG. In FIG. 3, 31 is an input terminal, 32 is a delay circuit, 33 is an output node of the delay circuit, 34 is a NOR logic gate, and 39 is an output terminal.

Next, the operation of the circuit shown in FIG. 3 will be described with reference to FIG.

FIG. 4 is a diagram showing the operation waveforms of the nodes of the circuit of FIG. 3, and 41 to 43 represent the waveforms of the nodes 31, 33 and 35, respectively. Further, in FIG. 4, the solid line shows the operation waveform when the pulse width of the input signal is wide, and the broken line shows the operation waveform when the pulse width is narrow.

In FIG. 4, when the input signal changes from the H level to the L level at the time t0, in response to this, after the delay time D, the time t
At 1, the node 33 changes from H level to L level. Then, both inputs of the NOR logic gate 34 become L level, so that the output node 35 changes from L level to H level at time t2. Next, at time t3, the input signal changes from L level to H level.
When the level becomes high, the output node 35 changes from the H level to the L level at time t4. When an input signal having a pulse width of Wi is applied to this circuit, the pulse width Wo of the output signal is Wo =
It is represented by Wi-D. Therefore, the input signal pulse Wi
However, when it becomes equal to the value of D, Wo becomes 0, and when it becomes narrower than the value of D, the output does not move. In other words, this circuit is a pulse width discrimination circuit in which the output does not respond even when a pulse having a width narrower than a certain width is input.

As already described in the description of the conventional example, in the fluctuation of the ground pad potential of the chip which occurs when the output level of the semiconductor memory changes from the H level to the L level, the fluctuation width W
Is smaller than the rise time tr of the gate signal of the output MOSFET, the value of D in the above pulse width discrimination circuit is set so as to satisfy D> tr, and the output signal of this pulse width discrimination circuit is set. By controlling the transfer gate provided between the sense amplifier and the output buffer circuit, it is possible to solve the problem that the once output data is temporarily lost as in the conventional case.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 5 shows that after the first embodiment controls the transfer gate provided between the sense amplifier and the output buffer circuit by the output signal of the pulse width discrimination circuit,
The difference is that the inverter at the next stage of the sense amplifier 519 is controlled by the output signal of the pulse width discrimination circuit.

When the address applied from the outside changes, the address transition detection circuit, the address buffer, the decoder, the word line, and the Y address line move as in the first embodiment, and the data of the newly selected memory cell is transferred to the sense amplifier. 519
It is amplified by and is added to the gates of Q15 and Q16. In accordance with this, the output of the pulse width discrimination circuit 517 becomes H level, Q14 and Q17 are turned on, the inverter consisting of Q15 and Q16 operates, and the data is amplified to the input of the inverters 520 and 522 which drive the output MOSFET. Tell, output M
The OSFET Q19 is turned on and read data is output to the output terminal. After the read data is output, the pulse width discrimination circuit 5
Since the output of 17 becomes L level, Q14 and Q17 are turned off, so that the inverter composed of Q15 and Q16 does not work. Even if the ground pad potential of the chip fluctuates when the output level changes from the H level to the L level, the output of the pulse width discrimination circuit 517 remains at the L level as in the first embodiment. Q17 remains off, and even if the output of the sense amplifier 519 becomes uncertain, the inputs of the inverters 520 and 522 that drive the output MOSFETs do not move and hold correct data. Therefore, the problem that the data once output is temporarily lost does not occur unlike the conventional case.

〔The invention's effect〕

As described above, the present invention generates a pulse only when the pulse width of the address signal applied to the address input terminal is sufficiently longer than the rising and falling times of the gate signal of the output MOSFET in the output buffer circuit. A pulse width discrimination circuit is provided, and a gate circuit is provided between the output of the sense amplifier and the input of the output buffer circuit. The gate circuit is controlled by the output of the pulse width discrimination circuit, and the pulse of the address signal applied to the address input terminal. The gate circuit opens only when the width is wide enough to transfer the sense amplifier output to the output buffer input, so that when the read data output to the output terminal changes from H level to L level, the output load capacitance Discharge current that discharges the charge accumulated in the wire, bonding wire, inductor of lead frame The potential of the ground pad of the memory chip fluctuates significantly depending on the component, and the address signal applied to the address terminal does not change for this reason. There is an effect that it is possible to provide a stable semiconductor memory in which the problem that read data once output disappears due to the operation of the internal circuit can be provided.

In recent years, semiconductor memories have become faster and faster, and at the same time, the number of products having a large number of input / output terminals is increasing. System malfunctions due to fluctuations in the ground potential of the chip when the read data changes are extremely high. It has become a serious problem, and the meaning of the present invention is very great.

In the above description, the semiconductor memory using the MOSFET has been described, but it goes without saying that the present invention is not limited to this and can be applied to a semiconductor memory using a bipolar transistor or a compound semiconductor transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory according to the first embodiment of the present invention. In FIG. 1, A0, Ai, Ai + 1, Aj are address terminals, DOUT is an output terminal, 101-104 are address buffers and address transition detection circuits, 105-1.
Reference numeral 08 is a NAND decoder, 109 to 112 are decoder buffers, 113 to 116 are digit line and data bus line equipotential signal generation circuits, 117 is a pulse width discrimination circuit, 118 to 119 are sense amplifier circuits, and 120 and 122 are inverters. , 121 and 123 are inverters for driving output MOSFETs, Q1, Q2, Q3, Q4 and Q5 are digit line load MOSFETs, Q3 and Q6 are digit line equalizing MOSFETs, and Q7 to Q10 are transfer lines for selecting digit lines. Gate MOSFE
T, Q11, Q12 are data bus load MOSFET, Q1
3 is a data bus line equipotential MOSFET, Q14, Q1
5 is a transfer gate MOSFET, Q16, Q1
7 is an output MOSFET, C00, Ck0, C01, Ck
1 is a memory cell, D0, ▲ ▼, D1, ▲ ▼ are digit lines, DB, ▲ ▼ are data bus lines, and X0, X
k is a word line, Y0 and Y1 are Y address lines, EQ is an equipotential signal, A0, ▲ ▼, Ai, ▲ ▼, Ai +
1, , Aj, ▲ ▼ are address buffer output lines, OS, O
Si, OSi + 1, and OSj are address transition detection signal lines. FIG. 2 is a waveform diagram showing operation waveforms of main nodes in FIG. In FIG. 2, 201 is an address signal waveform, 202
Is an address transition detection signal waveform, 203 is a word line signal waveform, 204 is an equipotential signal waveform, 205 is a digit line signal waveform, 206 is a data bus line signal waveform, 207 is a gate signal waveform of the output MOSFET Q15, and 208 is a pulse width. Waveform of the output signal GP of the discrimination circuit, 209 is the output terminal D
The signal waveform of OUT, 210 is a discharge current waveform flowing into the ground through the output MOSFET Q15, and 211 is a ground pad voltage waveform of the memory chip. FIG. 3 shows an embodiment of the pulse width discrimination circuit. In FIG. 3, 31 is an input terminal, 32 is a delay circuit, 33 is an output node of the delay circuit, 34 is a NOR logic gate, and 35 is an output terminal. FIG. 4 is a diagram showing the operation waveforms at the nodes of the circuit of FIG. 3, and 41 to 43 represent the waveforms at the nodes 31, 33 and 35, respectively. Further, in FIG. 4, the solid line shows the operation waveform when the pulse width of the input signal is wide, and the broken line shows the operation waveform when the pulse width is narrow. FIG. 5 is a circuit diagram of a semiconductor memory according to the second embodiment of the present invention. In FIG. 5, A0, Ai, Ai + 1, and Aj are address terminals, DOUT is an output terminal, 501 to 504 are address buffers and address transition detection circuits, and 505 to 50.
8 is a NAND decoder, 509 to 512 are decoder buffers, 513 to 516 are digit line and data bus line equipotential signal generation circuits, 517 is a pulse width discrimination circuit, 519 is a sense amplifier circuit, 518 and 521 are inverters, 520 , 522 are inverters for driving output MOSFETs, Q1, Q2, Q4, Q5 are digit line load MOSFETs, Q3, Q6 are digit line equipotential MOSFETs, Q7 to Q10 are transfer gate MOSFETs for selecting digit lines, and Q11. , Q
12 is a data bus line load MOSFET, Q13 is a data bus line equipotentializing MOSFET, Q14 to Q17 are sense amplifier inverters controlled by pulse width discrimination circuit output, Q1
8, Q19 are output MOSFETs, C00, Ck0, C0
1, Ck1 are memory cells, D0, ▲ ▼, D1, ▲
▼ is a digit line, DB, ▲ ▼ is a data bus line,
X0 and Xk are word lines, Y0 and Y1 are Y address lines, and E
Q is an equipotential signal line, A0, ▲ ▼, Ai, ▲
▼, Ai + 1, , Aj, are address buffer output lines, OS, OS
i, OSi + 1, and OSj are address transition detection signal lines. FIG. 6 is a circuit diagram of a conventional semiconductor memory. In FIG. 6, A0, Ai, Ai + 1, and Aj are address terminals,
DOUT is an output terminal, 601 to 604 are address buffers and address transition detection circuits, and 605 to 608 are NANs.
D decoder, 609 to 612 are decoder buffers,
613 to 616 are equal potential signal generation circuits for digit lines and data bus lines, 617 to 618 are sense amplifier circuits, 619 to 620 are inverters for driving output MOSFETs, Q1, Q2, Q4 and Q5 are digit line load MOSFETs, Q3 and Q6 are digit line equipotential MO
SFETs, Q7 to Q10 are transfer gates for selecting digit lines, Q11 and Q12 are data bus line load MOSFETs, and Q13 is a data bus line equipotential MOSF.
ET, Q14, Q15 are output MOSFETs, C, Ck0, C
01, Ck1 are memory cells, D0, ▲ ▼, D1, ▲
▼ is a digit line, DB, ▲ ▼ is a data bus line, X0 and Xk are word lines, Y0 and Y1 are Y address lines, EQ is an equipotential signal line, A0, ▲ ▼, Ai, and ▲.
▼, Ai + 1, , Aj, ▲ ▼ are address buffer output lines, OS, O
Si, OSi + 1, and OSj are address transition detection signal lines. FIG. 7 is a waveform diagram showing the operation of the circuit of FIG. 6. In FIG. 7, 701 is an address signal waveform, 702 is an address transition detection signal waveform, 703 is a word line signal waveform, and 704 is an equal potential. Signal waveform, 705 is digit line signal waveform, 7
06 is a data bus line signal waveform, 707 is an output MOSFE
A gate signal waveform of TQ15, 708 a signal waveform of the output terminal DOUT, 709 a discharge current waveform flowing into the ground through the output MOSFET Q15, and 710 a ground pad voltage waveform of the memory chip.

Claims (1)

[Claims] 1. A memory cell array including a plurality of word lines, bit line pairs, and memory cells, and an equipotential equalizing means for equalizing the potentials of the plurality of bit line pairs in accordance with control pulse signals. A plurality of address input terminals, a decoder for selecting a predetermined word line and a predetermined bit line according to an address input to the address input terminal, and a sense amplifier for amplifying read data read from the memory cell A transfer gate for receiving the output of the sense amplifier and controlling the conduction of the output data, an output buffer circuit for receiving the output of the transfer gate and outputting read data to a data output terminal, and a plurality of address input terminals. Address that detects the change in the input address and generates the control pulse signal The transfer detection circuit and the control pulse signal are generated only when the pulse width of the control pulse signal is longer than the transition time of the gate signal of the output transistor forming the output buffer circuit by a predetermined time to permit conduction of the transfer gate. And a pulse width discrimination circuit for outputting read data to the output buffer.