JPS60224238A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60224238A
JPS60224238A JP59080047A JP8004784A JPS60224238A JP S60224238 A JPS60224238 A JP S60224238A JP 59080047 A JP59080047 A JP 59080047A JP 8004784 A JP8004784 A JP 8004784A JP S60224238 A JPS60224238 A JP S60224238A
Authority
JP
Japan
Prior art keywords
back surface
substrate
semiconductor element
conductor
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59080047A
Other languages
Japanese (ja)
Inventor
Tadashi Yamaguchi
忠士 山口
Akira Sakamoto
章 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59080047A priority Critical patent/JPS60224238A/en
Publication of JPS60224238A publication Critical patent/JPS60224238A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73277—Wire and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

PURPOSE:To simplify the steps and to reduce the contacting resistance by exposing the back surface of a semiconductor element buried in a substrate, and forming a conductor for connecting the wiring pattern of the substrate directly to the back surface. CONSTITUTION:Through holes 12 are formed at a substrate 11. Then, an adhesive tape 13 is bonded to block the holes 12 on the back surface of the substrate 11, a semiconductor element 14 is inserted to the holes 12, and bonded fixedly onto the tape 13. Then, the electrodes of the element 14 and a wiring pattern on the surface of the substrate 11 are connected by wirings 15, and sealed with resin 16. Then, the tape 13 is removed. Subsequently, a conductor 18 for connecting the back surface of the element 14 to the wiring pattern 17 of the bias potential of the back surface of the substrate 11 is formed on the exposed surface. Thereafter, to protect the conductor 18 and the back surface of the element 14, resin is coated thinly.

Description

【発明の詳細な説明】 （技術分野） この発明は、配線ノ４’ターンが形成された基板に半導
体素子を埋め込む構造の半導体装置を製造する方法に関
する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device having a structure in which a semiconductor element is embedded in a substrate on which a 4' wiring turn is formed.

（従来技術） 薄型を目的とした上述構造の半導体装置の従来例を第１
図に示す。この図において、１は配線／４’ターン（図
示せず）を形成したプリント基板で、貫通孔２が形成さ
れる。この貫通孔２内に、ダイボンドシート３上に接着
して半導体素子４が設けられる。この半導体素子４は、
表面の電極が、基板１上の配置ｉｉ　ｐ４ターンにポン
ディグワイヤ５により接続される。また、このポンディ
グワイヤ５による配線部および前記半導体素子部は、樹
脂６により封止される。(Prior art) The first conventional example of a semiconductor device with the above-mentioned structure aimed at thinning is
As shown in the figure. In this figure, 1 is a printed circuit board on which a wiring/4' turn (not shown) is formed, and a through hole 2 is formed therein. A semiconductor element 4 is provided in this through hole 2 and adhered onto a die bond sheet 3 . This semiconductor element 4 is
The surface electrode is connected to the arrangement ii p4 turn on the substrate 1 by a pounding wire 5. Furthermore, the wiring section formed by the bonding wire 5 and the semiconductor element section are sealed with resin 6.

このような従来の装置において、半導体素子４の裏面に
バイアス電位を加える場合には、ダイボンドシート３に
導電性のものを用いることの外に、このダイボンドシー
ト３に、プリント基板１裏面のバイアス電位の配線ノ４
ターンを導電性の接続方法（例えば導電性樹脂）で接続
する必要がある。In such a conventional device, when applying a bias potential to the back surface of the semiconductor element 4, in addition to using a conductive die bond sheet 3, the die bond sheet 3 is also applied with a bias potential on the back surface of the printed circuit board 1. Wiring No. 4
It is necessary to connect the turns using a conductive connection method (eg, conductive resin).

さらに、ダイボンドシート３と半導体素子４の裏面とを
、あらかじめ導電性を有する接続方法で接続しておく必
要がある。Furthermore, it is necessary to connect the die bond sheet 3 and the back surface of the semiconductor element 4 in advance using a conductive connection method.

このように、従来の装置では、半導体素子４の裏面にバ
イアス電位を加えたい場合（Ｎ−ＭＯ８半導体の場合通
常行われる）、半導体素子４の裏面からプリント基板１
の配線ノｆターンまで２度の導電性のある接続を行う必
要があシ、工程が繁雑になった。！た、この接続には、
高温の必要々共晶などのメタリックな接続ができないた
めに導電性樹脂を用いることになるので、２度も接続を
行うと、接触抵抗が高くなるという欠点があった。In this way, in the conventional device, when it is desired to apply a bias potential to the back surface of the semiconductor element 4 (usually done in the case of N-MO8 semiconductor), the printed circuit board 1 is applied from the back surface of the semiconductor element 4.
It was necessary to make two conductive connections up to the F-turn of the wiring, making the process complicated. ! For this connection,
Because a metallic connection such as eutectic cannot be made due to the high temperature required, a conductive resin is used, which has the disadvantage of increasing contact resistance if the connection is made twice.

（発明の目的） この発明は上記の点に鑑みなされたもので、その目的は
、基板に埋め込まれた半導体素子の裏面にバイアス電位
を加える場合に従来の欠点を解決できる半導体装置の製
造方法を提供することにある。(Object of the Invention) The present invention has been made in view of the above points, and its object is to provide a method for manufacturing a semiconductor device that can solve the conventional drawbacks when applying a bias potential to the back surface of a semiconductor element embedded in a substrate. It is about providing.

（発明の概要） この発明の要点は、基板に埋め込まれた半導体素子の裏
面を露出させ、この面に直接、基板の配線パターンと接
続するための導体を形成することにある。(Summary of the Invention) The main point of the present invention is to expose the back surface of a semiconductor element embedded in a substrate, and to form a conductor directly on this surface for connection to a wiring pattern on the substrate.

（実施例） 以下この発明の一実施例を図面を参照して説明する。第
２図はこの発明の一実施例を説明するための断面図であ
る。この図において、１１は配線パターン（図示せず）
を形成したプリント基板で、まず、この基板１１に第２
図（ａ）に示すように貫通孔１２を形成する。次に、同
第２図（ａ）に示すように、基板１１の裏面に、貫通孔
１２を塞ぐ形で、接着剤の付いた耐熱性フレキシブルテ
ープ（以下粘着テープという）１３ｔ−貼夛付ける。次
いで、この粘着テープ１３で底部側が塞がれた前記貫通
孔１２に同じく第２図（ａ）に示すように半導体素子１
４を挿入して、この半導体素子１４ｔ−前記粘着テープ
１３上に接着固定する。しかる後、半導体素子１４の電
極と基板１１表面の配Ｗｊ／”ターンとを同第２図（ａ
）で示すようにワイヤ１５で接続した上で、このワイヤ
１５による配線部および半導体素子部を同第２図（ａｌ
に示すように樹脂１６で封止する。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a sectional view for explaining one embodiment of the present invention. In this figure, 11 is a wiring pattern (not shown)
First, a second layer is formed on this printed circuit board 11.
A through hole 12 is formed as shown in Figure (a). Next, as shown in FIG. 2(a), a heat-resistant flexible tape (hereinafter referred to as adhesive tape) 13t with an adhesive is pasted on the back surface of the substrate 11 so as to close the through hole 12. Next, as shown in FIG. 2(a), the semiconductor element 1 is inserted into the through hole 12 whose bottom side is closed with the adhesive tape 13.
4 is inserted and the semiconductor element 14t is adhesively fixed onto the adhesive tape 13. Thereafter, the electrodes of the semiconductor element 14 and the pattern Wj/'' turn on the surface of the substrate 11 are arranged as shown in FIG.
) as shown in FIG. 2 (al.
It is sealed with resin 16 as shown in FIG.

しかる後、粘着テープ１３を剥離する。すると、半導体
素子１４の裏面、基板１１の被覆されていた裏面部およ
び封止樹脂１６の裏面部が露出する。After that, the adhesive tape 13 is peeled off. Then, the back surface of the semiconductor element 14, the covered back surface of the substrate 11, and the back surface of the sealing resin 16 are exposed.

そこで、次に、第２図（ｂ）に示すように、この露出面
に、半導体素子１４の裏面と基板１１真面のバイアス電
位の配線パターン（第２図（ｂｌでは、特にこの配線パ
ターンを符号１７を付して示す）とを接続するための導
体１８を形成する。この導７体１８は例えば導電性樹脂
（銀ペースト、金ペーストなど）からなる。あるいは、
真空蒸着法により蒸着される金属によシ導体１８を形成
してもよい。Therefore, as shown in FIG. 2(b), a bias potential wiring pattern (especially this wiring pattern in FIG. 2(bl)) is placed on this exposed surface. (shown with reference numeral 17) is formed.This conductor 18 is made of, for example, a conductive resin (silver paste, gold paste, etc.).Alternatively,
The conductor 18 may be formed of metal deposited by vacuum deposition.

その後、この導体１８および半導体素子１４の裏面を保
護するために、あるいは絶縁性を保つために、必要なら
ば、それらに図示しないが樹脂などを薄くコーティング
する。Thereafter, in order to protect the back surfaces of the conductor 18 and the semiconductor element 14 or to maintain insulation, if necessary, they are thinly coated with a resin or the like (not shown).

（発明の効果） 以上の一実施例から明らかなように、この発明の方法で
は、基板に埋め込まれた半導体素子の裏面を露出させ、
この面に直接、基板の配線パターンと接続するための導
体を形成する。したがって、接続の工程は一度であり、
工程の簡略化、接触抵抗の低減を図ることができる。さ
らに、この発明の方法によれば、ダイボンドシートのよ
うな仲介物を省略して、その分、全体の厚さを薄くする
ことができる。よって、得られた装置を薄型製品（ＩＣ
カードや時計など）へ適用することが可能となる。(Effects of the Invention) As is clear from the above embodiment, in the method of the present invention, the back surface of the semiconductor element embedded in the substrate is exposed;
A conductor for connection to the wiring pattern of the board is directly formed on this surface. Therefore, the connection process is one time,
It is possible to simplify the process and reduce contact resistance. Furthermore, according to the method of the present invention, an intermediary such as a die-bonding sheet can be omitted, and the overall thickness can be reduced accordingly. Therefore, the obtained device can be used as a thin product (IC
It can be applied to cards, watches, etc.).

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置を示す断面図、第２図はこの
発明の半導体装置の製造方法の一実施例を説明するため
の断面図である。 １１・・・プリント基板、１２・・・貫通孔、１３・・
・耐熱性フレキシブルテープ（粘着チー７’）、１４・
・・半導体素子、１５・・・ワイヤ、１６・・・樹脂、
１７・・・配線パターン、１８・・・導体。 特許出願人　沖電気工業株式会社 第１図 第２図 ６FIG. 1 is a sectional view showing a conventional semiconductor device, and FIG. 2 is a sectional view illustrating an embodiment of the method for manufacturing a semiconductor device of the present invention. 11... Printed circuit board, 12... Through hole, 13...
・Heat-resistant flexible tape (adhesive 7'), 14・
...Semiconductor element, 15...Wire, 16...Resin,
17... Wiring pattern, 18... Conductor. Patent applicant Oki Electric Industry Co., Ltd. Figure 1 Figure 2 Figure 6

Claims (3)

【特許請求の範囲】[Claims] （１）配線ツヤターンが形成された基板に貫通孔を設け
る工程と、その貫通孔を塞ぐ形で前記基板の裏面に接着
剤の付いたチーｆｔ−貼夛付ける工程と、このテープで
底部側が塞がれた前記貫通孔に挿入して前記テープ上に
半導体素子を接着固定する工程と、その半導体素子の電
極と基板面の配線／４’ターンとをワイヤで接続する工
程と、そのワイヤによる配線部および前記半導体素子部
を樹脂で封止する工程と、この封止工程後に前記テープ
を剥がす工程と、これにより露出した半導体素子裏面と
前記基板裏面に形成された配線パターンとを彎続する導
体を、半導体素子の裏面、基板の裏面および封止樹脂の
裏面部に形成する工程とを具備してなる半導体装置の製
造方法。(1) A step of providing a through hole in the board on which the wiring gloss turn is formed, a step of pasting a tape with adhesive on the back side of the board to close the through hole, and a step of sealing the bottom side with this tape. A step of inserting the semiconductor element into the peeled through hole and adhesively fixing it on the tape, a step of connecting the electrode of the semiconductor element and the wiring/4' turn on the substrate surface with a wire, and wiring with the wire. a step of sealing the part and the semiconductor element part with a resin, a step of peeling off the tape after this sealing step, and a conductor connecting the back surface of the semiconductor element exposed thereby and the wiring pattern formed on the back surface of the substrate. A method for manufacturing a semiconductor device, comprising the steps of: forming on the back surface of a semiconductor element, the back surface of a substrate, and the back surface of a sealing resin. （２）導体として導電性樹脂を用いることを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方法。(2) A method for manufacturing a semiconductor device according to claim 1, characterized in that a conductive resin is used as the conductor. （３）導体として真空蒸着法により蒸着された金属を用
いたことｔ−特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, characterized in that a metal deposited by vacuum evaporation is used as the conductor.
JP59080047A 1984-04-23 1984-04-23 Manufacture of semiconductor device Pending JPS60224238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59080047A JPS60224238A (en) 1984-04-23 1984-04-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59080047A JPS60224238A (en) 1984-04-23 1984-04-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60224238A true JPS60224238A (en) 1985-11-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP59080047A Pending JPS60224238A (en) 1984-04-23 1984-04-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60224238A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1304739A1 (en) * 2001-10-15 2003-04-23 United Test Center Inc. Semiconductor device and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1304739A1 (en) * 2001-10-15 2003-04-23 United Test Center Inc. Semiconductor device and method for fabricating the same

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