JPS6029228B2 - Tape for connecting semiconductor devices - Google Patents

Tape for connecting semiconductor devices

Info

Publication number
JPS6029228B2
JPS6029228B2 JP53018465A JP1846578A JPS6029228B2 JP S6029228 B2 JPS6029228 B2 JP S6029228B2 JP 53018465 A JP53018465 A JP 53018465A JP 1846578 A JP1846578 A JP 1846578A JP S6029228 B2 JPS6029228 B2 JP S6029228B2
Authority
JP
Japan
Prior art keywords
tape
adhesive
wiring pattern
semiconductor element
device hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53018465A
Other languages
Japanese (ja)
Other versions
JPS54111762A (en
Inventor
弘明 奥平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53018465A priority Critical patent/JPS6029228B2/en
Publication of JPS54111762A publication Critical patent/JPS54111762A/en
Publication of JPS6029228B2 publication Critical patent/JPS6029228B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は電気絶縁性を有する樹脂材料から成る可榛性テ
ープ上に、所定形状の導体配線パターンを設けた半導体
素子接続用テープに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tape for connecting semiconductor elements, in which a conductor wiring pattern of a predetermined shape is provided on a flexible tape made of a resin material having electrical insulation properties.

半導体素子接続用テープの平面構造を第1図に断面構造
を第2図に示す。
The planar structure of the tape for connecting semiconductor elements is shown in FIG. 1, and the cross-sectional structure is shown in FIG. 2.

図において電気絶縁性の樹脂材料からなる可榛性テープ
1には該テープの送りを行なうための孔2および半導体
素子を接続するための孔3(以下この孔をデバイス孔と
よぶ)が穿孔されている。また該テープ上には所定形状
の導体配線パターン4が形成されている。該導体パター
ンは一般に、予め前記テープ上に塗布された接着剤5に
より銅箔を接着し、ホトェッチング法により形成される
。該テープと半導体素子6との接続は、テープ上に設け
た配線パターンの前記デバイス孔に突出した部分7(以
下これをインナーリードとよぶ)と半導体素子に設けた
突起電極8との位置合わせを行ない、熱圧着法、共晶法
などの方法により接続される。インナーリード7の一般
的な寸法は幅約100ム長さ約1側であり、半導体素子
1個当りの本数は20〜40本である。
In the figure, a flexible tape 1 made of an electrically insulating resin material has a hole 2 for feeding the tape and a hole 3 for connecting a semiconductor element (hereinafter referred to as a device hole). ing. Further, a conductor wiring pattern 4 having a predetermined shape is formed on the tape. The conductor pattern is generally formed by bonding the copper foil with an adhesive 5 applied on the tape in advance and using a photoetching method. The connection between the tape and the semiconductor element 6 is achieved by aligning the portion 7 of the wiring pattern provided on the tape that protrudes into the device hole (hereinafter referred to as an inner lead) with the protruding electrode 8 provided on the semiconductor element. They are connected using methods such as thermocompression bonding, eutectic bonding, etc. The general dimensions of the inner leads 7 are about 100 mm in width and about 1 side in length, and the number of leads per semiconductor element is 20 to 40.

ところが半導体素子の機能増加等により、電極数の多い
半導体素子を接続する場合には電極数に等しいインナー
リード7を設ける必要がある。そのためにはインナーリ
ード7の幅を小さくしなければならない。しかしインナ
ーリード7の長さは半導体素子の突起電極の位置などの
関係で短かくすることはできず、その結果インナーリー
ド7は細く長いものとなる。このためインナーリード7
は極めて曲りやすくなり、製造工程中での曲りの発生頻
度が増加し、歩蟹りは低下する。このため従釆法ではイ
ンナーリード7の幅を現状より細くすることは困難であ
り、電極数の多い半導体素子を接続することはできない
。本発明の目的は、上記した従来技術の欠点をなくし、
電極数の多い半導体素子の接続を可能にした半導体素子
接続用テープを提供するにある。本発明は従来可操性テ
ープに塗布されていた接着剤を銅箔に塗布して、可榛性
テープと銅箔とを接着することにより、インナーリード
を接着剤薄膜で保持するようにしたものである。これに
よりインナーリードの幅を狭くしても、インナーリード
は綾着剤の薄膜で保持されているため曲ることはなく、
電極数の多い半導体素子の接続が可能となる。以下、実
施例に従い本発明を詳述する。第3図および第4図は本
発明の一実施例を示した図である。樹脂材料からなる可
擬性テープ1と導体配線パターン4とは接着剤5により
接着されている。接着剤薄膜9はデバイス孔3に張出し
、インナーリード7を保持している。接着剤薄膜9の厚
さは5〜20仏であり、一方突起電極8の高さは25〜
35ムであるから、薮着剤薄膜9がデバイス孔3に張出
しても接続上、何ら問題はない。これによりインナーリ
ードの幅が狭くなっても、テープの製造工程などにおい
て曲がる恐れはない。インナーリードの先端は半導体素
子5の突起電極8と接続するため、接続に必要な長さだ
け接着剤薄膜9より突出している。次に本発明の半導体
素子接続用テープの製造方法の一例を示す。
However, due to increased functionality of semiconductor devices, when connecting semiconductor devices with a large number of electrodes, it is necessary to provide inner leads 7 equal to the number of electrodes. For this purpose, the width of the inner lead 7 must be reduced. However, the length of the inner lead 7 cannot be shortened due to the position of the protruding electrode of the semiconductor element, and as a result, the inner lead 7 becomes long and thin. Therefore, inner lead 7
becomes extremely bendable, the frequency of bending occurring during the manufacturing process increases, and the occurrence of bending decreases. For this reason, it is difficult to make the width of the inner lead 7 narrower than the current width using the follow-up method, and it is not possible to connect semiconductor elements with a large number of electrodes. The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art,
An object of the present invention is to provide a tape for connecting semiconductor elements, which enables connection of semiconductor elements having a large number of electrodes. In the present invention, the adhesive that was conventionally applied to the flexible tape is applied to the copper foil, and the flexible tape and the copper foil are bonded together, thereby holding the inner leads with a thin adhesive film. It is. As a result, even if the width of the inner lead is narrowed, the inner lead will not bend because it is held by a thin film of twill adhesive.
It becomes possible to connect semiconductor elements with a large number of electrodes. Hereinafter, the present invention will be explained in detail according to Examples. FIGS. 3 and 4 are diagrams showing an embodiment of the present invention. A fugitive tape 1 made of a resin material and a conductor wiring pattern 4 are bonded together with an adhesive 5. The adhesive thin film 9 overhangs the device hole 3 and holds the inner lead 7. The thickness of the adhesive thin film 9 is 5 to 20 mm, while the height of the protruding electrode 8 is 25 to 20 mm.
35 mm, even if the thick adhesive thin film 9 overhangs the device hole 3, there will be no problem in terms of connection. As a result, even if the width of the inner lead becomes narrow, there is no risk of bending during the tape manufacturing process. In order to connect the tip of the inner lead to the protruding electrode 8 of the semiconductor element 5, it protrudes from the adhesive thin film 9 by a length necessary for connection. Next, an example of a method for manufacturing the tape for connecting semiconductor elements of the present invention will be described.

35仏厚の銅箔にポリィミド系、ェポキシ系等の接着剤
を5〜30仏の厚さに塗布する。
Apply adhesive such as polyimide or epoxy adhesive to a thickness of 5 to 30 mm on a 35 mm thick copper foil.

ついで25側中に切断し、銅箔テープとする。一方12
5仏厚のポリィミドシートを35側中に切断し、ポリィ
ミドテープとする。次にポリイミドシートに所定形状の
スプ。ケット孔およびデバイス孔を穿孔する。このポリ
ィミドテープと銅箔テープとを、前記の銅箔テープに塗
布しておいた接着剤により接着する。接着を終了したテ
ープのデバイス孔部分の断面を第5図に示す。本方法で
は従来法とは異なりデバイス孔3部分の銅箔10にも接
着剤薄膜9が形成されている。次に第6図に示すように
デバイス孔部分の銅箔に形成された接着剤薄膜を水酸化
ナトリウム等のエッチング液を用いて、半導体素子6の
突起電極8群の外周より大きく、溶解除去する。ついで
従来法と同機にホトレジスト塗布プレベーク、露光、現
像、鋼箔のエッチングのいわゆるホトエツチングプロセ
スにより、所定形状の配線パターンを形成する。なおデ
バイス孔に露出した銅箔部分はエッチング工程前に予め
保護用樹脂を塗布しておきエッチング工程中にデバイス
孔部分の銅箔が裏面からエッチングされるのを防止する
。上記の方法を用いることにより、第3図に示したよう
なデバイス孔に張出した配線パターンを接着剤薄膜で支
えた構造のテープを作成することができる。なお、配線
パターンと半導体素子の突起電極との接合をAu−Sn
共晶接合の如く比較的低温(約280oo)で行ない、
かつ接着剤に耐熱性の大きいボリィミド系接着剤を用い
た場合等はデバイス孔部分に形成した接着剤薄膜を半導
体素子の突起電極群の外周より大きく溶解除去すること
なく、配線パターンの表側(ポリィミドテープを接着し
ていない側)に半導体素子を接続し、使用に供すること
も可能である。
Then, it is cut into 25 sides to obtain a copper foil tape. On the other hand 12
A polyimide sheet with a thickness of 5 mm is cut into 35 mm sides to obtain a polyimide tape. Next, spray the specified shape onto the polyimide sheet. Drill the socket holes and device holes. This polyimide tape and copper foil tape are bonded together using the adhesive applied to the copper foil tape. FIG. 5 shows a cross section of the device hole portion of the tape after adhesion. In this method, unlike the conventional method, the adhesive thin film 9 is also formed on the copper foil 10 in the device hole 3 portion. Next, as shown in FIG. 6, the adhesive thin film formed on the copper foil in the device hole area is dissolved and removed using an etching solution such as sodium hydroxide to a size larger than the outer periphery of the 8 groups of protruding electrodes of the semiconductor element 6. . Next, a wiring pattern of a predetermined shape is formed by a so-called photoetching process of applying photoresist, pre-baking, exposing, developing, and etching the steel foil using the same machine as the conventional method. Note that the copper foil portion exposed in the device hole is coated with a protective resin before the etching process to prevent the copper foil in the device hole portion from being etched from the back side during the etching process. By using the above method, it is possible to create a tape having a structure in which a wiring pattern extending into a device hole is supported by a thin adhesive film as shown in FIG. 3. Note that the bond between the wiring pattern and the protruding electrode of the semiconductor element is made of Au-Sn.
Performed at a relatively low temperature (about 280 oo) like eutectic bonding,
In addition, when a polyimide adhesive with high heat resistance is used as the adhesive, the adhesive thin film formed in the device hole portion is not dissolved and removed to a greater extent than the outer periphery of the protruding electrode group of the semiconductor element. It is also possible to connect a semiconductor element to the side to which mido tape is not attached and use it.

以上説明したごとく本発明によればインナーリード幅を
狭くすることが可能となり、電極数の多い半導体素子を
接続することが可能になった。
As explained above, according to the present invention, it has become possible to narrow the inner lead width, and it has become possible to connect semiconductor elements with a large number of electrodes.

また、製造工程中でインナーリードが曲ることによるテ
−フ。製造の歩留り低下を防止できる。
Also, the inner lead is bent during the manufacturing process. It is possible to prevent a decrease in manufacturing yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のテープの構造を示す平面図、第2図は従
来のテープの構造を示す断面図、第3図は本発明のテー
プの構造を示す平面図、第4図は本発明のテープの構造
を示す断面図、第5図および第6図は本発明のテープの
製作法を示す図である。 1・・・・・・可榛・性樹脂テープ、2・・・・・・ス
プロケット孔、3・・・・・・デバイス孔、4・・・・
・・配線パターン、5・・・・・・接着剤、6・・・・
・・半導体素子、7・・・・・・インナーリード、8・
・・・・・突起電極、9・・・・・・接着剤薄膜、10
・・・・・・鋼箔。 汁1図 汁2図 才3図 オナ図 オS図 介6図
Fig. 1 is a plan view showing the structure of a conventional tape, Fig. 2 is a sectional view showing the structure of a conventional tape, Fig. 3 is a plan view showing the structure of the tape of the present invention, and Fig. 4 is a plan view showing the structure of the tape of the present invention. 5 and 6 are cross-sectional views showing the structure of the tape, and are diagrams showing a method of manufacturing the tape of the present invention. 1... Flexible resin tape, 2... Sprocket hole, 3... Device hole, 4...
...Wiring pattern, 5...Adhesive, 6...
...Semiconductor element, 7...Inner lead, 8.
... Protruding electrode, 9 ... Adhesive thin film, 10
・・・・・・Steel foil. Juice 1 figure Juice 2 figure Age 3 figure Masturbation figure S figure S figure 6 figure

Claims (1)

【特許請求の範囲】[Claims] 1 電気絶縁性を有する樹脂からなる可撓性を有するテ
ープと、このテープの所定箇所に穿設されたデバイス孔
と、上記テープの片面にテープの長さ方向に接着剤で接
着されかつその一部が上記デバイス孔に対向して突出し
ている導体配線パターンよりなる半導体素子接続用テー
プにおいて、上記のデバイス孔に対向して突出している
導体配線パターンの少なくとも半導体素子の接続される
部分を除いて上記の接着剤層と同一材料で裏打ちされて
いることを特徴とする半導体素子接続用テープ。
1 A flexible tape made of electrically insulating resin, device holes drilled at predetermined locations on this tape, and one side of the tape adhered with an adhesive in the length direction of the tape. In a tape for connecting a semiconductor element, which is made of a conductor wiring pattern in which a portion of the conductor wiring pattern protrudes opposite to the device hole, at least a portion of the conductor wiring pattern that protrudes opposite to the device hole, excluding at least a portion to which a semiconductor element is connected. A tape for connecting semiconductor devices characterized by being lined with the same material as the adhesive layer described above.
JP53018465A 1978-02-22 1978-02-22 Tape for connecting semiconductor devices Expired JPS6029228B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53018465A JPS6029228B2 (en) 1978-02-22 1978-02-22 Tape for connecting semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53018465A JPS6029228B2 (en) 1978-02-22 1978-02-22 Tape for connecting semiconductor devices

Publications (2)

Publication Number Publication Date
JPS54111762A JPS54111762A (en) 1979-09-01
JPS6029228B2 true JPS6029228B2 (en) 1985-07-09

Family

ID=11972376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53018465A Expired JPS6029228B2 (en) 1978-02-22 1978-02-22 Tape for connecting semiconductor devices

Country Status (1)

Country Link
JP (1) JPS6029228B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105435A (en) * 1988-10-13 1990-04-18 Nec Corp Film carrier type for semiconductor manufacture use
JP2771203B2 (en) * 1988-12-27 1998-07-02 日本電気株式会社 Integrated circuit mounting tape

Also Published As

Publication number Publication date
JPS54111762A (en) 1979-09-01

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