JPS6085547A - Manufacture of lead for connection of semiconductor device - Google Patents
Manufacture of lead for connection of semiconductor deviceInfo
- Publication number
- JPS6085547A JPS6085547A JP19378683A JP19378683A JPS6085547A JP S6085547 A JPS6085547 A JP S6085547A JP 19378683 A JP19378683 A JP 19378683A JP 19378683 A JP19378683 A JP 19378683A JP S6085547 A JPS6085547 A JP S6085547A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- copper foil
- connection
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052737 gold Inorganic materials 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000010931 gold Substances 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 24
- 239000011889 copper foil Substances 0.000 abstract description 22
- 238000007747 plating Methods 0.000 abstract description 8
- 229910052718 tin Inorganic materials 0.000 abstract description 7
- 239000008188 pellet Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 238000005452 bending Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 229910000831 Steel Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の接続用リード製造方法に係り、特
に外部引き出し電極として突起電＠を有する半導体素子
と外部リードとを電気的に接続する為の半導体装置の接
続用リード製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a lead for connecting a semiconductor device, and particularly for connecting a semiconductor device for electrically connecting a semiconductor element having a protruding electrode @ as an external lead electrode and an external lead. The present invention relates to a lead manufacturing method.
半導体素子上の外部引き出し電極と外部リードと全電気
的に接続する方法の一つに、金属ＭＢ線を使用せず可撓
性の電気絶縁フィルム面上に、半導体素子上の電極の位
置に相対するように金属ＩＪ −ドを形成し、かつ半導
体素子の電極端子に金属突起を設け、相対する複数個の
各々を同時に筬続する方法が提案されている。上記接続
方法には、銅を基体とするリードに錫を被せ表面が金で
覆；ｂれた突起電極（バンプ）との間で熱によシ金／錫
の共晶合金を作り接続する合金接続方法と、Ａを基体と
するリードに金を被せ、金バンプとの間で熱と圧力によ
り接続する熱圧着方法とがある。金／錫の合金接続方法
は錫の単結晶によるウィスカーがリード間の電気的短絡
を発生させるという致命的欠陥の為、信頼性全要求され
る半導体装置では金／金の熱用着方法が用いられる傾向
にある。前記接続方法に於ける従来の接続用リードは以
下に述べる工程順で製造される□
（１）二第１図■に示すように可撓性の電気絶糾フィル
ムｌに半導体ベレットより大きな孔（ウィンド一孔）２
′に形成する。One of the methods for fully electrically connecting the external lead electrodes and external leads on the semiconductor element is to connect them to the electrodes on the semiconductor element on a flexible electrically insulating film surface without using metal MB wires. A method has been proposed in which a metal IJ-de is formed as shown in FIG. The above connection method involves coating a copper-based lead with tin and covering the surface with gold; a heat-dissipated gold/tin eutectic alloy is created between the lead and the protruding electrode (bump) to make the connection. There is a connection method and a thermocompression bonding method in which a lead having A as a base is covered with gold and connected to a gold bump using heat and pressure. The gold/tin alloy bonding method has a fatal flaw in that tin single crystal whiskers cause electrical shorts between leads, so the gold/gold thermal bonding method is used in semiconductor devices that require high reliability. There is a tendency to The conventional connection lead in the above connection method is manufactured in the following process order: (1) As shown in Figure 1, holes (larger than the semiconductor pellet) are formed in a flexible electrically insulating film l. Window hole) 2
’ to form.
（２）：フィルム】の一方の主面にポリエステル樹脂等
の接着剤で薄い鋼箔３全貼
（３）：銅箔３の表面に感光性樹脂４を塗布し写真焼付
法で配線用導体部を感光性樹脂４で覆う（第１図０）ｌ
。(2): Paste the entire thin steel foil 3 on one main surface of the film with an adhesive such as polyester resin. (3): Apply photosensitive resin 4 to the surface of the copper foil 3 and photoprint the wiring conductor. Cover with photosensitive resin 4 (Fig. 1 0)
.
（４）：不要な銅箔３をエツチングし部分５を残す（第
１図ａ）。(4): Etch the unnecessary copper foil 3 and leave a portion 5 (FIG. 1a).
（５）：配線用導体５の鋼表面にメッキ法で錫層又は金
層６を被覆する（第１図■）０
かかる製造方法ではウィンド一孔を形成した後、銅箔を
貼着する為、ウィンド一孔部の銅箔にたわみが発生し易
く＠箔は均一に貼着することができず、金属リードに長
さの不整合が生じ高精度な金属リードを製造することが
困難であるという欠点を有しているーこの銅箔のたわみ
はウィンド一孔が大きさに比例しており、半導体素子の
ゲート数が増加し半導体ペレットが大きくなる種金属リ
ードの精度は低下してしまう。(5): Covering the steel surface of the wiring conductor 5 with a tin layer or gold layer 6 by plating (Fig. 1 ■) 0 In this manufacturing method, after forming a window hole, copper foil is pasted. , the copper foil in the window hole tends to bend, making it impossible to stick the foil uniformly, resulting in length mismatch in the metal lead, making it difficult to manufacture high-precision metal leads. This has the drawback that the deflection of this copper foil is proportional to the size of the window hole, and as the number of gates in the semiconductor device increases and the semiconductor pellet becomes larger, the precision of the seed metal lead decreases.
更に銅箔に錫又は金層を被覆する工程に於いてメッキ液
の攪拌等によりリードの折れ、曲がシが発生し易いとい
う欠点を有している。Furthermore, in the step of coating the copper foil with a tin or gold layer, the lead is easily bent or bent due to stirring of the plating solution, etc., which is a disadvantage.
上記欠点は半導体素子の突起電極（バンプ）と金属リー
ドとの確実な接続ができず、その結果ボンディング歩留
を低下させ半導体装置のコストヲ上げてしまう。The above drawback is that the protruding electrodes (bumps) of the semiconductor element cannot be reliably connected to the metal leads, resulting in a decrease in bonding yield and an increase in the cost of the semiconductor device.
更に突起電極のサイズ、間隔を小さくできず半導体ペレ
ットの縮小化金妨げている一因となっている。 ゛
本発明の目的は突起電極（バング）を有する半導体素子
と外部リードとの接続に於いて、前記欠点を除き高精度
な接続かり能な接続用リード全提供することである。Furthermore, the size and spacing of the protruding electrodes cannot be reduced, which is one reason why semiconductor pellets cannot be made smaller. ``An object of the present invention is to provide a complete connection lead that eliminates the above-mentioned drawbacks and enables high-precision connection in connection between a semiconductor element having a protruding electrode (bung) and an external lead.
本発明の特敵は、可撓性の電気絶縁フィルムの一方の主
面に貼着された銅箔に所望の配・線用導体を形成し、そ
の後鍋又は金層を被せ、該配線用導体に相対するように
半導体ペレットよシ大きな貫通孔を設は金属リードを形
成することである。The special feature of the present invention is to form a desired wiring/wiring conductor on a copper foil adhered to one main surface of a flexible electrical insulating film, and then cover the wiring conductor with a pot or a gold layer. A large through hole is formed in the semiconductor pellet so as to face it, and a metal lead is formed.
以下、図面に示す不発明の実施例に基づいて本発明の詳
細な説明する。第２図囚〜第２図（ト）は本発明を示す
もので製造工程順に得られる接続用リードの断面図であ
る。Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. FIGS. 2(a) to 2(g) illustrate the present invention and are cross-sectional views of connection leads obtained in the order of manufacturing steps.
（１）：ポリイミド等のり祷件の電気絶縁フィルムｌの
一方の主面に薄い銅箔３を貼着する（第２図（２））。(1): A thin copper foil 3 is pasted on one main surface of an electrically insulating film l made of polyimide or the like (FIG. 2 (2)).
（２）：銅箔３の表面にフォト・レジス１４ｔの感光性
材料を塗布し写真焼付法で所望の配線用導体部以外を感
光性材料４で覆う（第２図面）。(2): A photosensitive material 14t of photoresist is applied to the surface of the copper foil 3, and areas other than the desired wiring conductor portions are covered with the photosensitive material 4 using a photoprinting method (second drawing).
（３）：銅箔３を陰極として電解金メッキ全行ない配線
用導体部の銅表面に金層６を被覆する（第２図０）。(3): Using the copper foil 3 as a cathode, electrolytic gold plating is performed throughout to coat the copper surface of the wiring conductor portion with a gold layer 6 (FIG. 20).
（４）：電気絶縁フィルム１の他方の主面（銅箔３が貼
着されていない主面）にフォト・レジスト等の感光性材
料７全塗布し写真蝕刻法でウィンド一孔２全形成する（
第２図［Ｆ］）。(4): Apply a photosensitive material 7 such as a photoresist to the other main surface of the electrical insulating film 1 (the main surface to which the copper foil 3 is not attached), and then form a window hole 2 by photolithography. (
Figure 2 [F]).
（５）二上記金属をマスクとして不要な銅箔をエツチン
グウィンド一孔２を形成し、金属リードを形成する（第
２図■，［Ｆ］）。(5) Using the above metal as a mask, etching unnecessary copper foil to form a hole 2 and forming a metal lead (Fig. 2, [F]).
このように銅箔の貼着工程後にウィンド一孔全形成して
いる為、銅箔にたわみが発生せず、銅箔を均一に貼着す
ることができる・
更にウィンド一孔形成工ａ前に電解金メッキを行なって
おり、電解金メッキ工程でのリード折れ、曲が９がない
。In this way, since the entire window hole is formed after the copper foil bonding process, the copper foil does not bend and the copper foil can be bonded uniformly.Furthermore, before the window hole forming step Electrolytic gold plating is performed, so there are no lead breaks or bends during the electrolytic gold plating process.
上記の結果、リード長は均一で折れ、曲がりの少ない金
属リードが形成でき、半導体素子のバンプと確実な接続
が可能で、かつ半導体素子のバンプ・サイズ及び間隔を
小さくでき、半導体ベレット’ｌ縮小できるという利点
を有している。As a result of the above, it is possible to form a metal lead with a uniform lead length and less bending and bending, which enables reliable connection with the bumps of the semiconductor element, and also allows the bump size and spacing of the semiconductor element to be reduced, reducing the size of the semiconductor bullet. It has the advantage of being possible.
本発明により、突起電極分有する半導体素子と外部引出
し用リードとの接続に於いて、確実な接続ができ、高い
ボンディング歩留が得られる。特にその効果は半導体素
子の電極数が増加する程著しくその工業的価値は極めて
大きい。According to the present invention, a reliable connection can be made and a high bonding yield can be obtained in connection between a semiconductor element having a protruding electrode portion and a lead for external extraction. In particular, the effect becomes more pronounced as the number of electrodes in a semiconductor device increases, and its industrial value is extremely large.
尚、本発明の実施例では配線用導体は゛電解金メッキ全
行ない、この金層をマスクとして不要な鋼箔をエツチン
グして形成したが、本発明はこれに限定されることはな
く、写真蝕刻法で所望のパターンを形成し、その後電解
金メッキを行ない銅層に金層を被覆する方法でもかまわ
ない＠しかしながらウィンド孔形成工程に於いて銅箔全
貼着した主面から電気絶縁フィルムがエツチングされな
い手段を構する必要が生じ、本発明の実施例が製法上好
ましい。要は銅箔を貼着し、配線用導体を形成し、その
後、ウィンド一孔を該配線用導体に相対するように設け
、金属リードを形成する方法であればかまわない・In the embodiment of the present invention, the wiring conductor was formed by electrolytic gold plating and etching unnecessary steel foil using this gold layer as a mask, but the present invention is not limited to this, and photo-etching was used. It is also possible to form a desired pattern using electrolytic gold plating, and then electrolytically plate the copper layer with a gold layer. Therefore, the embodiment of the present invention is preferable in terms of manufacturing method. In short, any method is acceptable as long as copper foil is pasted, a wiring conductor is formed, a window hole is then provided opposite the wiring conductor, and a metal lead is formed.
第１図ω〜第１図面は従来の製造方法で工程順に得られ
る接続用リードの断面図である。第２図■〜第２図［Ｆ
］は本発明の実施例を示すもので、製造工程順に得られ
る接続用リードの断面図であるＤ尚、図に於いて
１・・・・・・可撓性の電気絶縁フィルム、２・・・・
・・ウィンド一孔、３・・・・・・銅箔、４，７・・・
・・・感光性樹脂、５・・・・・・配線用導体、６・・
・・・・錫又は金層でおる。
第１図1 to 1 are cross-sectional views of connection leads obtained in the order of steps by a conventional manufacturing method. Figure 2 ■ - Figure 2 [F
] shows an example of the present invention, and is a cross-sectional view of a connection lead obtained in the order of the manufacturing process.・・・
...Window hole, 3...Copper foil, 4,7...
... Photosensitive resin, 5 ... Wiring conductor, 6 ...
...covered with tin or gold layer. Figure 1
Claims (1)
望の配線用導体を形成し、その後場４又は金層で被覆し
、該配線用導体に相対するように半導体ベレットより大
きな貫通孔を設は金属リードを形成することを特徴とす
る半導体装置の接続用リードの製造方法。A desired wiring conductor is formed on the @ foil stuck to the main surface of the flexible electrical insulating film, and then covered with a gold layer or a layer larger than the semiconductor bullet so as to face the wiring conductor. A method of manufacturing a lead for connecting a semiconductor device, the method comprising forming a metal lead by providing a through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19378683A JPS6085547A (en) | 1983-10-17 | 1983-10-17 | Manufacture of lead for connection of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19378683A JPS6085547A (en) | 1983-10-17 | 1983-10-17 | Manufacture of lead for connection of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6085547A true JPS6085547A (en) | 1985-05-15 |
Family
ID=16313768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19378683A Pending JPS6085547A (en) | 1983-10-17 | 1983-10-17 | Manufacture of lead for connection of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6085547A (en) |
-
1983
- 1983-10-17 JP JP19378683A patent/JPS6085547A/en active Pending
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