JPS60219760A - Formation of semiconductor resistant layer - Google Patents
Formation of semiconductor resistant layerInfo
- Publication number
- JPS60219760A JPS60219760A JP7569584A JP7569584A JPS60219760A JP S60219760 A JPS60219760 A JP S60219760A JP 7569584 A JP7569584 A JP 7569584A JP 7569584 A JP7569584 A JP 7569584A JP S60219760 A JPS60219760 A JP S60219760A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon
- doped
- boron
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 title abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052796 boron Inorganic materials 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 3
- 229920005591 polysilicon Polymers 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 238000002161 passivation Methods 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 238000003475 lamination Methods 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000007429 general method Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- -1 boron gold ions Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体抵抗層の形成方法に係り、トランジス
タのバイアス抵抗を内蔵した小信号トランジスタの該抵
抗をポリシリコンで基板に形成する方法に適用される。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of forming a semiconductor resistance layer, and is applied to a method of forming a resistor of a small signal transistor with a built-in transistor bias resistor on a substrate using polysilicon. Ru.
従来トランジスタのバイアス抵抗をポリシリコン層で形
成する（二は次のように行なわれていた。Conventionally, the bias resistor of a transistor is formed from a polysilicon layer (the second method is as follows).
トランジスタの素子をＮＰＮ型で例示し、第１図ないし
第５図によって説明する。An NPN type transistor element will be exemplified and explained with reference to FIGS. 1 to 5.
まず、エミツタ層まで形成され上面に５ｉ０２層（ｌａ
）ｔ−備えたシリコン基体（ｌｌ’を用意する。なお、
エミッタ形成１での工程は一般と変わるところがないの
で説明を省略する（第１図）。次に、バクシヘーショ：
／Ｍ（Ｐ−ＡＳ−８ＧＭ）（２）を膜厚約４ｏｏｏＸ、
膜中のリンψ）の濃度が１．６〜３Ｘ１０ ／ｃｔ：に
形成する（第２図）。次に、減圧化学蒸着法（化学蒸着
をＣＶＤと略称する）によってポリシリコンＮ ｔ３）
’ｌｒデポジション温度約５７５℃、膜厚約４５０Ｏ
Ａに形成する（第３図）。次に、ポリ抵抗形成のための
拡散不純物としてボロン０３）ヲ約３Ｘ１０ ／−のド
ーズ量でイオン注入法によりドープし、ドープドポリシ
リコン膜（３ａ）にする（第４図）。次に、窒素雰囲気
中で９００℃、２０分間程の加熱処理を施し、ドープド
ポリシリコン膜（３＆）々イオン注入されたボロン金活
性化させるアニーリングによってアニールされたドープ
ドポリシリコン膜（３ｂ）にする（第５図）。次に、上
記アニールされたドープドポリシリコンＭ（３ｂ）にフ
ォトエツチングによるバターニングを施し所望の抵抗寸
法、面積のポリ抵抗層（３ｃ）に形成する（図示省略）
。First, the emitter layer is formed and the 5i02 layer (la
)t- Prepare a silicon substrate (ll').
The process of emitter formation 1 is the same as the general process, so the explanation will be omitted (FIG. 1). Next, Bakshihesho:
/M (P-AS-8GM) (2) with a film thickness of about 4oooX,
The concentration of phosphorus ψ) in the film is 1.6 to 3×10 /ct (Figure 2). Next, polysilicon Nt3) is deposited by low pressure chemical vapor deposition method (chemical vapor deposition is abbreviated as CVD).
'lr deposition temperature approximately 575℃, film thickness approximately 450O
Form into A (Figure 3). Next, boron 03) is doped as a diffusion impurity for forming a polyresistance by ion implantation at a dose of about 3.times.10@2 /- to form a doped polysilicon film (3a) (FIG. 4). Next, the doped polysilicon film (3b) is annealed by heat treatment at 900°C for about 20 minutes in a nitrogen atmosphere to activate the boron gold ions implanted in the doped polysilicon film (3&). (Figure 5). Next, the annealed doped polysilicon M (3b) is patterned by photoetching to form a polyresistance layer (3c) with desired resistance dimensions and area (not shown).
.
上記従来の方法による抵抗層の形成方法には次Ｃ二あげ
る要因により抵抗値にばらつきが太きく、再現性と制御
性が乏しいなどの欠点があった。The above-mentioned conventional method for forming a resistive layer has drawbacks such as large variations in resistance values due to the following factors and poor reproducibility and controllability.
捷ず、抵抗（＋Ｉ ’にきわめるものとして次の３要素
がある。There are the following three factors that lead to resistance (+I') without change.
（ａ） ポリシリコン膜中にドープする拡散不純物のホ
ロンの添加量のオーダー。(a) Order of the amount of holon, a diffusion impurity doped into a polysilicon film.
これについては、一般的に均一性は高添加程、つまり高
濃度程有利である。In this regard, generally speaking, the higher the addition, the higher the concentration, the more advantageous the uniformity is.
（ｂ） ポリシリコン膜に不純物を添加して得られるポ
リシリコン膜のシート抵抗値はその膜質によって左右さ
れ、それを決冗させるパラメータとしてポリシリコンの
成長温度がある。この要因は、添加不純物が一足であっ
てもポリシリコンの成長温度の変化によってポリシリコ
ンのシート抵抗０１カ変化する基本性質として表われる
。(b) The sheet resistance value of a polysilicon film obtained by adding impurities to a polysilicon film depends on its film quality, and the growth temperature of polysilicon is a parameter that affects this. This factor is manifested in the basic property that the sheet resistance of polysilicon changes with a change in the growth temperature of polysilicon even if the amount of added impurity is small.
（ｃ） ポリシリコン膜とこれにドープされる不純物は
、後のアニーリングの熱処理によって活性化されるが、
この場合ポリシリコン膜直下の下地の膜に拡散不純物を
含んだ膜が存在すると、アニールの熱処理によってポー
ラスなポリシリコン膜の側へこの不純物が浸み出し、ポ
リシリコン中の不純物濃度を相殺させる現象を起こし、
最終的にポリ抵抗層の抵抗値を変化させる。(c) The polysilicon film and the impurities doped into it are activated by the subsequent annealing heat treatment, but
In this case, if there is a film containing diffused impurities in the underlying film directly below the polysilicon film, this impurity will seep into the porous polysilicon film due to the annealing heat treatment, canceling out the impurity concentration in the polysilicon film. wake up,
Finally, the resistance value of the poly resistance layer is changed.
上記（ａ）、（ｂ）、（ｅ）の要素は、従来のポリシリ
コン成長温度が、成長温度とポリシリコンのシート抵抗
値との基本関係においてシート抵抗が低目になる５７５
℃近く、従って添加不純物量が一般的に高濃度程均−性
に有利という条件に反して少な目、例えばＱｄ−３Ｘ１
０ ／ｊ程の不純物量としていた。The factors (a), (b), and (e) above are such that the conventional polysilicon growth temperature has a low sheet resistance in the basic relationship between the growth temperature and the sheet resistance value of polysilicon.575
℃, and therefore the amount of added impurities is relatively small, contrary to the condition that generally higher concentrations are advantageous for uniformity, such as Qd-3X1.
The amount of impurities was about 0/j.
次に、上記（ｅ）の要素は、実際に膜中のリン濃度が１
．６−３刈Ｑ ２”７ｃｍ３程のきわめて高いＰ−Ａｓ
−８Ｇのパッシベーション膜を有しており、アニーリン
グの熱処理によってポリシリコン側へ不純物のリンが浸
み出し、ポリシリコンのシート抵抗厘ヲ変化させる現象
が認められる。Next, in the element (e) above, the phosphorus concentration in the film is actually 1.
．． 6-3 Cut Q Very high P-As of about 2”7cm3
It has a -8G passivation film, and it is observed that the impurity phosphorus seeps into the polysilicon side by annealing heat treatment, causing a change in the sheet resistance of the polysilicon.
この発明は上記従来の問題点に鑑み、ポリシリコン抵抗
層の抵抗値を安定させるように改良した形成方法を提供
する。In view of the above-mentioned conventional problems, the present invention provides an improved formation method for stabilizing the resistance value of a polysilicon resistance layer.
この発明にかかる半導体素子（二内蔵された半導体抵抗
層の形成方法は、シリコン基体上に形成されたＰ−Ａｓ
−８Ｇ膜を介してノンドーグのＣＶＤ ５ｉＣｈ膜を被
着して２層構造のパッシベーション膜を形成し、さらに
積層して６２０℃にてポリシリコン膜を被着したのちイ
オン注入法によってボロンをドーグさせるもので、良好
なパッシベーション機能と、ポリシリコンの成長温度を
高くかつ添加不純物濃度を高くすることによりシート抵
抗値、と不純物濃度均一化とを？Ｒ３間に得る。The method for forming a semiconductor resistor layer (incorporated in a semiconductor element) according to the present invention is to
A non-doped CVD 5iCh film is deposited through the -8G film to form a two-layer passivation film, and after further lamination, a polysilicon film is deposited at 620°C, and boron is doped by ion implantation. Is it possible to achieve a good passivation function, a high polysilicon growth temperature, and a high added impurity concentration to improve sheet resistance and uniform impurity concentration? Obtained between R3.
次にこの発明の１実施例につき図面を参照して詳細に説
明する。Next, one embodiment of the present invention will be described in detail with reference to the drawings.
なお、この実施例の説明（二おいて、従来方法と変わら
ない工程Ｃ：ついては説明を省略し、相違する部分につ
き説明する。It should be noted that the explanation of this embodiment (2, step C, which is the same as the conventional method) will be omitted, and only the different parts will be explained.
まず、一般の方法によってエミツタ層まで形成され、上
面Ｃ二ＳｔＯ，膜が形成されてなる半導体基体ｔｔ）
” 、常圧ＣＶＤ法等の方法”’ＣＰ−Ａｓ−ＰＳＧ
１！Ｘ （ＩＩ）ｋ厚さが約２０００人、膜中のリン濃
度が１．６〜３×１０／ｃｒｎＣ二形成し、さらに、積
層させてノンドープドＳｉｎ。First, a semiconductor substrate (tt) is formed up to the emitter layer by a general method, and a C2StO film is formed on the upper surface.
``, atmospheric pressure CVD method, etc.''CP-As-PSG
1! X(II)k thickness is about 2000, phosphorus concentration in the film is 1.6~3×10/crnC2, and non-doped Sin is further laminated.
膜ａ１１さ約２００ＯＡになるように形成する（第６図
）。次に、減圧ＣＶＤ法によってポリシリコン膜ｔ１３
ｎ６２０℃前後の成長温度で厚さが約４５０ＯＡ 仁な
るよう（＝形成する（第７図）。爾後のポリシリコンｇ
ｉｌｌへのイオン注入工程以降は従来の第４図、第５図
ζ二足し説明された如くしてポリ抵抗層が形成される。The film a11 is formed to have a thickness of about 200 OA (FIG. 6). Next, a polysilicon film t13 is formed by low pressure CVD method.
Formed at a growth temperature of about 620°C to a thickness of about 450 OA (Figure 7).Then the polysilicon g
After the step of ion implantation into ill, a poly resistance layer is formed in the conventional manner as described by adding two ζ in FIGS. 4 and 5.
この発明には次にあける利点がある。 This invention has the following advantages.
（＆） 一般的に不純物濃度の均一化に有利であるポリ
シリコン膜中への拡散不純物ボロン注大量の増加方向は
、第８図に示す相関図からポリシリコンの成長温度が６
２０℃近辺の時に限られる。図のへ曲線はホロンインプ
ラドーズ量が２．６ＸＩＯ／＝ｔの場合、８曲線は８Ｘ
１０ ／＝！の場合全夫々示す。(&) Generally speaking, the direction of increase in the amount of boron diffused into the polysilicon film, which is advantageous for making the impurity concentration uniform, is determined by the correlation diagram shown in Figure 8 when the polysilicon growth temperature is 6.
Only when the temperature is around 20℃. The curve in the figure is 8X when the holon implantation dose is 2.6XIO/=t.
10 /=! In the case of , all are shown.
（ｂ） 一般的に均一化に有利であるポリシリコン膜中
への拡散不純物ボロンの注入量の増加方向は第９図に示
される相関図によっても明確である。(b) The direction of increase in the amount of boron diffusion impurity implanted into the polysilicon film, which is generally advantageous for uniformity, is also clear from the correlation diagram shown in FIG.
（Ｃ） ポリシリコン膜が接する下地の膜にリンなどの
拡散不純物が含１れる膜構造におけるポリ抵抗値への影
響度合は第１０図に示す相関図に明瞭に認められ、極め
て強い要因である。すなわち、図の自、０２線に挾まれ
た域は従来の方法によるＰｓのばらつきの範囲、ＤＩ、
Ｄ２線に挾まれた域は本発明の方法によるＰｓのばらつ
きが極めて小さいことが明瞭に示されている。(C) The degree of influence on the poly resistance value in a film structure in which the underlying film in contact with the polysilicon film contains diffusion impurities such as phosphorus is clearly seen in the correlation diagram shown in Figure 10, and is an extremely strong factor. . In other words, the area between the lines 02 and 02 in the figure is the range of variation in Ps according to the conventional method, DI,
It is clearly shown that the variation in Ps obtained by the method of the present invention is extremely small in the area between the D2 lines.
（ｄ） この発明によるポリ抵抗形成方法のポリ抵抗１
１０．ばらつきは第１１図に示すように、従来のＥ、〜
Ｅ４によるばらつき菫の±４４チに対し、本発明のＦ。(d) Polyresistance 1 of the polyresistance forming method according to the present invention
10. As shown in Figure 11, the variations are as follows:
F of the present invention is different from ±44 chi of the variation violet by E4.
〜Ｆ４に↓るばらつ＠量は±１６チ（９５０±１００Ｑ
／口）で、従来の約１／３と小さく、効果の顕著なこと
が明瞭である。～F4 ↓ variation @ amount is ±16chi (950±100Q
/mouth), which is about 1/3 smaller than the conventional one, and it is clear that the effect is significant.
（ｅ） ポリシリコンの成長温度を従来よりも約５０℃
高くシ、公知の６２５℃以上の高温で形成された安定な
膜質の粒子サイズと変わらないものとした。(e) Increased polysilicon growth temperature by approximately 50°C compared to conventional methods.
The particle size was set to be the same as that of a known stable film formed at a high temperature of 625° C. or higher.
このように、本発明のポリシリコン膜は丁でに述べたよ
う（ニバツシベーション膜を改良して達成されている。As described above, the polysilicon film of the present invention is achieved by improving the nivatization film.
叙上の如く、本発明の製造方法によ）１ば、半導体素子
の品質、歩留全大幅に改良する顕著な効果がある。筐た
、この発明は実施も容易である上（二、工程も多くなら
ない利点もある。As mentioned above, the manufacturing method of the present invention has the remarkable effect of significantly improving the overall quality and yield of semiconductor devices. Furthermore, this invention is easy to implement (second, it does not require a large number of steps).
なお、実施例ＶｉＮＰＮ型トランジスタについて示した
がこれに限られず、ＰＮＰ型トランジスタについても、
またこの他の素子についても適用できることは勿論であ
る。Although the example shows a ViNPN type transistor, the present invention is not limited to this, and a PNP type transistor may also be used.
Of course, the present invention can also be applied to other elements.
第１図ないし第５図は従来の半導体抵抗層の形成方法を
工程順（二示すいずれも断面図、第６図および第７図は
本発明の半導体抵抗層の形成力法の一部を示すいずれも
断面図、第８図はポリシリコンの成長温度とボロンのド
ーズ散によるシート抵抗値との相関を示す線図、第９図
はアニール温度が９００℃から１０００℃に変化した場
合にボロンドーズ惜別のシート抵抗値の変化度合を示す
線図、第１０図はポリシリコン下地の膜にリンの不純物
の有無によるボロン注入量とポリシリコンシート抵抗値
との相関を示す線図、第１１図はポリ抵抗層コントロー
ルの実Ｓ＊’を従来と本発明と比較して示す線図である
。
１ 半導体基体
１１Ｐ−Ａｓ−３Ｏ膜
１２ ノンドーグドＳｉＯズ膜
１３ ポリシリコン膜
代理人 弁理士 井 上 −男
第 １ 図
第 ２ 図
第 ３ 図
第 ４ 図
第 ５ 図
第 ６ −
第 ７ 図
第 ８ 図
ポリンリコン＠Ａ＼
プボ温渡 −
第 ９ 図
第１０図
第１１図Figures 1 to 5 show a conventional method for forming a semiconductor resistance layer in the order of steps (both are cross-sectional views), and Figures 6 and 7 show a part of the process for forming a semiconductor resistance layer according to the present invention. All are cross-sectional views. Figure 8 is a diagram showing the correlation between polysilicon growth temperature and sheet resistance due to boron dose dispersion. Figure 9 is a diagram showing the correlation between the polysilicon growth temperature and the sheet resistance value due to boron dose dispersion. Figure 9 shows the boron dose separation when the annealing temperature changes from 900°C to 1000°C. Figure 10 is a diagram showing the correlation between the amount of boron implanted and the polysilicon sheet resistance depending on the presence or absence of phosphorus impurity in the polysilicon underlying film. 1 is a diagram showing a comparison of actual S*' of resistance layer control between the conventional and the present invention. 1 Semiconductor substrate 11P-As-3O film 12 Non-doped SiO2 film 13 Polysilicon film Agent Patent attorney Inoue-Otoko 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 - Figure 7 Figure 8
Claims (1)
成されたＰ−ＡＳ−８Ｇ膜を介して化学蒸着法によりノ
ンドーグの酸化シリコン膜を形成する工程と、前記酸化
シリコン膜（二項層して６２０℃にてポリシリコン膜を
被着する工程と、前記ポリシリコン層にイオン注入法で
ボロンをドープさせる工程を含み形成されることを特徴
とする半導体抵抗層の形成方法。A process of forming a non-doped silicon oxide film by chemical vapor deposition via a P-AS-8G film formed on a silicon substrate, and a step of forming a non-doped silicon oxide film (a bilayer layer) built into a semiconductor element, through a P-AS-8G film formed on a silicon substrate. 1. A method for forming a semiconductor resistance layer, comprising the steps of: depositing a polysilicon film at 620° C.; and doping the polysilicon layer with boron by ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59075695A JPH06101535B2 (en) | 1984-04-17 | 1984-04-17 | Method for forming semiconductor resistance layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59075695A JPH06101535B2 (en) | 1984-04-17 | 1984-04-17 | Method for forming semiconductor resistance layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60219760A true JPS60219760A (en) | 1985-11-02 |
| JPH06101535B2 JPH06101535B2 (en) | 1994-12-12 |
Family
ID=13583597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59075695A Expired - Lifetime JPH06101535B2 (en) | 1984-04-17 | 1984-04-17 | Method for forming semiconductor resistance layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101535B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210660A (en) * | 1981-06-19 | 1982-12-24 | Seiko Epson Corp | Static ram |
| JPS5888114A (en) * | 1981-11-18 | 1983-05-26 | Hitachi Ltd | Process for impurity diffusion |
-
1984
- 1984-04-17 JP JP59075695A patent/JPH06101535B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210660A (en) * | 1981-06-19 | 1982-12-24 | Seiko Epson Corp | Static ram |
| JPS5888114A (en) * | 1981-11-18 | 1983-05-26 | Hitachi Ltd | Process for impurity diffusion |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06101535B2 (en) | 1994-12-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |