JPH0395965A - Complementary type thin-film transistor - Google Patents

Abstract

PURPOSE:To reduce a photolithography process once, enable an impurities diffusion layer to be of low resistance, and reduce variation of resistance by providing a gate insulation film on source and drain regions of only either of a P-channel type and an N-channel type thin-film transistors which are equipped with the source and drain regions. CONSTITUTION:A P-type impurities region is covered with photolithography and phosphor is implanted into an N-type impurity region by ion implantation. After eliminating an oxide film 3 on source and drain regions of an N-channel transistor with a resistor 5 and a gate electrode 4 as a mask upon ion- implantation, the resist 5 on the entire surface is eliminated and boron ions are implanted at 40keV by ion implantation. When borons are laminated at this energy, boron ions penetrate a silicon layer at the source and drain regions of the N-channel transistor, so that an N-type transistor is formed in spite of implantation of boron.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to complementary transistors.

[Prior art]

Traditionally, photolithography and impurity diffusion have been used to manufacture complementary transistors consisting of a P-channel transistor and an N-channel transistor.
A method of forming a P-type semiconductor region and an N-type semiconductor region is used. If this method is used, photolithography is required two or more times to form the P-type and N-type regions. This method will be explained according to FIG. The P-type semiconductor region is covered with a resist or the like by photolithography, and an N-type impurity such as phosphorus is implanted by ion implantation or the like.

After removing the cover such as resist, the N-type semiconductor region is covered using a similar method to form a P-type semiconductor region.

One way to reduce the number of photolithography operations is to use compensate.

As shown in FIG. 2, P-type and N-type semiconductor regions are formed by introducing one impurity in a larger amount than the other impurity. However, this method is difficult to control impurity diffusion, especially in the case of thin film transistors.

〔the purpose〕

An object of the present invention is to provide a transistor having an impurity diffusion layer with a lower resistance and smaller variation in resistance than a transistor obtained by a conventional compensate method, using a simple structure and manufacturing method.

[structure]

The complementary thin film transistor of the present invention is either a P-channel thin film transistor having a source and drain region made of a P-type semiconductor thin film, or an N-channel thin film transistor having a source and drain region made of an N-type semiconductor thin film. It is characterized by having a gate insulating film only on the source and drain regions of the transistor.

〔Example〕

The structure and manufacturing method of a complementary thin film transistor in which impurity diffusion is performed in one photolithography process with good controllability will be described with reference to FIGS. 3 and 4. FIG.

1,000 layers of amorphous silicon were deposited on the MA#C substrate 1 by chemical vapor deposition, and the element semiconductor layer 2 was separated into islands using photolithography and etching. 10 on the surface of amorphous silicon by thermal oxidation.
An oxide film (gate insulating film 3) was formed. After depositing 3,000 ml of phosphorous-doped polycone as a gate electrode material by chemical vapor deposition, a gate electrode 4 was formed using photolithography and etching (FIG. 3a).

The P-type impurity region was covered by photolithography, and phosphorous was implanted into the N-type impurity region by ion implantation (FIG. 3b). After removing the oxide film 3 on the source and drain regions of the N-channel transistor using the resist 5 and gate electrode 4 as masks during ion implantation, the resist 5 was removed from the entire surface, and boron ions were implanted at 40 KeV ( Figure 3C). When boron is implanted with this energy, boron ions penetrate through the silicon layer in the source and drain regions of an N-channel transistor, so it becomes an N-type semiconductor despite boron implantation (
Figure 4). Thereafter, after activation and deposition of an interlayer insulating film, contact holes are opened and electrode wiring made of aluminum is performed. Although the method for removing the oxide film on the source and drain regions of an N-channel transistor has been described here, the method for removing the oxide film on the source and drain regions of a P-channel transistor is also similar. In this case, phosphorus ions penetrate through the silicon layer of the source and drain regions of the P-channel transistor, resulting in a P-type semiconductor.

〔effect〕

The present invention can reduce the number of photolithography steps by one step, and the transistor of the present invention has an impurity diffusion layer with lower resistance and smaller variation in resistance than that obtained by the conventional compensate process.

[Brief explanation of drawings]

Figures 1 (a) to (c) show a conventional transistor manufacturing process of a type that requires two photolithography steps, and Figure 2 shows the state of impurity diffusion in a transistor by the conventional compensate method. It's a model. FIGS. 3(a) to 3(c) show examples of manufacturing steps for the transistor of the present invention. FIG. 4 is a model showing the state of impurity diffusion in the transistor of the present invention obtained by the method shown in FIG. 1... Insulating substrate 2... Semiconductor layer 3... Gate insulating film 4... Gate electrode 5... Resist
6...Resist Figure 1; } Figure 2 To Figure I - Pch Nch Figure 3 Figure 4 Pch Nch

Claims (1)

[Claims] 1. The source and drain regions of one of the following: a P-channel thin film transistor with a source and drain region made of a P-type semiconductor thin film, and an N-channel thin film transistor with a source and drain region made of an N-type semiconductor thin film. A complementary thin film transistor characterized by having a gate insulating film only on the top.