JPH06101535B2 - Method for forming semiconductor resistance layer - Google Patents
Method for forming semiconductor resistance layerInfo
- Publication number
- JPH06101535B2 JPH06101535B2 JP59075695A JP7569584A JPH06101535B2 JP H06101535 B2 JPH06101535 B2 JP H06101535B2 JP 59075695 A JP59075695 A JP 59075695A JP 7569584 A JP7569584 A JP 7569584A JP H06101535 B2 JPH06101535 B2 JP H06101535B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon
- forming
- resistance layer
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 37
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 239000012535 impurity Substances 0.000 description 19
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体抵抗層の形成方法に係り、トランジス
タのバイアス抵抗を内蔵した小信号トランジスタの該抵
抗をポリシリコンで基板に形成する方法に適用される。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming a semiconductor resistance layer, and is applied to a method of forming the resistance of a small signal transistor including a bias resistance of the transistor on a substrate with polysilicon. It
従来トランジスタのバイアス抵抗をポリシリコン層で形
成するには次のように行なわれていた。トランジスタの
素子をNPN型で例示し、第１図ないし第５図によつて説
明する。Conventionally, the bias resistance of a transistor is formed of a polysilicon layer as follows. The transistor element is exemplified by the NPN type and will be described with reference to FIGS. 1 to 5.
まず、エミツタ層まで形成され上面にSiO2層（1a）を備
えたシリコン基体（１）を用意する。なお、エミツタ形
成までの工程は一般と変わるところがないので説明を省
略する（第１図）。次に、パツシベーシヨン膜（P-As-S
G膜）（２）を膜厚的400Å、膜中のリン（Ｐ）の濃度が
1.6〜３×1021/cm3に形成する（第２図）。次に、減圧
化学蒸着法（化学蒸着をCVDと略称する）によって一般
に用いられるモノシラン（SiH4）を用いたポリシリコン
膜（３）をデポジシヨン温度約575℃、膜厚約4500Åに
形成する（第３図）。次に、ポリ抵抗形成のための拡散
不純物とてボロン（Ｂ）を約３×1014/cm2のドープ量で
イオン注入法によりドープし、ドープドポリシリコン膜
（3a）にする（第４図）。次に、窒素雰囲気中で900
℃、20分間程の加熱処理を施し、ドープドポリシリコン
膜（3a）とイオン注入されたポロンを活性化させるアニ
ーリングによつてアニールされたドープドポリシリコン
膜（3b）にする（第５図）。次に、上記アニールされた
ドープドポリシリコン膜（3b）にフオトエツチングによ
るパターニングを施し所望の抵抗寸法、面積のポリ抵抗
層に形成する（図示省略）。First, a silicon substrate ( 1 ) having an emitter layer formed thereon and having a SiO 2 layer (1a) on its upper surface is prepared. Since the steps up to the formation of the emitter are the same as the general process, the description thereof is omitted (FIG. 1). Next, the passivation film (P-As-S
G film) (2) has a thickness of 400Å and the concentration of phosphorus (P) in the film is
It is formed to 1.6 to 3 × 10 21 / cm 3 (Fig. 2). Next, a low pressure chemical vapor deposition method (chemical vapor deposition is abbreviated as CVD) is used to form a polysilicon film (3) using monosilane (SiH 4 ) generally used at a deposition temperature of about 575 ° C. and a film thickness of about 4500 Å. (Fig. 3). Next, boron (B) is doped as a diffusion impurity for forming a poly resistance by an ion implantation method with a doping amount of about 3 × 10 14 / cm 2 to form a doped polysilicon film (3a) (fourth). Figure). Then 900 in a nitrogen atmosphere
The doped polysilicon film (3a) is annealed by annealing to activate the doped polysilicon film (3a) and the ion-implanted boron (3b) by heat treatment at 20 ° C. for about 20 minutes (FIG. 5). ). Next, the annealed doped polysilicon film (3b) is patterned by photoetching to form a polyresistive layer having a desired resistance dimension and area (not shown).
上記従来の方法による抵抗層の形成方法には次にあげる
要因により抵抗値にばらつきが大きく、再現性と制御性
が乏しいなどの欠点があつた。The conventional method of forming a resistance layer has drawbacks such as a large variation in resistance value due to the following factors, poor reproducibility and controllability.
まず、抵抗値をきわめるものとして次の３要素がある。First, there are the following three elements that determine the resistance value.
（ａ） ポリシリコン膜中にドープする拡散不純物のボ
ロンの添加量のオーダー。(A) Order of the added amount of boron as a diffusion impurity to be doped in the polysilicon film.
これについては、一般的に均一性は高添加程、つまり高
濃度程有利である。In this regard, in general, the higher the addition, that is, the higher the concentration, the more advantageous the uniformity is.
（ｂ） ポリシリコン膜に不純物を添加して得られるポ
リシリコン膜のシート抵抗値はその膜質によつて左右さ
れ、それを決定させるパラメータとしてポリシリコンの
成長温度がある。この要因は、添加不純物が一定であつ
てもポリシリコンの成長温度の変化によつてポリシリコ
ンのシート抵抗値が変化する基本性質として表われる。(B) The sheet resistance value of a polysilicon film obtained by adding impurities to the polysilicon film depends on the film quality, and the growth temperature of polysilicon is a parameter that determines the sheet resistance value. This factor appears as a basic property that the sheet resistance value of polysilicon changes due to changes in the growth temperature of polysilicon even when the added impurities are constant.
（ｃ） ポリシリコン膜とこれにドープされる不純物
は、後のアニーリングの熱処理によつて活性化される
が、この場合ポリシリコン膜直下の下地の膜に拡散不純
物を含んだ膜が存在すると、アニールの熱処理によつて
ポーラスなポリシリコン膜の側へこの不純物が浸み出
し、ポリシリコン中の不純物濃度を相殺させる現象を起
こし、最終的にポリ抵抗層の抵抗値を変化させる。(C) The polysilicon film and the impurities doped therein are activated by the heat treatment for the subsequent annealing. In this case, if a film containing diffusion impurities exists in the underlying film immediately below the polysilicon film, By the annealing heat treatment, the impurities permeate to the side of the porous polysilicon film, causing a phenomenon of canceling the impurity concentration in the polysilicon, and finally changing the resistance value of the poly resistance layer.
上記（ａ），（ｂ），（ｃ）の要素は、従来のポリシリ
コン成長温度が、成長温度とポリシリコンのシート抵抗
値との基本関係においてシート抵抗が低目になる575℃
近く、従つて添加不純物量が一般的に高濃度程均一性に
有利という条件に反して少な目、例えばQd＝３×1014/c
m2程の不純物量としていた。The elements of (a), (b), and (c) above are such that the conventional polysilicon growth temperature has a lower sheet resistance in the basic relationship between the growth temperature and the sheet resistance value of polysilicon at 575 ° C.
Therefore, the amount of added impurities is generally small, contrary to the condition that the higher the concentration, the more advantageous the uniformity is. For example, Qd = 3 × 10 14 / c
The amount of impurities was about m 2 .
次に、上記（ｃ）の要素は、実際に膜中のリン濃度が1.
6〜３×1021/cm3程のきわめて高いP-As-SGのパツシベー
シヨン膜を有しており、アニーリングの熱処理によつて
ポリシリコン膜へ不純物のリンが浸み出し、ポリシリコ
ンのシート抵抗値を変化させる現象が認められる。Next, the element of (c) above actually has a phosphorus concentration of 1.
It has an extremely high passivation film of P-As-SG of about 6 to 3 × 10 21 / cm 3 , and phosphorus, which is an impurity, leaches into the polysilicon film due to the annealing heat treatment, and the sheet resistance of polysilicon A phenomenon that changes the value is recognized.
この発明は上記従来の問題点に鑑み、ポリシリコン抵抗
層の抵抗値を安定させるように改良した形成方法を提供
する。In view of the above conventional problems, the present invention provides a forming method improved so as to stabilize the resistance value of a polysilicon resistance layer.
この発明にかかる半導体素子に内蔵された半導体抵抗層
の形成方法は、シリコン基体上に形成されたP-As-SG膜
を介してノンドープのCVD SiO2膜を被着して２層構造の
バツシベーシヨン膜を形成し、さらに積層して620℃に
てポリシリコン膜を被着したのちイオン注入法によつて
ボロンをドープさせるもので、良好なパツシベーシヨン
機能と、ポリシリコンの成長温度を高くかつ添加不純物
濃度を高くすることによりシート抵抗値と不純物濃度均
一化とを高度に得る。A method of forming a semiconductor resistance layer incorporated in a semiconductor device according to the present invention is a passivation method having a two-layer structure in which a non-doped CVD SiO 2 film is deposited via a P-As-SG film formed on a silicon substrate. A film is formed and further laminated and a polysilicon film is deposited at 620 ° C and then boron is doped by the ion implantation method. It has a good passivation function, a high polysilicon growth temperature and a high impurity content. By increasing the concentration, it is possible to obtain a high sheet resistance value and a uniform impurity concentration.
なお、現状の半導体プロセスでは、ポリシリコンを形成
する場合、一般的には減圧CVD法によりモノシラン（SiH
4）を用い600℃前後の熱分解により達成される。そして
この加熱温度によって形成される多結晶の膜質に変化の
あることが知られている。モノシランを熱分解してシリ
コンを形成する場合、形成温度によって無定形（アモル
ファス）シリコン、無定形＋有形シリコン（多結晶シリ
コン）、有形シリコン、の各状態を生ずる。これら夫々
の境界温度は明確でなかったが、無定形＋有形シリコン
の境界温度を発明者は推定して、これが620℃近傍にあ
ることを明らかにした。これについては第８図によって
後述したところである。すなわち、この温度は不純物を
添加してポリ抵抗を形成して得られるポリ抵抗値が620
℃時をピーク（極大）に、それ以下低温側は無定形で抵
抗値が下がり、それ以上高温例は単結晶方向で抵抗値が
下がる現象で確められた（第８図）。なお、上記現象は
使用されるガス（SiH4）のSiとＨとの結合エネルギによ
ると考えられる。In the current semiconductor process, when polysilicon is formed, monosilane (SiH
4 ) is achieved by thermal decomposition around 600 ℃. It is known that the quality of the polycrystalline film formed changes depending on the heating temperature. When monosilane is pyrolyzed to form silicon, each state of amorphous silicon, amorphous + tangible silicon (polycrystalline silicon), and tangible silicon occurs depending on the formation temperature. Although the boundary temperature of each of these was not clear, the inventor estimated the boundary temperature of amorphous + tangible silicon and clarified that it was around 620 ° C. This will be described later with reference to FIG. That is, at this temperature, the poly resistance value obtained by adding impurities to form a poly resistance is 620.
It was confirmed that the peak value (maximum) at ℃, the resistance value decreases in the low temperature side below that, and the resistance value decreases in the higher temperature examples in the single crystal direction (Fig. 8). It is considered that the above phenomenon is due to the binding energy between Si and H of the gas (SiH 4 ) used.
次にこの発明の１実施例につき図面を参照して詳細に説
明する。Next, one embodiment of the present invention will be described in detail with reference to the drawings.
なお、この実施例の説明において、従来方法と変わらな
い工程については説明を省略し、相違する部分につき説
明する。In the description of this embodiment, steps that are the same as those in the conventional method will be omitted, and different points will be described.
まず、一般の方法によつてエミッタ層まで形成され、上
面にSiO2膜が形成されてなる半導体基体（１）に、常圧
CVD法等の方法でP-As-PSG膜（11）を厚さが約2000Å、
膜中のリン濃度が1.6〜３×1021/cm3に形成し、さら
に、積層させてノンドープドSiO2膜（12）を厚さ約2000
Åになるように形成する（第６図）。次に、モノシラン
（SiH4）を用い、減厚CVD法によつてポリシリコン膜（1
3）を620℃前後の成長温度で厚さが約4500Åになるよう
に形成する（第７図）。爾後のポリシリコン膜（13）へ
のイオン注入工程以降は従来の第４図、第５図に示し説
明された如くしてポリ抵抗層が形成される。First, a semiconductor substrate (1) having an emitter layer formed by a general method and having a SiO 2 film formed on the upper surface thereof is subjected to atmospheric pressure.
The thickness of P-As-PSG film (11) is about 2000Å by the CVD method.
The phosphorus concentration in the film is formed to be 1.6 to 3 × 10 21 / cm 3, and the non-doped SiO 2 film (12) is further stacked to a thickness of about 2000.
Form so that it becomes Å (Fig. 6). Next, using monosilane (SiH 4 ), a polysilicon film (1
3) is formed at a growth temperature of around 620 ° C to a thickness of approximately 4500Å (Fig. 7). After the ion implantation step into the polysilicon film (13) after that, the poly resistance layer is formed as shown and described in the conventional FIGS. 4 and 5.
この発明には次にあげる利点がある。 This invention has the following advantages.
（ａ） 一般的に不純物濃度の均一化に有利であるポリ
シリコン膜中への拡散不純物ポロン注入量の増加方向
は、第８図に示す相関図からポリシリコンの成長温度が
620℃近辺の時に限られる。図のＡ曲線はボロンインプ
ラドーズ量が2.6×1014/cm2の場合、Ｂ曲線は８×1014/
cm2の場合を夫々示す。(A) In general, the direction of increasing the amount of diffused impurity polon injected into the polysilicon film, which is generally advantageous for making the impurity concentration uniform, shows from the correlation diagram shown in FIG.
Limited to around 620 ℃. The curve A in the figure is 8 × 10 14 / cm 2 when the boron implant dose is 2.6 × 10 14 / cm 2.
The case of cm 2 is shown.
（ｂ） 一般的に均一化に有利であるポリシリコン膜中
への拡散不純物ボロンの注入量の増加方向は第９図に示
される相関図によつても明確である。(B) In general, the direction of increasing the amount of diffusion impurity boron implanted into the polysilicon film, which is advantageous for homogenization, is clear from the correlation diagram shown in FIG.
（ｃ） ポリシリコン膜が接する下地の膜にリンなどの
拡散不純物が含まれる膜構造におけるポリ抵抗値への影
響度合は第10図に示す相関図に明瞭に認められ、極めて
強い要因である。すなわち、図のC1,C2線に挾まれた域
は従来の方法によるρｓのばらつきの範囲、D1,D2線に
挾まれた域は本発明の方法によるρｓのばらつきが極め
て小さいことが明瞭に示されている。(C) The degree of influence on the poly resistance value in the film structure in which the underlying film in contact with the polysilicon film contains diffusion impurities such as phosphorus is clearly recognized in the correlation diagram shown in FIG. 10 and is an extremely strong factor. That is, the region sandwiched by the C 1 and C 2 lines in the figure shows the range of variation of ρs by the conventional method, and the region sandwiched by the D 1 and D 2 lines has extremely small variation of ρs by the method of the present invention. Is clearly shown.
（ｄ） この発明によるポリ抵抗形成方法のポリ抵抗値
ばらつきは第11図に示すように、従来のE1〜E4によるば
らつき量の±44％に対し、本発明のF1〜F4によるばらつ
き量は±16％（950±100Ω／□）で、従来の約1/3と小
さく、効果の顕著なことが明瞭である。(D) As shown in FIG. 11, the variation in the poly resistance value of the poly resistance forming method according to the present invention is ± 44% of the variation amount due to the conventional E 1 to E 4 , and the variation due to F 1 to F 4 of the present invention. The variation amount is ± 16% (950 ± 100Ω / □), which is about 1/3 of the conventional value, and the effect is clear.
このように、本発明のポリシリコン膜はすでに述べたよ
うにパツシベーシヨン膜を改良して達成されている。As described above, the polysilicon film of the present invention is achieved by improving the passivation film as described above.
叙上の如く、本発明の製造方法によれば、半導体素子の
品質、歩留を大幅に改良する顕著な効果がある。また、
この発明は実施も容易である上に、工程も多くならない
利点もある。As described above, according to the manufacturing method of the present invention, there is a remarkable effect of greatly improving the quality and yield of semiconductor devices. Also,
The present invention is easy to implement and has the advantage of not increasing the number of steps.
なお、実施例はNPN型トランジスタについて示したがこ
れに限られず、PNP型トランジスタについても、またこ
の他の素子についても適用できることは勿論である。It should be noted that although the embodiment has been described with respect to the NPN type transistor, the present invention is not limited to this, and it goes without saying that the present invention can be applied to a PNP type transistor and other elements.
第１図ないし第５図は従来の半導体抵抗層の形成方法を
工程順に示すいずれも断面図、第６図および第７図は本
発明の半導体抵抗層の形成方法の一部を示すいずれも断
面図、第８図はポリシリコンの成長温度とポロンのドー
ズ量によるシート抵抗値との相関を示す線図、第９図は
アニール温度が900℃から1000℃に変化した場合にボロ
ンドーズ量別のシート抵抗値の変化度合を示す線図、第
10図はポリシリコン下地の膜にリンの不純物の有無によ
るポロン注入量とポリシリコンシート抵抗値との相関を
示す線図、第11図はポリ抵抗層コントロールの実績を従
来と本発明と比較して示す線図である。１ ……半導体基体 11……P-As-SG膜 12……ノンドープドSiO2膜 13……ポリシリコン膜1 to 5 are sectional views showing a conventional method for forming a semiconductor resistance layer in the order of steps, and FIGS. 6 and 7 are sectional views showing a part of the method for forming a semiconductor resistance layer according to the present invention. Fig. 8 is a diagram showing the correlation between the growth temperature of polysilicon and the sheet resistance value depending on the dose of boron, and Fig. 9 is a sheet by boron dose when the annealing temperature changes from 900 ° C to 1000 ° C. A diagram showing the degree of change in resistance,
FIG. 10 is a diagram showing the correlation between the amount of implanted boron and the resistance value of the polysilicon sheet depending on the presence or absence of phosphorus impurities in the film underlying the polysilicon, and FIG. 11 compares the actual results of the control of the poly resistance layer with those of the present invention. FIG. 1 …… Semiconductor substrate 11 …… P-As-SG film 12 …… Non-doped SiO 2 film 13 …… Polysilicon film
Claims (1)
ン基体上に形成されたP-As-SG膜を介して化学蒸着法に
よりノンドープの酸化シリコン膜を形成する工程と、前
記酸化シリコン膜に積層して620℃にてポリシリコン膜
を被着する工程と、前記ポリシリコン層にイオン注入法
でボロンをドープさせる工程を含み形成されることを特
徴とする半導体抵抗層の形成方法。1. A step of forming a non-doped silicon oxide film by a chemical vapor deposition method for forming a resistance layer built in a semiconductor element through a P-As-SG film formed on a silicon substrate, and the silicon oxide film. And forming a polysilicon film at 620 ° C. and a step of doping the polysilicon layer with boron by an ion implantation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59075695A JPH06101535B2 (en) | 1984-04-17 | 1984-04-17 | Method for forming semiconductor resistance layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59075695A JPH06101535B2 (en) | 1984-04-17 | 1984-04-17 | Method for forming semiconductor resistance layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60219760A JPS60219760A (en) | 1985-11-02 |
| JPH06101535B2 true JPH06101535B2 (en) | 1994-12-12 |
Family
ID=13583597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59075695A Expired - Lifetime JPH06101535B2 (en) | 1984-04-17 | 1984-04-17 | Method for forming semiconductor resistance layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101535B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210660A (en) * | 1981-06-19 | 1982-12-24 | Seiko Epson Corp | Static ram |
| JPS5888114A (en) * | 1981-11-18 | 1983-05-26 | Hitachi Ltd | Process for impurity diffusion |
-
1984
- 1984-04-17 JP JP59075695A patent/JPH06101535B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60219760A (en) | 1985-11-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |