JPH021935A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To form shallowly a base layer without generating a rediffused layer and moreover, to reduce the resistance of a base extraction electrode by a method wherein a one conductivity type emitter layer is formed in the base layer consisting of a dissimilar conductivity type single crystal Si layer at an emitter layer formation region. CONSTITUTION:An Si3N4 film (a second insulating film) 31 exposed at an emitter formation region is removed to form an opening in a base layer (a doped single crystal Si film) 14, a poly Si film is adhered by a CVD method, arsenic (As) ions are implanted in the poly Si film to form an As-doped poly Si film 23, this film 23 is patterned to make the film 23 remain only at an emitter formation region and a collector contact electrode formation region, which are located in opening parts, and moreover, a heat treatment is performed at a temperature of 850 deg.C to demarcate an n<+> emitter layer 16. Then, an insulating film 24 is adhered by a CVD method, openings are formed in this film 24 to form an emitter electrode 19 and a collector contact electrode 17 on the film 23 and a base electrode 18 is formed on a base extraction electrode 15 to complete a bipolar semiconductor device.

Description

[Detailed Description of the Invention] [Summary] A method of manufacturing a base lead-out electrode type bipolar semiconductor device using a technique of simultaneously growing a single crystal silicon layer and a polycrystalline silicon layer, the base layer can be grown without generating a re-diffusion layer. The first electrode is formed with an opening in the base formation region on the surface of the -i type semiconductor substrate.
A doped silicon film is grown on the insulating film using 5PEG technology to form a base layer made of a single crystal silicon film of a different conductivity type, and a first different conductivity type monocrystalline silicon film is grown on the first insulating film. forming a type polycrystalline silicon film, then selectively covering the formed paste layer with a second insulating film;
a step of stacking a second different conductivity type polycrystalline silicon film on the first different conductivity type polycrystalline silicon film with the second insulating film sandwiched therebetween; then, opening the second doped polycrystalline silicon film; forming a third insulating film on the entire surface including the opening, and opening the second insulating film to open an emitter layer formation region;
Next, the method includes a step of forming an emitter layer of one conductivity type on the base layer made of the single crystal silicon layer of different conductivity types in the emitter layer formation region.

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular, a method for manufacturing a semiconductor device, in which a single crystal silicon layer and a polycrystalline silicon layer are grown simultaneously.
E G (Selective Poly-and
Epitaxial-silicon Growth)
The present invention relates to a method of manufacturing a base extraction electrode type bipolar semiconductor device using technology.

Recently, technology development has been progressing in the direction of miniaturizing and increasing the speed of semiconductor devices such as ICs and LSIs.Bipolar semiconductor devices have also developed base lead-out electrode structures, and miniaturization and higher density are progressing. It is being However, the manufacturing method requires further study to improve performance.

[Prior Art] Figure 2 shows a cross-sectional view of a normal bipolar semiconductor device, in which 1 is a p-type silicon substrate, 2 is an n++ buried layer, 3 is an n-type collector layer, and 4 is a S (silicon oxide) film. 5 is a p-type base layer, 6 is an n-type field insulating film, and 5 is a p-type base layer.
++ emitter layer, 7 is a collector contact electrode, 8 is a base electrode, and 9 is an emitter electrode.

Moreover, FIG. 3 shows a structural cross-sectional view of a conventional base extraction electrode type bipolar semiconductor device, and this example shows a structure of a single crystal silicon layer and a polycrystalline silicon layer among several types of base extraction electrode type bipolar semiconductor devices. Growing at the same time 5
1 is a structural cross-sectional view of a base extraction electrode type bipolar semiconductor device using PEG technology. In the figure, 11 is a p-type silicon substrate, 12 is an n++ buried layer, 13 is an n-type collector layer, 1
4 is a p-type base layer, 15 is a base extraction electrode made of a doped polycrystalline silicon film, 16 is an n++ emitter layer, 1
7 is a collector contact electrode, 18 is a base electrode, 19
is an emitter electrode, and 20 is another 5i02 film.

The structure produced by the manufacturing method using such 5PEG technology is very effective in forming a shallow base layer and increasing the speed compared to the normal structure shown in FIG.

FIG. 4 (al to (el) shows a step-by-step cross-sectional view of a conventional manufacturing method of a base-extended electrode type bipolar semiconductor device using the 5PEG technology, and its outline will be explained step by step. forms a shallow base layer, and
This invention relates to an improved manufacturing method for reducing the resistance of base extraction electrodes.

Refer to FIG. 4+al; An n-type collector layer 13 is epitaxially grown on a p-type silicon substrate 11 via an n+ type buried layer 12, and thermally oxidized on the n-type collector layer 13 to form a 5i0
A B-doped polycrystalline silicon film 1 containing boron (B) is formed on the film 21 (thickness: 300 nm).
5' (film thickness 300 nm, boron concentration 10/cIIl)
Then, using lithography technology, 5i02
Membrane 21. An opening is made in the base layer formation region of the B-doped polycrystalline silicon film at 15°. Note that 12' is an n+ type collector contact region, and this region is formed in a step immediately before the formation of the 5i02 film 21.

See Figure 4(b); then at 930°C in a hydrogen atmosphere.
A heat treatment was performed for 915 minutes to remove the natural oxide film on the surface of the base layer formation region with the opening, and then a boron-containing doped silicon film was formed on the B-doped polycrystalline silicon film 15' including the opening. Film (film thickness 50-100 nm
, an impurity concentration of 101 g/cI+ is grown.

Then, a doped polycrystalline silicon film 15 grows on the B-doped polycrystalline silicon film 151, and a doped single-crystalline silicon film 14 grows in the opening.

Refer to FIG. 4(C); Next, the doped silicon film is patterned using lithography technology to form a doped single crystal silicon film 14 that will become a p-type base layer and a doped polycrystalline silicon film 15°+15 that will become a base extraction electrode. The doped polycrystalline silicon film in other parts is removed by etching, leaving a portion of the doped polycrystalline silicon film remaining, and then chemical vapor deposition (chemical vapor deposition) is performed on the top surface.
5i02 film 22 (thickness: 300 nm) by CVD) method.
). Then, the doped polycrystalline silicon film 15'+15 which becomes the base extraction electrode has a film thickness of 350 to 4
It is possible to increase the thickness to about 0.00 nm and reduce its resistance.

Refer to FIG. 4(d); Next, the emitter formation region and the collector contact formation region of the 5i02 film 22 are opened, a polycrystalline silicon film is deposited by the CVD method, and arsenic (As) ions are deposited on the polycrystalline silicon film. was implanted to form an As-doped polycrystalline silicon film 23, patterned to leave the S-doped polycrystalline silicon film 23 only in the emitter formation region of the opening and the collector contact electrode formation region, and further heated to a temperature of 850°C. Heat treated at °C
A + type emifter layer 16 is defined. Note that for forming this emitter layer, a method of heat treatment is adopted while checking characteristics such as h.

Refer to Figure 4 (tel): Next, PSG (
An insulating film 24 such as a phosphosilicate glass film or a 5i02 film is deposited, and an S-doped polycrystalline silicon film 23 is formed by opening this.
Emitter electrode 19. Collector contact electrode 17
, and a base electrode 18 is formed on the base extraction electrode 15 to complete the process.

The above is an outline of the method for forming a base extraction electrode type bipolar semiconductor device to which the 5PEG technology is applied and in which the base extraction electrode is reduced by 17< to lower the base resistance.

[Problems to be Solved by the Invention] By the way, in the above formation method, a thin base layer with a thickness of about 50 to 100 nm is grown in order to operate at high speed.
In addition, the doped polycrystalline silicon film that becomes the base extraction electrode is made thicker and its impurity concentration is increased to lower its resistance. In order to remove the natural oxide film on the surface, heat treatment is performed at 930°C for 15 minutes in a hydrogen atmosphere, and the heating causes boron to be removed from the B-doped polycrystalline silicon film 15' containing a high concentration of boron. Then, a doped silicon film (50 to 100 nm thick) containing boron is grown to form the base layer 14.
When the doped polycrystalline silicon film 15 is formed, a re-diffusion layer is generated in the collector layer 13 on the surface of the base layer forming region, and in severe cases, the film thickness reaches as much as 400 nm. Figure 5 (Al is a diagram showing the problems of the conventional method, and the figure shows only the base layer part enlarged, but 14 in the figure
′ is the re-diffusion layer. If this happens, a problem arises in that the original purpose of increasing the speed of the base lead-out electrode type structure, which is to form a shallow base layer, is lost.

On the other hand, in order to reduce such problems, Fig. 5 (
As shown in b), in the step explained in FIG.
．． A method of forming a base layer 14 and a doped polycrystalline silicon film 15 by opening a base layer forming region in a three-layer film consisting of a B-doped polycrystalline silicon film 15 and an insulating film 25, and then growing a doped silicon film. However, this method has the disadvantage that the step becomes large, and furthermore, re-diffusion from the side surfaces of the B-doped polycrystalline silicon film 15' cannot be prevented.

Therefore, the present invention provides a method for manufacturing a semiconductor device, which aims to solve these problems, form a shallow base layer without generating a re-diffusion layer, and reduce the resistance of the base lead-out electrode. This is what we propose.

[Means for Solving the Problems] The problems are - a step of forming a first insulating film on a conductivity type semiconductor substrate and selectively removing the first insulating film to open a base layer forming region; Next, a silicon film of a different conductivity type is grown on the entire surface including the base layer formation region, and a base layer made of a single crystal silicon film of a different conductivity type is formed in the base layer formation region, and There is a first layer on the insulating film.
forming a polycrystalline silicon film of a different conductivity type, then selectively covering the base layer with a second insulating film, and forming a polycrystalline silicon film of a different conductivity type and the second insulating film and the first polycrystalline silicon film of a different conductivity type. a step of laminating a second polycrystalline silicon film of different conductivity type thereon to form a base extraction electrode film consisting of the first polycrystalline silicon film of different conductivity type and the second polycrystalline silicon film of different conductivity type; Next, an opening is formed in the second different conductivity type polycrystalline silicon film on the second insulating film, a third insulating film is formed on the entire surface including the opening, and further, the second insulating film is The problem is solved by a manufacturing method that includes a step of opening an emitter layer formation region by opening a window, and then a step of forming an emitter layer of one conductivity type on the base layer made of the different conductivity type single crystal silicon layer in the emitter layer formation region. Ru.

[Function] That is, in the present invention, first, a doped silicon film (50 to 100 nm thick) is grown using 5PEG technology on an insulating film (first insulating film) with an opening in the base formation region. ,
A base layer and a first doped polycrystalline silicon are formed.

Next, the formed base layer is covered with a second insulating film,
A second doped polycrystalline silicon film is laminated on the first doped polycrystalline silicon film with the second insulating film in between.

Thereafter, the second doped polycrystalline silicon film and the second insulating film are opened to form an emitter layer in the base layer.

By doing so, re-diffusion (
Out diffusion) can be prevented, the base layer can be formed thin, and the thickness of the base lead-out electrode can also be increased, reducing its resistance, and as a result, the operation speed can be increased.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIGS. 1fa) to 1gl show step-by-step sectional views of the manufacturing method according to the present invention, which will be explained in order.

FIG. 1 (see al; as in the conventional case, a p-type silicon substrate 1
1, an n-type collector layer 13 (
(specific resistance of about 1Ωcm) is epitaxially grown, and its n
The surface of the mold collector layer 13 is thermally oxidized to produce a 5i02 film 21 (thickness: 300 nm; first insulating film). Thermal oxidation is performed by heating to 1000° C. in wet oxygen. Next, the two 5i02 films are patterned using lithography technology to open the base layer formation region. The opening in the base layer formation region is made by etching the 5i02 film using a fluorine gas or by active ion etching.

Note that 121 is an n++ collector contact region.

FIG. 1 (see BL; next, a doped silicon film (film thickness 50 to 100 nm, impurity concentration 10') is grown on the 5i02 film 21 including the open base layer formation region. Then, the 5i02 film 21 A doped polycrystalline silicon film 15 (first polycrystalline silicon film of a different conductivity type) that will become a base extraction electrode is grown on top, and a doped single-crystalline silicon film 14 that will be a base layer is grown in the opening.This epitaxial growth For example, diborane (B2
A low-temperature decomposition method (substrate heating temperature of 540 to 600°C) is used to photodecompose disilane (Si2H6) containing H6), because the photodecomposition method causes less re-diffusion and allows the base layer to be made shallower. .

Figure 1 (see C1; next, Si3N4 (
A silicon nitride film 31 (about 300 nm thick; second insulating film) is deposited by the CVD method, and is etched and hacked to leave the Si3N4 film 31 only on the base layer 14 in the recess. This etchback involves applying a resist film on the Si3N4 film to planarize the surface, and then flattening the surface using a reactive gas (for example, CF4 gas) that has no difference in the etching ratio between the Si3N4 film and the resist film. This is a method of etching uniformly.

See Figure 1(d); Next, a polycrystalline silicon film (thickness: 300 nm) is deposited by decomposing monosilane (SiH4) as a reaction gas at approximately 600°C using a low pressure CVD method. Implant boron ions to a concentration of 102
A B-doped polycrystalline silicon film 15" of about 1/cn (
A second polycrystalline silicon film of different conductivity type is formed. The ion implantation conditions are a dose of M1.5XIO'/ct acceleration energy of about 50 Keν. Note that the B-doped polycrystalline silicon film 15'' is made from B-doped from the beginning instead of being ion-implanted.
A doped polycrystalline silicon film may be deposited by low pressure CVD.

Refer to FIG. 1(Q); Next, the B-doped polycrystalline silicon film 15' is patterned using lithography technology to open an emitter formation region and form a doped polycrystalline silicon film 15' that will become a base extraction electrode. Leaving the +15 portion, the other portions of the doped polycrystalline silicon film 15', 15 are partially etched, and then the B-doped polycrystalline silicon film 15° including the opening of the emitter formation region is etched.
and the surface of the doped polycrystalline silicon film 150 at a temperature of 80°C.
A 5i02 film 22 (300 nm thick) was formed by high-pressure oxidation at 0°C.
; third insulating film). Then, all of the B-doped polycrystalline silicon film remaining in the portions other than the base extraction electrode is transformed into the 5i02 film 22, and the 5i02 film 22 is also formed at the periphery of the opening in the emitter formation region. Furthermore, at a temperature of 800°C, almost no re-diffusion occurs, and this 5i
By forming the 02 film 22, the opening width of the fine emitter formation region can be formed in a self-aligned manner.

FIG. 1 (see fl; next, the exposed Si3N4 film 31 in the emitter formation region is removed to open the base layer 14, and then a polycrystalline silicon film is deposited by CVD in the same manner as in the conventional method. , arsenic (As) is added to the polycrystalline silicon film.
) Ions are implanted to form an As-doped polycrystalline silicon film 23, and this is patterned to form an As-doped polycrystalline silicon film 23 only in the emitter formation region of the opening and the collector contact electrode formation region.
The s-doped polycrystalline silicon film 23 remains and is further heat-treated at a temperature of 850° C. to define the n1 type crystal layer 16. Incidentally, the B-doped polycrystalline silicon film 15' into which the boron ions have been implanted is simultaneously activated by the activation heat treatment of the emitter layer.

Refer to FIG. 1 tg+; Next, the insulating film 2 is
4 is deposited, this is opened, an emitter electrode Fm 19 and a collector contact electrode 17 are formed on the As-doped polycrystalline silicon film 23, and a base electrode 18 is formed on the base extraction electrode 15 to complete the process. .

The above is the manufacturing method according to the present invention. According to such a manufacturing method, re-diffusion from the B-doped polycrystalline silicon film 15' (second polycrystalline silicon film of different conductivity type) containing impurities at a high concentration can be prevented, and the etch bank method It is suitable for microfabrication because it is flattened by the doped silicon film, and the base layer can be formed thinly by controlling the thickness of the doped silicon film.
Moreover, it can be formed at a high concentration and its resistance can be lowered. Therefore, this manufacturing method can improve frequency characteristics and operate at high speed.

[Effects of the Invention] As is clear from the description of the embodiments above, according to the manufacturing method of the present invention, the base resistance of the base lead-out electrode type semiconductor device can be lowered, the frequency characteristics can be improved, and the device can operate at high speed. This will greatly help improve its performance.

[Brief explanation of the drawing]

1(a) to fg+ are cross-sectional views in the order of steps of the manufacturing method according to the present invention; FIG. 2 is a cross-sectional view of a normal bipolar semiconductor device; FIG. 3 is a cross-sectional view of a base lead-out electrode type semiconductor device; Figure (a
) to (e) are step-by-step sectional views of the conventional manufacturing method, and Fig. 5f
at, fb) are diagrams showing conventional problems. In the figure, 11 is a p-type silicon substrate, 12 is an n+ type buried layer, 13 is an n-type collector layer, 14 is a p-type base layer, and 15 is a base extraction electrode (first different conductivity type) made of a doped polycrystalline silicon film. 15 is a base extraction electrode made of B-doped polycrystalline silicon film (second polycrystalline silicon film of different conductivity type), 16 is an n+ type emitter layer, 17 is a collector contact mA, 18 is a base electrode , 19 is an emitter electrode, 21 is a 5i02 film (first insulating film), 22 is a 5i02 film (third insulating film), 23 is an As-doped polycrystalline silicon film, 24 is an insulating film, and 31 is a Si3N4 film (first insulating film). 2) is shown. 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 1st edition of the 4th edition. Figure 1 (Jt?l) Eu. P・I 4 wide・−ra +17 lower 421! 11 komam 2nd
Figurebe°-Suwo I±4. Words C corner by fu・-fuhana sate /
1~Figure 3

Claims (1)

[Claims] A first insulating film is formed on a semiconductor substrate of one conductivity type;
selectively removing an insulating film to open a base layer formation region; then, growing a silicon film of a different conductivity type on the entire surface including the base layer formation region; forming a base layer made of a single crystal silicon film, and forming a first polycrystalline silicon film of a different conductivity type on the first insulating film; then, selectively forming a second polycrystalline silicon film on the base layer; a second polycrystalline silicon film of different conductivity type is laminated on the second insulating film and the first polycrystalline silicon film of different conductivity type, and crystalline silicon film and second
forming a base extraction electrode film consisting of a polycrystalline silicon film of a different conductivity type, and then opening the second polycrystalline silicon film of a different conductivity type on the second insulating film, and covering the entire surface including the opening. forming a third insulating film, and further opening a window in the second insulating film to open an emitter layer forming region; 1. A method of manufacturing a bipolar semiconductor device, comprising the step of forming an emitter layer of one conductivity type.