JPH021936A - Manufacture of bipolar semiconductor device - Google Patents

Manufacture of bipolar semiconductor device

Info

Publication number
JPH021936A
JPH021936A JP14415888A JP14415888A JPH021936A JP H021936 A JPH021936 A JP H021936A JP 14415888 A JP14415888 A JP 14415888A JP 14415888 A JP14415888 A JP 14415888A JP H021936 A JPH021936 A JP H021936A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
film
form
electrode
layer
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14415888A
Inventor
Satoru Fukano
Kunihiro Suzuki
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To form shallowly a base layer without generating a rediffused layer and to reduce the resistance of a base extraction electrode by a method wherein, after a masking material is removed to form a second insulating film on the whole surface, an opening is selectively formed in the second insulating film to form a one conductivity type emitter layer in the base layer.
CONSTITUTION: An SiO2 film (a second insulating film) 22 is adhered on an upper surface by a CVD method. At this time, a remaining SiO2 film 22' is comprised in the film 22. Then, the film 22 is opened, a poly Si film is adhered by a CVD method, arsenic (As) ions are implanted in the poly Si film to form an As-doped poly Si film 23, this film 23 is patterned to make the film 23 remain only at an emitter formation region and collector contact electrode formation region, which are located in opening parts, and moreover, a heat treatment is performed at a temperature of 850°C to demarcate an n+ emitter layer 16. Then, an insulating film 24 is adhered by a CVD method, this film 24 is opened to form an emitter electrode 19 and a collector contact electrode 17 on the film 23 and a base electrode 18 is formed on a base extraction electrode 15 to complete a bipolar semiconductor device.
COPYRIGHT: (C)1990,JPO&Japio
JP14415888A 1988-06-10 1988-06-10 Manufacture of bipolar semiconductor device Pending JPH021936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14415888A JPH021936A (en) 1988-06-10 1988-06-10 Manufacture of bipolar semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14415888A JPH021936A (en) 1988-06-10 1988-06-10 Manufacture of bipolar semiconductor device

Publications (1)

Publication Number Publication Date
JPH021936A true true JPH021936A (en) 1990-01-08

Family

ID=15355550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14415888A Pending JPH021936A (en) 1988-06-10 1988-06-10 Manufacture of bipolar semiconductor device

Country Status (1)

Country Link
JP (1) JPH021936A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5286996A (en) * 1991-12-31 1994-02-15 Purdue Research Foundation Triple self-aligned bipolar junction transistor
US5721147A (en) * 1995-09-29 1998-02-24 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors
US5814538A (en) * 1996-03-19 1998-09-29 Samsung Electronics Co., Ltd. Methods of forming BiCMOS devices having dual-layer emitter electrodes and thin-film transistors therein
US5994196A (en) * 1997-04-01 1999-11-30 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques
US6080631A (en) * 1997-05-23 2000-06-27 Nec Corporation Method for manufacturing self-alignment type bipolar transistor having epitaxial base layer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5286996A (en) * 1991-12-31 1994-02-15 Purdue Research Foundation Triple self-aligned bipolar junction transistor
US5382828A (en) * 1991-12-31 1995-01-17 Purdue Research Foundation Triple self-aligned bipolar junction transistor
US5434092A (en) * 1991-12-31 1995-07-18 Purdue Research Foundation Method for fabricating a triple self-aligned bipolar junction transistor
US5721147A (en) * 1995-09-29 1998-02-24 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors
US5814538A (en) * 1996-03-19 1998-09-29 Samsung Electronics Co., Ltd. Methods of forming BiCMOS devices having dual-layer emitter electrodes and thin-film transistors therein
US5994196A (en) * 1997-04-01 1999-11-30 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques
US6080631A (en) * 1997-05-23 2000-06-27 Nec Corporation Method for manufacturing self-alignment type bipolar transistor having epitaxial base layer

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