JPS60213049A - Package for semiconductor integrated circuit - Google Patents

Package for semiconductor integrated circuit

Info

Publication number
JPS60213049A
JPS60213049A JP6943984A JP6943984A JPS60213049A JP S60213049 A JPS60213049 A JP S60213049A JP 6943984 A JP6943984 A JP 6943984A JP 6943984 A JP6943984 A JP 6943984A JP S60213049 A JPS60213049 A JP S60213049A
Authority
JP
Japan
Prior art keywords
chip
resin
eprom
molding resin
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6943984A
Other languages
Japanese (ja)
Inventor
Kenji Noguchi
健二 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6943984A priority Critical patent/JPS60213049A/en
Publication of JPS60213049A publication Critical patent/JPS60213049A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/18Circuits for erasing optically

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To prevent an effect on a chip, and to improve the memory holding characteristics of the chip by dividing a molding resin for an ultraviolet erasing type EPROM resin mold package into two upper and lower sections with hollow inside. CONSTITUTION:With the ultraviolet erasing type EPROM resin mold package, a molding resin is divided into two upper and lower sections, and changed into a lower molding resin 11a, to which a lead frame 9 section is held, and an upper molding resin 11b, a hollow inside thereof coveres an EPROM chip 3 mounted onto the lead frame 9, bonding wires 4 for the chip, etc. without being directly brought into contact with these chip, bonding wires, etc. Since the upper molding resin 11b is not brought directly into contact with the EPROM chip 3, the infiltration of a contaminant having an effect on the memory holding characteristics of an EPROM can be prevented by resin components.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体集積回路パンケージに関し、特に紫外
線消去型EFROM樹脂モールドパッケージに係るもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit package, and more particularly to an ultraviolet erasable EFROM resin mold package.

〔従来技術〕[Prior art]

一般的な紫外線消去型EPROMチップは、書き込まれ
たメモリ情報を紫外線により消去できるようにするため
に、紫外線透過窓付きのパンケージに収納されており、
このパッケージの場合、紫外線透過窓付きであるという
特殊性のために、通常。
Typical UV-erasable EPROM chips are housed in a pan cage with a UV-transparent window so that written memory information can be erased using UV light.
For this package, usually due to the special feature of having a UV-transparent window.

セラミックパッケージが用いられ、EPROMチップと
紫外線透過窓付きの蓋との間が中空になっている。この
一般的な紫外線消去型EF ROMパンケージの各側倒
による概要構成を第1図囚、 (B) 、 (C)。
A ceramic package is used, with a hollow space between the EPROM chip and a lid with a UV-transparent window. Figures 1 (B) and (C) show the general configuration of this general ultraviolet-erasable EF ROM panpackage.

0)に示す。すなわち、これらの第1図体)〜■)にお
いて、符号1はリードビン2を有するセラミック基板、
3はこのセラミック基板1の凹部面にマウントしたEP
ROMチップ、4はそのボンディングワイヤ、5は前記
セラミック基板1上の接着ガラス、6aは紫外線透過窓
8付きの蓋Tを配し7たセラミック蓋、6bは紫外線透
過窓8付きのセラミック蓋である。
0). That is, in these first figures) to ■), reference numeral 1 indicates a ceramic substrate having a lead bin 2;
3 is an EP mounted on the concave surface of this ceramic substrate 1.
ROM chip, 4 its bonding wire, 5 adhesive glass on the ceramic substrate 1, 6a a ceramic lid with a lid T provided with an ultraviolet ray transmitting window 8, and 6b a ceramic lid with an ultraviolet ray transmitting window 8. .

またこ\数年来、注目されつ\ある従来例として、紫外
線消去型EFROM樹脂モールドパッケージがある。こ
\でもその概要構成を第2図に示す。
Another conventional example that has been attracting attention over the past few years is the ultraviolet erasable EFROM resin mold package. Figure 2 shows its general configuration.

この第2図従来例構成の場合、 EPROMチップ3゜
そのボンティングワイヤ4およびこれらをマウントする
リードフレーム9の全てがモールド樹脂10に封じ込め
られ、EPROMチップのメモリセルおよび周辺回路の
側面に接触しており、この従来例構成では、紫外線透過
窓が形成されておらず、書き込まれたメモリ情報を消去
できないために、メモリ情報の書き込みを1回限りのみ
と想定している。すなわち、この従来構成は、紫外線透
過窓付きパンケージのコストが高いために、その代用と
して注目されているもので、メモリ情報の書き込みが1
回のみに限られる用途においては、価格的に利点を有し
ている。
In the case of the conventional configuration shown in FIG. 2, the EPROM chip 3, its bonding wires 4, and the lead frame 9 that mounts them are all sealed in a molding resin 10, and are in contact with the side surfaces of the memory cells and peripheral circuits of the EPROM chip. In this conventional configuration, since no ultraviolet light transmission window is formed and the written memory information cannot be erased, it is assumed that the memory information can be written only once. In other words, this conventional configuration is attracting attention as a substitute for the high cost of pancakes with ultraviolet-transmitting windows, and it is possible to write memory information only once.
For applications that are limited to once use, it has a cost advantage.

こ\でこの種の紫外線消去型E FROMでのメモリ保
持特性、耐湿性などの長期信頼特性は、EFROMチッ
プ表面のパンシベーション膜特性と、同膜上に接するモ
ールド樹脂の材質、および成形時の同腹に対するモール
ド樹脂の圧迫の度合などとによって影響されることが知
られており、さきのEFROMチップが中空内部に納め
られた紫外線透過窓付きパッケージの場合には、特に問
題とはならなかったメモリ保持特性、および書き込み特
性が、この従来例による紫外線消去型EPROM樹脂モ
ールドパッケージの場合に悪化するという欠点を生ずる
ものであった。
The long-term reliability characteristics of this type of ultraviolet-erasable E FROM, such as memory retention characteristics and moisture resistance, depend on the characteristics of the pansivation film on the surface of the EFROM chip, the material of the molding resin in contact with the film, and the molding process. It is known that this is affected by factors such as the degree of pressure of the molding resin on the litter, but this did not pose a particular problem when the EFROM chip was housed in a hollow package with an ultraviolet-transparent window. This conventional ultraviolet erasable EPROM resin mold package has a drawback in that the retention characteristics and writing characteristics are deteriorated.

〔発明の概要〕[Summary of the invention]

この発明は従来のこのような欠点に鑑み、紫外線消去型
EPROM樹脂モールドパンケージにおいて、EPRO
Mチンプのメモリセルおよび周辺回路の側面が中空内部
に配されて、このEFROMチップにモールド樹脂など
を直接々触させることのないようにさせたものである。
In view of the above-mentioned drawbacks of the conventional technology, the present invention provides an ultraviolet-erasable EPROM resin mold pancage.
The side surfaces of the memory cells and peripheral circuits of the Mchimp are arranged in a hollow interior to prevent the EFROM chip from coming into direct contact with molding resin or the like.

〔発明の実施例〕[Embodiments of the invention]

以下この発明に係る紫外線消去型EFROM樹脂モール
ドパッケージの一実施例につき、第3図を参照して詳細
に説明する。
Hereinafter, one embodiment of the ultraviolet erasable EFROM resin mold package according to the present invention will be described in detail with reference to FIG.

この第3図実施例は前記第2図従来例に幻応して表わし
たもので、各図中、同一符号は同一または相当部分を示
しており、この実施例装置では前記EpnoMチップ3
.そのポンディングワイヤ4およびこれらをマウントす
るり−・ドフレーム9の全てをモールド樹脂(てより封
じ込める場合、このモールド樹脂を上下に2分割して、
リードフレーム90部分を保持させる下部モールド樹脂
11aと、リードフレーム9上にマウントされるE P
ROMチンプ3.そのポンディングワイヤ4などに直接
々触せずに、これらを中空内部で覆う上部モールド樹脂
11bとにしたものである。
This embodiment in FIG. 3 is shown in response to the conventional example in FIG. 2, and the same reference numerals indicate the same or corresponding parts in each figure.
.. The bonding wire 4 and the board frame 9 on which they are mounted are all molded with resin.
A lower mold resin 11a that holds the lead frame 90 portion and an E P mounted on the lead frame 9.
ROM Chimp 3. The upper mold resin 11b covers the bonding wire 4 and the like in a hollow interior without directly touching them.

従ってこの実施例構成の場合には、上部モールド樹脂1
1bがEPROMチップ3に直接々触していないために
、EPROMのメモリ保持特性に影響を及はす汚染物の
浸透を樹脂成分によって阻止できるのであり、また上部
モールド樹脂11bにょるEPROMチップ3への圧迫
が解消されることがら、従来のEPROMテンプ接触モ
ールド[脂バンクージにおいて、不良原因のひとつにな
っていたところの、チップ表面上の異物、パンシベーシ
ョン膜のピンホール、欠陥に伴なうチップ表面上の凹凸
などによるメモリセルおよび周辺回路の押しつぶし不良
とか、あるいはパンシベーション展の欠陥を通してのモ
ールド樹脂の入り込みによる汚染物不良などをそれぞれ
に防止でき、さらにはポンディングワイヤについてもモ
ールド樹脂による圧迫を受けないために、その断線防止
をもなし得るのである。
Therefore, in the case of this embodiment configuration, the upper mold resin 1
1b does not directly touch the EPROM chip 3, the resin component can prevent contaminants from penetrating into the EPROM chip 3 that would affect the memory retention characteristics of the EPROM. This eliminates the pressure caused by foreign matter on the chip surface, pinholes in the pansivation film, and defects in the chip, which were one of the causes of defects in the conventional EPROM template contact mold [fat bankage]. It is possible to prevent defects such as crushing of memory cells and peripheral circuits due to unevenness on the surface, contaminants caused by mold resin entering through defects due to pansivation, etc. Furthermore, it is possible to prevent bonding wires from being compressed by mold resin. Therefore, it is possible to prevent wire breakage.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようKこの発明によれば、紫外線消去型l
PROM樹脂モールドパッケージにおいて、EFROM
チップのメモリセルおよび周辺回路の側面が中空内部に
配されるようにモールド樹脂を上下に2分割させ、この
モールド樹脂がEPROMチア7’に直接々触しないよ
うKしたので、gPROMチップに灼する影響を確実に
阻止でき、これによってEFROMチップのメモリ保持
特性、および書き込み特性などをそれぞれに向上し得る
などの特長を有するものである。
As described in detail above, according to this invention, the ultraviolet erasing type l
In PROM resin mold package, EFROM
The mold resin was divided into upper and lower halves so that the side surfaces of the chip's memory cells and peripheral circuits were arranged inside the hollow, and the mold resin was prevented from directly touching the EPROM cheer 7', so that the gPROM chip could be burned. This has the advantage that the influence can be reliably prevented, thereby improving the memory retention characteristics and write characteristics of the EFROM chip.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(至)および(B) 、 (C)および0)は一
般的な紫外面図、第2図は従来例による紫外線消去型E
PROM樹脂モールドパッケージの概黴構成を示す断面
図、第3図はこの発明の一実施例による同上紫外線消去
型EFROM樹脂モールドパッケージの概要構成を示す
断面図である。 3・・・・EPROMチップ、4拳・0・ボンディング
ワイヤ、9拳11−1ノードフレーム、11a。 11b・・・・下部、上部モールド樹脂。 代 理 人 人 岩 坩° 雄 @ 1 図
Figures 1 (to), (B), (C) and 0) are general ultraviolet surface diagrams, and Figure 2 is a conventional ultraviolet erasing type E.
FIG. 3 is a cross-sectional view showing the general structure of a PROM resin mold package, and FIG. 3 is a cross-sectional view showing the general structure of an ultraviolet erasable EFROM resin mold package according to an embodiment of the present invention. 3...EPROM chip, 4 fists 0 bonding wire, 9 fists 11-1 node frame, 11a. 11b...Lower and upper mold resin. Representative Person Person Iwa 坩° Male @ 1 Figure

Claims (1)

【特許請求の範囲】[Claims] 紫外線消去型gFROM樹脂モールドパッケージにおい
て、EPROMチップのメモリセルおよび周辺回路の側
面が中空内部に配されるようにモールド樹脂を上下に2
分割させ、このモールド樹脂がEPROMチップに直接
々触しないようにしたことを特徴とする半導体集積回路
パンケージ。
In an ultraviolet-erasable gFROM resin mold package, the mold resin is placed vertically two times so that the sides of the memory cells and peripheral circuits of the EPROM chip are placed inside the hollow.
A semiconductor integrated circuit pancase characterized in that the mold resin is divided to prevent direct contact with an EPROM chip.
JP6943984A 1984-04-06 1984-04-06 Package for semiconductor integrated circuit Pending JPS60213049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6943984A JPS60213049A (en) 1984-04-06 1984-04-06 Package for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6943984A JPS60213049A (en) 1984-04-06 1984-04-06 Package for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS60213049A true JPS60213049A (en) 1985-10-25

Family

ID=13402665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6943984A Pending JPS60213049A (en) 1984-04-06 1984-04-06 Package for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS60213049A (en)

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