JPS60169154A - Package device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent adverse effects on a chip even though a resin sealing form is provided, by covering the upper surface side of a memory type integrated circuit chip part by an insulating cover with a space being provided, and sealing the chip part by a resin with the space being maintained. CONSTITUTION:An ultraviolet-ray erasing type EPROM chip 1 is die-bonded to a lead frame 2 and also wire-bonded by metal thin wire 3. Many lead pins 4 are arranged on the frame 2. The upper surface side is covered by an insulating cover 11 with a space being provided. The back surface side of the chip is contacted with the lower part of the frame 2 so as to close the lower side of the chip 1. An insulating stop plate, which stops the intrusion of an injected resin into the space part, is provided. The entire configuration of this state is sealed by the molding of a resin sealing body 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit package device in which a memory type integrated circuit chip portion is sealed by synthetic resin molding.

[Prior art]

Conventional ultraviolet erasing type]! ! FROM sealing, ultraviolet erase type F! The FROM chip is housed in a package with an ultraviolet-transparent window in order to erase written memory information. This package is.

They are usually packaged in ceramic because they have a window that transmits UV rays, and there is a space between the chip and the window. In applications where memory information is written only once and the written information is not erased, inexpensive synthetic resin molded packages have come to be used because ultraviolet light transmission windows are not required.

A conventional semiconductor integrated circuit package device of an ultraviolet erasable IPROM using resin sealing is shown in FIGS. 1 and 2 as a plan view and a partial front view. (1) is an ultraviolet-erasable PROM chip (hereinafter referred to as the "chip"), which is firmly bonded to a lead frame (2) and wire-bonded with a thin metal wire (3). ) (4) is a large number of lead bins taken out from the lead frame (2), (5) is a chip (1)
It is a resin-sealed body that is sealed and molded.

The conventional resin-sealed packaging device shown in Figures 1 and 2 of this Koshirae is lower in price than a ceramic package with a transparent window, and is often used in applications where memory information can be written only once. It has the advantage of being easy to mold and inexpensive.

On the other hand, the memory retention characteristics of UV erasable BFROM.

The long-term reliability of moisture-resistant types, etc. depends on the passivation film on the surface of the chip (1), the material of the resin sealant (5) that contacts the passivation film, and the sealant injected into the mold during resin molding. This is influenced by the degree to which the stopper resin presses against the passivation film on the chip (1).

If the above-mentioned conventional package with an ultraviolet-transmitting window has a vacant space on the chip, the memory characteristics and write characteristics of ICFROM, which did not pose a problem in actual use, are In packaging equipment using sealed bodies,
The injected resin directly contacted and compressed the surface of the chip (1), causing the following problems. That is, the surface of the chip (1) is uneven due to adhesion of foreign matter, pinholes or defects in the passivation film, etc., but the pressure during resin injection molding may cause memory hills on the chip (1), crushing of the circuit, or the like.

Defects in the passivation film caused contamination due to infiltration of the injected resin, resulting in a decline in quality and the occurrence of defective products. Although it is an inexpensive resin-sealed package,
The thin metal wire (3) was deformed or separated due to the resin.

[Summary of the invention]

This invention eliminates the drawbacks of the conventional device described above, by covering the surface side of the memory type integrated circuit chip part with an insulating enclosure with a space left, and sealing the chip part with resin while maintaining this space. It is an object of the present invention to provide a semiconductor integrated circuit package device that eliminates adverse effects on memory storage retention and thin metal wires.

[Embodiments of the invention]

FIG. 3 is a partially sectional front view showing an integrated circuit package device according to an embodiment of the present invention;
) is the same as the conventional device described above. aυ is the chip (
It is an insulating enclosure that covers the surface side of part 11 with a space left in it, and is made of a synthetic resin material that is heat resistant and has relatively high mechanical strength. :l@ corresponds to the insulating enclosure αD, and is an insulating closing plate that is applied to the lower part of the lead frame (2) and closes the lower side of the chip (1) part to prevent the injected resin from entering the space. Made of the same material as 0υ. This entire state is sealed by molding a resin sealing body a3.

In the device of the above embodiment, a space is formed on the surface side of the chip (1) portion from the resin sealing body @ by the insulating enclosure OD,
No direct contact. This eliminates pressure on the surface of the chip (1) by the resin sealing body (2), resulting in a memory hill and
No more squeezing of the circuit due to contaminants in the penetrated resin components. In the above embodiment, ultraviolet erasable FiF
Although the case of ROM is shown, it does not need to be of the ultraviolet erasable type and can be applied to resin sealing of memory type integrated circuits.

〔Effect of the invention〕

As described above, according to the present invention, the surface side of the memory type integrated circuit chip is covered with an insulating enclosure to form a space, and this space is maintained and the chip portion is sealed by molding a resin sealant. , the resin does not come into direct contact with the chip surface, and even if it is a resin-sealed type, it will prevent any adverse effects on the chip, there will be no deterioration in memory retention characteristics, and it will be an inexpensive resin-sealed body. Also, the effect on the thin metal wire is eliminated.

[Brief explanation of the drawing]

1 and 2 are a plan view and a partially sectional front view of a conventional semiconductor integrated circuit package device, and FIG. 3 is a partially sectional plan view of a semiconductor integrated circuit package device according to an embodiment of the present invention. FIG. DESCRIPTION OF SYMBOLS 1...Ultraviolet erasable EFROM chip, 2...Lead frame, 11...Insulating enclosure, 12...Insulating cover plate, 13...Resin sealing body Note that the same reference numerals in the figure refer to the same - or a corresponding portion. Agent Masuo Oiwa Paragraph 21 Figure 3 To the Commissioner of the Japan Patent Office 1 Indication of the case Japanese Patent Application No. 59-26444 2 Title of the invention Semiconductor integrated circuit package device 3 To the person making the amendment Representative Hitoshi Katayama Part 5 , "Detailed Description of the Invention" column of the specification to be amended. 6. Details of correction (1) Correct "Memory Hill" in the 20th line of page 3 of the specification by "Memory Cell" K. (2) In the 12th line of page 5 of the specification, "in terms of characteristics" is amended to "in terms of durability."that's all

Claims (2)

[Claims] (1) An insulating enclosure that covers the surface side of the memory integrated circuit chip fixed on the die pad with a space left in it, and a molded resin seal that seals the chip while leaving a space inside the insulating enclosure. A semiconductor integrated circuit packaging device with a body. (2) The memory type integrated circuit chip is an ultraviolet erasable gpROM.
A semiconductor integrated circuit package device according to claim 1, which comprises a chip.