JPS59228748A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS59228748A JPS59228748A JP58103297A JP10329783A JPS59228748A JP S59228748 A JPS59228748 A JP S59228748A JP 58103297 A JP58103297 A JP 58103297A JP 10329783 A JP10329783 A JP 10329783A JP S59228748 A JPS59228748 A JP S59228748A
- Authority
- JP
- Japan
- Prior art keywords
- package
- integrated circuit
- window
- ultraviolet
- ultraviolet ray
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
し発明の技術分野1
本発明は、紫外線消去型リード・オンリー・メモリ(U
V−EPROM)に他の集積回路素子を電気的に接続し
一体化して構成される混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field 1 of the Invention The present invention relates to ultraviolet erasable read only memory (U
The present invention relates to a hybrid integrated circuit device configured by electrically connecting and integrating a V-EPROM with other integrated circuit elements.
[発明の技術的背景とその問題点コ
UV−EPROMは、外部から集積回路チップに紫外線
を照射することによりメモリセルに記憶されている情報
を消去することができ、再び新たな情報を記憶させるこ
とができるように構成されている。[Technical background of the invention and its problems] With UV-EPROM, information stored in memory cells can be erased by irradiating ultraviolet light onto the integrated circuit chip from the outside, and new information can be stored again. It is configured so that it can be done.
第1図は、このようなUV−EPROMIを示すもので
、このUV−EPR,OMlでは集積回路チップ2を収
容したパッケージ3の上面には紫外線透過窓4が設けら
れて、この透過窓4を介して、パッケージ3内部の集積
回路デツプ2に紫外線を照射し得るようになってる。紫
外線透過窓4は石英ガラスやサファイア板、ま7.−は
透明アルミプ等から作られており、常時はこの紫外線透
過窓4に遮光シール(図示せず)が貼着されCメモリセ
ルに記憶された情報を保護するJ:うにされ°Cいる。FIG. 1 shows such a UV-EPROMI. In this UV-EPR, OMl, an ultraviolet light transmitting window 4 is provided on the top surface of a package 3 that houses an integrated circuit chip 2. Through this, the integrated circuit depth 2 inside the package 3 can be irradiated with ultraviolet light. The ultraviolet transmitting window 4 is made of quartz glass, sapphire plate, or 7. - is made of transparent aluminum or the like, and a light-shielding seal (not shown) is always attached to this ultraviolet-transmitting window 4 to protect the information stored in the memory cell.
そしてこの情報の消去は、遮光シールを剥がして紫外線
透過窓4から強い紫外線を照射することにより行なわれ
る。This information is erased by peeling off the light-shielding seal and irradiating strong ultraviolet light from the ultraviolet-transmitting window 4.
ところで、近時電子機器の小型化の要望がら混成集積回
路装置の開発が進んでいるが、特にマイクロコンピユー
タ−の分野で幅広い用途が考えられるLJV−EPRO
Mを用いた混成集積回路装置は開発されているものが少
く、応用範囲の広い混成集積回路装置の開発が期待され
ている。By the way, the recent demand for miniaturization of electronic devices has led to the development of hybrid integrated circuit devices, and LJV-EPRO, which has a wide range of applications in the field of microcomputers in particular, has been developed.
Few hybrid integrated circuit devices using M have been developed, and the development of hybrid integrated circuit devices with a wide range of applications is expected.
[発明の目的]
本発明はかかる事情に対処してなされたもので、U V
−E P ROMと他の集積回路素子を混成化し、遮
光シールを用いることなく U V −[E F RO
Mに記憶されている情報の保存をづることができ、しか
もコンパクトで応用範囲の広い混成集積回路装、置の提
供を目的とづる。[Object of the invention] The present invention has been made in response to such circumstances, and
- By hybridizing E P ROM and other integrated circuit elements, UV - [E F RO
The purpose of this invention is to provide a hybrid integrated circuit device which is compact and has a wide range of applications, and which can store information stored in M.
[発明の概要コ
すなわち本発明は、パンケージに紫外線透過窓を備えた
紫外線消去型リード・オンリー・メモリに他の集積回路
素子を電気的に接続し一体化してなる混成集積回路装置
において、前記パッケージの前記紫外vA透過窓側にソ
クツ1〜を設【)、このソケットに前記紫外線透過窓を
覆って前記他の集積回路素子を実装してなることを特徴
としている。[Summary of the Invention] In other words, the present invention provides a hybrid integrated circuit device comprising an ultraviolet erasable read-only memory having an ultraviolet transmitting window in a pancase and another integrated circuit element electrically connected to the package. A socket 1 is provided on the side of the ultraviolet vA transmitting window [), and the other integrated circuit element is mounted in this socket to cover the ultraviolet transmitting window.
[発明の実施例1
以下、本発明の詳細を図面に示す一実施例につい−C説
明する。[Embodiment 1 of the Invention] Hereinafter, details of the present invention will be described with reference to an embodiment shown in the drawings.
第2図は本発明の一実施例の混成集積回路装置を示すも
のであり、この実施例ひはデュアルインライン型(以下
、DIP型という)パッケージの[JV−EPROMの
上部にD T P型のM OS −RAMが搭載され、
さらにU V −E P ROMとMOS−RAMとが
ソケットを介しC電気的に接続されて混成集積回路装置
を4M成している。FIG. 2 shows a hybrid integrated circuit device according to an embodiment of the present invention, and this embodiment shows a dual in-line type (hereinafter referred to as DIP type) package [DTP type on top of JV-EPROM]. Equipped with MOS-RAM,
Further, the UV-EP ROM and the MOS-RAM are electrically connected via a socket to form a 4M hybrid integrated circuit device.
図において符号1で示したしのはUV−EPROMであ
り、集積回路チップ2を収容するパッケージ3の上面に
は紫外線透過窓4が形成され−Cいる。In the figure, the reference numeral 1 indicates a UV-EPROM, and an ultraviolet light transmitting window 4 is formed on the upper surface of a package 3 that accommodates an integrated circuit chip 2.
パッケージ3の側面部両側には端子ビン5が少数本列設
されており、それぞれの端子ビン5はパッケージ3内部
の集積回路チップ2に電気的に接続されている。A small number of terminal bins 5 are arranged in rows on both sides of the package 3, and each terminal bin 5 is electrically connected to the integrated circuit chip 2 inside the package 3.
パッケージ3の上面の紫外線透過窓4の両側には、パッ
ケージ3内部の集積回路チップ2と電気的に接続された
一対のソケツ]−6,6がそれぞれ紫外線透過窓4を挾
/υで対向して配設されている。On both sides of the ultraviolet transmitting window 4 on the top surface of the package 3, a pair of sockets ]-6, 6, which are electrically connected to the integrated circuit chip 2 inside the package 3, respectively face the ultraviolet transmitting window 4 at a distance of /υ. It is arranged as follows.
パッケージ3の紫外線透過窓4の上方にはMOS−RA
M7が配設されCおり、このM OS −ROM7は、
パッケージ8の側面部両側に列設される端子ビン9をソ
ケット6に挿入することにより固定されている。Above the ultraviolet transmitting window 4 of the package 3 is a MOS-RA.
M7 is provided, and this MOS-ROM7 is
The package 8 is fixed by inserting terminal pins 9 arranged in rows on both sides of the package 8 into the socket 6.
そしてパッケージ8の下面とパッケージ3の上面との間
には、両パッケージ間の隙間から紫外線透過窓4へ外部
からの光が侵入しないように遮光バッキング10が介装
され−(いる。A light-shielding backing 10 is interposed between the lower surface of the package 8 and the upper surface of the package 3 to prevent light from entering the ultraviolet light transmitting window 4 from the outside through the gap between the two packages.
以上のように構成された混成集積回路装置において、U
V−EPROMIに記憶された情報の消去は、MOS−
RAM7を取り去って紫外線透過窓4から強い紫外線を
照射ダることにより容易に行なうことができる。In the hybrid integrated circuit device configured as described above, U
To erase information stored in V-EPROMI, use MOS-
This can be easily done by removing the RAM 7 and irradiating strong ultraviolet rays from the ultraviolet transmitting window 4.
また、MOS−RAM7の端子ビン9はパッケージ8の
内部の集積回路チップ11に電気的に接続されているの
で、端子ビン9をソケット6に挿入すれば、MOS−R
AM7とU V−E I) ROMlとを電気的に容易
に接続することができる。Furthermore, since the terminal pin 9 of the MOS-RAM 7 is electrically connected to the integrated circuit chip 11 inside the package 8, if the terminal pin 9 is inserted into the socket 6, the MOS-R
AM7 and UV-E I) ROM1 can be electrically connected easily.
143図ハ前述L タU V−E P ROM 1 、
!= M O5−RAM7との電気的接続を示す回路構
成の一例を示したもので、この例ではU V −E P
ROM 1のパッケージ3内に、ゲートIC(NOT
グー1へ)12があらかじめ実装されており、このグー
1〜IC12をMOS−RAM7のチップイネーブル端
子CEIの前に電気的に介挿させ、チップセレクタ信号
CE+が“O″レベルときのみU V −lEPROM
1のチップセレクタCE+が選択されるので、UV−E
PROM1、fvlO8−RAM7相互の切り換えが可
能となる。したがってUV−FPROMlに情報を記憶
させる時に、U V −L: l)ROM1にのみ情報
を入力することができるのC゛、MOS−RAM7を必
要に応じてはJ“しておくことかできる。FIG. 143
! = An example of the circuit configuration showing the electrical connection with M O5-RAM7, in this example
A gate IC (NOT
Goo 1 to IC12 are mounted in advance, and these Goo 1 to IC12 are electrically inserted in front of the chip enable terminal CEI of MOS-RAM 7, and the UV − is activated only when the chip selector signal CE+ is at “O” level. lEPROM
Since chip selector CE+ of 1 is selected, UV-E
It becomes possible to switch between PROM1 and fvlO8-RAM7. Therefore, when storing information in the UV-FPROM 1, information can be input only to the UV-L: ROM 1, and the MOS-RAM 7 can be set to ``J'' if necessary.
なお図において、符号Vは電源ライン、符号へはアドレ
ス指定ライン、符号I10はデータ入出カライン、符号
WEは書き込み指令ライン、符号PGMはプログラム指
令端子、符号O[は出力指令ライン、符号R/Wは古き
込み/読み出し指令端子C′ある。In the figure, symbol V is a power supply line, symbol is an address designation line, symbol I10 is a data input/output line, symbol WE is a write command line, symbol PGM is a program command terminal, symbol O[ is an output command line, symbol R/W is the old loading/reading command terminal C'.
[発明の効果]
以上)ボべたように本発明の混成集(1を回路装置によ
れば、紫外線透過窓に遮光シールを貼希しCおかなく【
もIJV−EPROMに記憶された情報の保存がC′き
るコンパクトで応用範囲の広い混成集積回路装置を得る
ことがでさる。[Effects of the Invention] As mentioned above, according to the circuit device of the present invention (1), a light-shielding sticker is pasted on the ultraviolet-transmitting window and C is removed.
It is also possible to obtain a compact hybrid integrated circuit device which can store information stored in an IJV-EPROM and has a wide range of applications.
第1図は従来の混成集積回路装置を承り斜視図、第2図
は本発明の)fコ成集積回路装置の一実施例を示す横断
面図、第3図はその電気的接続例を説明するための回路
図である。
1・・・・・・・・・・・・UV−EPrで0M2.1
1・・・集積回路チップ
3.8・・・・・・パッケージ
4・・・・・・・・・・・・紫外線透過窓5.9・・・
・・・端子ビン
6・・・・・・・・・・・・ソケット
7・・・・・・・・・・・・M OS −RA Mlo
・・・・・・・・・・・・遮光バッキング12・・・・
・・・・・・・・ゲートIC代理人弁理士 須 山
佐 −
第1図
第2図 。Fig. 1 is a perspective view of a conventional hybrid integrated circuit device, Fig. 2 is a cross-sectional view showing an embodiment of the f-co integrated circuit device of the present invention, and Fig. 3 explains an example of its electrical connection. FIG. 1・・・・・・・・・・・・0M2.1 with UV-EPr
1...Integrated circuit chip 3.8...Package 4...Ultraviolet transmission window 5.9...
...Terminal bin 6...Socket 7...M OS -RA Mlo
・・・・・・・・・・・・Light blocking backing 12・・・・
...Gate IC Patent Attorney Sasa Suyama - Figure 1 Figure 2.
Claims (2)
リード・オーンリー・メモリに他の集積回路素子を電気
的に接続し一体化してなる混成集積回路装置において、
前記パッケージの前記紫外線透過窓側にソケットを設け
、このソケットに前記紫外線透過窓を覆って前記他の集
積回路素子を実装してなることを特徴とする混成集積回
路装置。(1) In a hybrid integrated circuit device formed by electrically connecting and integrating other integrated circuit elements to an ultraviolet-erasable read-only memory whose package has an ultraviolet-transmitting window,
A hybrid integrated circuit device characterized in that a socket is provided on the side of the ultraviolet ray transmitting window of the package, and the other integrated circuit element is mounted in the socket covering the ultraviolet ray transmitting window.
ージ間に遮光バッキングが介装されている特許請求の範
囲第1項記載の混成集積回路装置。(2) The hybrid integrated circuit device according to claim 1, wherein a light-shielding backing is interposed between the ultraviolet erasable read-only memory and the package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58103297A JPS59228748A (en) | 1983-06-09 | 1983-06-09 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58103297A JPS59228748A (en) | 1983-06-09 | 1983-06-09 | Hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59228748A true JPS59228748A (en) | 1984-12-22 |
Family
ID=14350327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58103297A Pending JPS59228748A (en) | 1983-06-09 | 1983-06-09 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59228748A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0393671A2 (en) * | 1989-04-20 | 1990-10-24 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
EP0393657A2 (en) * | 1989-04-20 | 1990-10-24 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
-
1983
- 1983-06-09 JP JP58103297A patent/JPS59228748A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0393671A2 (en) * | 1989-04-20 | 1990-10-24 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
EP0393657A2 (en) * | 1989-04-20 | 1990-10-24 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
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