JPS60210871A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make the wiring fine, and to reduce migration by a method wherein the titled devices driven by small current and large current are formed, and, in providing these with wiring electrodes, the electrode led out of the small current element is composed of a metallic layer, and the electrode led out of the large current element of a lamination of two metals. CONSTITUTION:Diffused regions 2 and 3 for small current and large current driven elements are provided in the surface layer section of a semiconductor substrate 1, which is then covered over with an SiO2 film 4, and contact holes 5 and 6 for electrode lead-out are bored by corresponding to the regions 2 and 3, respectively. Next, the first metallic layers 7 contacting the regions 2 and 3 are formed in the holes 5 and 6, and the whole surface is coated with an SiO2 film 10. Thereafter, a through-hole 11 is opened by corresponding to the metallic layer 7 in the hole 6, and the second metallic layer 8 is adhered only on the exposed metallic layer 71, which is then protected with a passivation film 9. The current capacitance is increased by thus thickening the electrode for the large current element, and the electrode width is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to an electrode wiring and a method of manufacturing the same.

(Prior Art) At or AL-8i alloy is generally used as the electrode wiring metal of a semiconductor device. This is because At satisfies various conditions as an electrode wiring metal, such as excellent adhesion and ohmic properties to semiconductor materials, low electrical resistance, and easy microfabrication.

By the way, as the degree of integration of semiconductor integrated circuits has improved recently, At N-pole wiring (including electrode wiring made of At-St gold alloy) and patterns have also been miniaturized. As a result of the increase in current density, A
So-called electromigration, in which 1M electrode wiring is short-circuited or disconnected due to movement of metal ions such as t, has become a problem.

In order to prevent this phenomenon, it is necessary to increase the width of the At electrode wiring, but this is a method that runs counter to miniaturization. Also, A
Although there is a method of using an alloy resistant to electromigration such as t-8i-Cu, it has drawbacks such as poor corrosion resistance and wire bonding properties.

Note that these problems are noticeable in bipolar semiconductor integrated circuits with relatively high current density, and are an impediment to miniaturization.

(Objective of the Invention) The present invention has been developed in view of the above points, and its object is to achieve both miniaturization of electrode wiring and electromigration resistance.

(Summary of the Invention) The key point of the present invention is that only the electrode wiring in the portion where a large current flows has a laminated structure of two metal layers.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention. The first embodiment will be explained with reference to this figure.
1, a semiconductor substrate 1 has a diffusion region 2 for a φ current drive element and a diffusion region 3 for a large current drive element in the surface portion of the semiconductor substrate 1. Further, an insulating film 4 such as 5t (h) is provided on the semiconductor substrate 1, and contact holes 5 and 6 for leading out electrodes are provided in this insulating film 4 on the diffusion region 2.3, respectively. .

On such a semiconductor substrate 1, At or ht-s i
The first metal layer 7 made of an alloy is heated at 6000 to 10000X.
By depositing the first metal layer 7 to a thickness of 100 nm and then turning the first metal NjI7t-/4' by a known photoetching technique, the first metal layer 7 is formed into a contact hole 6 as shown in FIG. 1(B). It is left only in the electrode wiring formation part of the large current drive element including the

Next, as shown in FIG. 1C, a second metal layer 8 made of a kt''*tiAt-8t alloy is deposited on the entire surface of the semiconductor substrate 1 to a thickness of 8,000 to 14,000 Å.

Thereafter, a second metal layer 8 is formed using a known photoetching technique.
By performing patterning, this second metal layer s
t-1g1 As shown in FIG. 0, it is left only on the remaining first metal layer 7 and on the electrode wiring forming portion of the small current driving element including the contact hole 5.

At this time, the second metal layer 8 on the first metal layer 7 is
When an overlap structure is formed as shown in FIG. 0, when patterning the second gold [118], the first metal I#! I
7 is not etched, and the coverage of the /4' ossification film is good.

And this second metal FW18? When the turning process is completed, the electrode wiring of the small current drive element is formed using the remaining second metal layer 8. Further, the electrode wiring of the large current driving element is formed with a laminated structure of the remaining first metal layer 7 and the remaining second metal NI8.

Thereafter, as shown in FIG. 1 (2), a mother tsipation film 9 (which protects the semiconductor device) is formed over the entire surface of the substrate by CVD.

FIG. 2 is a diagram showing a second embodiment of the invention. This second embodiment will be explained below.

As shown in FIG. 2(2), a diffusion region 2.3 and an insulating film 4 are formed in the semiconductor substrate 1, as in the first embodiment, and a contact hole 5.3 is formed in the insulating film 4. 6 is open.

After depositing a first metal layer 7 made of At or At-8t alloy to a thickness of 8,000 to 10,000 Å on such a semiconductor substrate 1, the first metal layer 7 is deposited to a thickness of /4 by a known photoetching technique. 'By turning, in this case, as shown in Figure 2, the first metal! +7 is left in the electrode wiring forming portion of the large current driving element including the contact hole 6t- and in the electrode wiring forming portion of the small current driving element including the contact hole 5.

Next, a 5-ins film 10f having a thickness of 4000 to 6000× is formed on the entire surface of the semiconductor substrate 1 by a known CVD method.

As shown in FIG. 2 (03), this 5ins film 10 has a
A through hole 1lt- is formed on the first metal layer 7 (hereinafter, this first metal layer will be particularly designated by reference numeral 71) connected to the buff diffusion region 3.

At this time, the through hole 11 may be formed by one large hole, or may be formed by many small holes.

After that, At or M-8i is applied to the entire surface of the semiconductor substrate 1.
The second metal layer 8 made of alloy is 8000~1ooooX
The second layer is formed to a thickness of
By turning the metal layer 8 of υ, this second
The metal layer 8 is left only in the through hole 11 portion, that is, only on the remaining first metal layer 71, as shown in FIG.

As a result, the electrode wiring of the large current drive element is formed with a laminated structure of the remaining first metal layer 71 and the remaining second metal layer 8. Moreover, the electrode wiring of the small current drive element is formed only by the remaining first metal layer 7 at the stage where the first metal layer 7 is deposited and patterned.

Thereafter, as shown in FIG. 2, a passivation film 9 is formed over the entire surface by CVD.

(Effects of the Invention) As is clear from the above embodiments, in the present invention, the electrode wiring of the large current drive element has a laminated structure of two metal layers. In this way, the electrode wiring of the large current driving element becomes relatively thick, and the current capacity can be increased to about twice the unit line width. Migration can be prevented.

Furthermore, as a result of being able to reduce the width of the electrode wiring, it is possible to achieve miniaturization of the electrode wiring of the large current drive element. Further, since the electrode wiring of the small current driving element is formed in a single layer of one gold N layer, it can be formed in a conventional fine pattern.

Although the present invention can be applied to any semiconductor device, it is particularly suitable for a case where the current density is relatively high, such as a bipolar type semiconductor integrated circuit. Further, it can be effectively applied to a semiconductor device in which a low current region and a large current region coexist, such as a Bi-0MO8 structure.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining a first embodiment of a semiconductor device and method for creating the same according to the present invention, and FIG. 2 is a cross-sectional view for explaining a second embodiment of the present invention. 1... Semiconductor substrate, 2, 3... Diffusion region, 7s71
...First metal layer, 8...Metal layer of #I2. Figure 1 Figure 2

Claims (2)

[Claims] (1) In a semiconductor device in which a small current drive element and a large current drive element are formed, the electrode wiring drawn out from the small current drive element is formed using one metal layer, while the electrode wiring drawn out from the large current drive element is formed using two metal layers. A semiconductor device characterized in that it is formed with a fitffit structure of layers. (2) A step of forming a metal layer only in the portion where the electrode wiring of the large current driving element is to be formed on the semiconductor substrate on which the small current driving element and the large current driving element are formed; A method for manufacturing a semiconductor device, characterized in that electrode wiring is formed by sequentially performing a step of forming a metal layer in a portion where electrode wiring of a current drive element and a large current drive element is to be formed, in an arbitrary order. .