JPH05109657A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05109657A JPH05109657A JP27162791A JP27162791A JPH05109657A JP H05109657 A JPH05109657 A JP H05109657A JP 27162791 A JP27162791 A JP 27162791A JP 27162791 A JP27162791 A JP 27162791A JP H05109657 A JPH05109657 A JP H05109657A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- film
- gold
- barrier metal
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は金めっき法による配線形
成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method using a gold plating method.
【0002】[0002]
【従来の技術】従来の金めっき法による配線形成方法に
ついて、図3を参照して説明する。2. Description of the Related Art A conventional wiring forming method by gold plating will be described with reference to FIG.
【0003】はじめに拡散工程済みの半導体基板1の表
面の酸化膜3にコンタクト用の開口が形成されている。
つぎに酸化膜3および金と密着性の良いバリアメタル4
をスパッタ法などにより堆積する。つぎに配線パターン
以外を覆うフォトレジスト7をパターニングする。つぎ
にバリアメタル4の一端にめっき用電極8を接続し、め
っき液に浸漬して電圧を印加する。フォトレジスト7が
マスクとなって、配線パターンにのみ金めっき膜9が形
成される。このとき金めっき膜9の金が半導体基板1に
侵入するのを防ぐため、バリアメタル4にはチタンまた
はチタンおよび白金が用いられることが多い。First, an opening for contact is formed in the oxide film 3 on the surface of the semiconductor substrate 1 after the diffusion process.
Next, a barrier metal 4 with good adhesion to the oxide film 3 and gold
Are deposited by a sputtering method or the like. Next, the photoresist 7 which covers other than the wiring pattern is patterned. Next, the plating electrode 8 is connected to one end of the barrier metal 4 and immersed in a plating solution to apply a voltage. Using the photoresist 7 as a mask, the gold plating film 9 is formed only on the wiring pattern. At this time, titanium or titanium and platinum are often used for the barrier metal 4 in order to prevent gold of the gold plating film 9 from entering the semiconductor substrate 1.
【0004】[0004]
【発明が解決しようとする課題】金が半導体基板に侵入
するのを防ぐとともに、酸化膜との密着性を保つために
バリアメタルにはチタン、モリブデン、チタンおよび白
金の積層などが用いられる。In order to prevent gold from penetrating into the semiconductor substrate and to maintain adhesion with the oxide film, titanium, molybdenum, a stack of titanium and platinum is used as the barrier metal.
【0005】このバリアメタルは比較的に抵抗率が高い
上に、白金を除いて半導体基板の堆積したのちフォトレ
ジストを形成して配線パターンを開口したとき、わずか
に酸化膜を形成して一段と抵抗率が高くなってしまう。This barrier metal has a relatively high resistivity, and when a wiring pattern is opened by forming a photoresist after depositing a semiconductor substrate except platinum, a slight oxide film is formed to further improve the resistance. The rate becomes high.
【0006】白金でも結晶の状態によっては、抵抗率が
かなり高くなる状態がしばしば生じている。[0006] Even in platinum, a state in which the resistivity is considerably high often occurs depending on the crystalline state.
【0007】このような半導体基板にフォトレジストを
パターニングして開口にめっきしたとき、めっき用の導
電パスの役目を果すバリアメタルの抵抗が大きいので、
開口のめっき用電極に近い部分と遠い部分とで微妙に電
位が異なる。めっき速度が異なって、めっき膜の厚さに
ばらつきが生じることが多い。そのため素子間の電気的
特性にばらつきを生じてしまうという問題がある。When a photoresist is patterned on such a semiconductor substrate and the opening is plated, the resistance of the barrier metal, which plays the role of a conductive path for plating, is large.
The potential is slightly different between the portion near the plating electrode and the portion far from the opening. Different plating rates often cause variations in the thickness of the plated film. Therefore, there is a problem in that the electrical characteristics between the elements vary.
【0008】[0008]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板の一主面に密着性の良い金属膜を
堆積する工程と、前記金属膜の表面に金の薄膜を形成す
る工程と、前記金の薄膜に選択的に金めっきを行なって
低抵抗の金めっき膜からなる配線パターンを形成する工
程と、前記金めっき膜をマスクとして前記金の薄膜およ
び前記金属膜をエッチングする工程とを含むものであ
る。According to a method of manufacturing a semiconductor device of the present invention, a step of depositing a metal film having good adhesion on one main surface of a semiconductor substrate and forming a gold thin film on the surface of the metal film. A step of selectively gold-plating the gold thin film to form a wiring pattern of a low-resistance gold plating film; and etching the gold thin film and the metal film using the gold plating film as a mask And a process.
【0009】[0009]
【実施例】本発明の第1の実施例について、図1(a)
〜(c)を参照して説明する。EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (c).
【0010】はじめに図1(a)に示すように、複数の
素子領域2を有する拡散工程済みの半導体基板1に酸化
膜3を形成し、コンタクト用の開口を形成する。First, as shown in FIG. 1A, an oxide film 3 is formed on a semiconductor substrate 1 having a plurality of element regions 2 and subjected to a diffusion process, and an opening for contact is formed.
【0011】つぎにスパッタ装置に入れて、厚さ200
nmのモリブデンからなるバリアメタル4をスパッタす
る。モリブデンはめっき用導電パス、金と酸化膜との接
着材、金の半導体基板への侵入防止の3つの役目をもっ
ている。Next, it is put in a sputtering apparatus and a thickness of 200
A barrier metal 4 made of molybdenum of 4 nm is sputtered. Molybdenum has three functions: a conductive path for plating, an adhesive between gold and an oxide film, and prevention of gold from entering the semiconductor substrate.
【0012】つぎに同一のスパッタ装置内で連続して厚
さ50nmの薄い金膜4を堆積したのち、スパッタ装置
から取り出す。Next, after depositing a thin gold film 4 having a thickness of 50 nm continuously in the same sputtering apparatus, it is taken out from the sputtering apparatus.
【0013】つぎに図1(b)に示すように、金配線を
形成する領域に開口6を有するフォトレジスト7を形成
する。Next, as shown in FIG. 1B, a photoresist 7 having an opening 6 is formed in a region where a gold wiring is to be formed.
【0014】つぎに図1(c)に示すように、めっき液
に浸漬してめっき電流を流して配線パターンとなる金め
っき膜9を形成する。Next, as shown in FIG. 1C, the gold plating film 9 is formed by immersing in a plating solution and applying a plating current to form a wiring pattern.
【0015】つぎに本発明の第2の実施例について説明
する。Next, a second embodiment of the present invention will be described.
【0016】本実施例では図1(a)において、半導体
基板1にバリアメタル4を形成したのち、スパッタ装置
から取り出す。つぎに図2に示すようにめっき用電極8
を接続し、対向電極11とともにめっき液10に浸漬し
て、めっき電源12により強電界を印加してストライク
めっきを行ない、図1(a)に示す薄い金膜5を形成す
る。そのあと第1の実施例と同様の工程を経て、図1
(c)に示す金めっき膜9を形成する。In this embodiment, as shown in FIG. 1A, the barrier metal 4 is formed on the semiconductor substrate 1 and then taken out from the sputtering apparatus. Next, as shown in FIG.
Are connected to each other and are immersed in the plating solution 10 together with the counter electrode 11, and a strong electric field is applied by the plating power source 12 to perform strike plating to form the thin gold film 5 shown in FIG. After that, the same steps as those in the first embodiment are performed, and
The gold plating film 9 shown in (c) is formed.
【0017】[0017]
【発明の効果】バリアメタルの上に配線パターンとなる
フォトレジストを形成する前に、予め薄い金膜を形成す
る。そのためバリアメタルの酸化を防いで、抵抗率の増
大を食い止めることができる。そのうえ薄い金膜は抵抗
率が低いので、めっき用導電パスとしての抵抗率を大幅
に下げることができる。EFFECTS OF THE INVENTION Before forming a photoresist to be a wiring pattern on a barrier metal, a thin gold film is formed in advance. Therefore, the barrier metal can be prevented from being oxidized and the increase in resistivity can be suppressed. In addition, since the thin gold film has a low resistivity, the resistivity as a conductive path for plating can be significantly reduced.
【0018】その結果、金めっき用配線パターン間相互
の電位差は非常に小さくなり、均一な金めっき層が実現
できる。したがって素子間の電気的特性のばらつきを抑
えることができる。As a result, the potential difference between the gold plating wiring patterns becomes very small, and a uniform gold plating layer can be realized. Therefore, it is possible to suppress variations in electrical characteristics between elements.
【図1】本発明の第1の実施例を工程順に示す断面図で
ある。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.
【図2】本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【図3】従来の金めっき法による配線形成方法を示す断
面図である。FIG. 3 is a cross-sectional view showing a wiring forming method by a conventional gold plating method.
1 半導体基板 2 素子領域 3 酸化膜 4 バリアメタル 5 薄い金膜 6 開口 7 フォトレジスト 8 めっき用電極 9 金めっき膜 10 めっき液 11 対向電極 12 めっき電源 1 Semiconductor Substrate 2 Element Area 3 Oxide Film 4 Barrier Metal 5 Thin Gold Film 6 Opening 7 Photoresist 8 Plating Electrode 9 Gold Plating Film 10 Plating Solution 11 Counter Electrode 12 Plating Power Supply
Claims (1)
膜を堆積する工程と、前記金属膜の表面に金の薄膜を形
成する工程と、前記金の薄膜に選択的に金めっきを行な
って低抵抗の金めっき膜からなる配線パターンを形成す
る工程と、前記金めっき膜をマスクとして前記金の薄膜
および前記金属膜をエッチングする工程とを含む半導体
装置の製造方法。1. A step of depositing a metal film having good adhesion on one main surface of a semiconductor substrate, a step of forming a gold thin film on the surface of the metal film, and a step of selectively plating the gold thin film with gold. A method of manufacturing a semiconductor device, comprising: a step of forming a wiring pattern made of a low resistance gold plating film; and a step of etching the gold thin film and the metal film using the gold plating film as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27162791A JPH05109657A (en) | 1991-10-21 | 1991-10-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27162791A JPH05109657A (en) | 1991-10-21 | 1991-10-21 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05109657A true JPH05109657A (en) | 1993-04-30 |
Family
ID=17502714
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27162791A Pending JPH05109657A (en) | 1991-10-21 | 1991-10-21 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05109657A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003031586A (en) * | 2001-07-17 | 2003-01-31 | Toshiba Corp | Manufacturing method for array substrate, the array substrate, and liquid crystal display element |
WO2015033652A1 (en) * | 2013-09-05 | 2015-03-12 | オリンパス株式会社 | Semiconductor substrate and method for manufacturing same |
-
1991
- 1991-10-21 JP JP27162791A patent/JPH05109657A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003031586A (en) * | 2001-07-17 | 2003-01-31 | Toshiba Corp | Manufacturing method for array substrate, the array substrate, and liquid crystal display element |
WO2015033652A1 (en) * | 2013-09-05 | 2015-03-12 | オリンパス株式会社 | Semiconductor substrate and method for manufacturing same |
JP2015053339A (en) * | 2013-09-05 | 2015-03-19 | オリンパス株式会社 | Semiconductor substrate and manufacturing method of the same |
US9653416B2 (en) | 2013-09-05 | 2017-05-16 | Olympus Corporation | Semiconductor substrate and manufacturing method thereof |
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